July 5, 20031

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 20032

Integrated Circuit Design

# of Transistors

0.1M

1M

10M

100M

1000M

1980 1990 2000 2010 Year

55MHzMHz

11GHzGHz

1010GHzGHz

33.0.0µµmm 180180nmnm 4545nmnm

80868086

Pentium 4Pentium 4

Pentium III Pentium III with Cuwith Cu

8038680386

PentiumPentium

July 5, 20033

MOSFET Scaling

Same basic transistor design

2000 2005 2010 2015 20201

10

100

GAT

E LE

NGTH

(nm

)

YEAR

LOW POWER HIGH PERFORMANCE

ITRS 2001 Projection

Technology Scaling

Investment

Market Growth

Better Performance/Cost

The first transistor 1947

The Power4 microprocessor

July 5, 20034

Bulk-Si MOSFET• Leakage current is the primary barrier to scaling• To suppress leakage, we need to employ:

—Higher body doping " lower carrier mobility, higher junction capacitance, increased junction leakage

—Thinner gate dielectric " higher gate leakage

—Ultra-shallow S/D junctions " higher Rseries

Substrate

Gate

Source DrainLeff Nsub

Xj

LgTox

Desired characteristics:

High ON current (Idsat)# Low OFF current

G

SD

courtesy of Prof. Kuroda

Keio University

July 5, 20035

Issues for Scaling Lg to <25 nm

• Incommensurate gains in Idsat with scaling— limited carrier mobilities— parasitic resistance

• VT variation (statistical dopant fluctuations)

• Leakage

July 5, 20036

Advanced MOSFET Structures• Leakage can be suppressed by using a thin body

Ultra-Thin Body

GateGate

Silicon Substrate

Source Drain

TBOX

TSi

SiO2

SOI

Double Gate

Source Drain

Gate 1Gate 1 Vg

Tox

TSiSOI

Gate 2Gate 2

July 5, 20037

Thin-Body MOSFETs• Control short-channel effects with Tbody

— No channel doping needed!— Relax gate oxide (Tox) scaling

• Double-Gate is even more effective— Scalable to 10nm gate lengths

TbodyUltra-Thin Body Double-Gate

Gate

Source Drain

Gate

Buried Oxide

Substrate

Source Drain

Gate

July 5, 20038

Scaling DG MOSFETs

• Scaling limited by control of Ioff

• Reducing Tbodyimproves short-channel effects

• Using ITRS leakage spec, Lmin~10nm at limit of Tbody=5nm

[D. J. Frank et al. IEDM 1992]

5 10 15 20 25 30

10-8

10-7

10-6

10-5

Tbody=10nm

Tbody=5nmTbody=4nm

ITRS Ioff Target

I off [

A/µm

]

LGate [nm]Tox,eq=10Å, VDD/VT,long=0.6/0.2V,

S/D=1nm/dec, Lmet=Lgate

July 5, 20039

Electric Field Reduction• Reduced vertical

field in DG and UTB

— No doping =No Qdepl!

• Expected to benefit:— Mobility— Gate Leakage

Si

deplinveff ε

QQηE

+=

Gate

Buried Oxide

Substrate

Qinv

Thin-Body

Gate Qinv

QdeplBulk

July 5, 200310

• No channel doping needed!↑ Ion

↓ Cload

• But…body thickness may be limited

— Improved mobility•Lower vertical electric field•No impurity scattering

— Improved swing•Better control of SCE•Lower VT

— No depletion or junction capacitance

Bulk

Idra

in

Vgate

DG

In Thin-Body FETs…

July 5, 200311

Why is IG Important?

• Thin Tox improves SCE and Idsat

• Scaling limited by tunneling current— Can dominate off-state leakage

• Migration to high-κ dielectrics

Carriers tunnelfrom the

inversion layer into the gateSource Drain

Gate

Buried Oxide

July 5, 200312

Ultra-Thin Body IG• As much as 3x

reduction in IG

• Matches measured data

• Smaller improvement when Tox is thin

0 1x1013 2x1013

10-4

10-2

100

102

104

22.5

: Measured

SiO2

Bulk UTB (Tbody=10nm)

20

15

Tox=10

Gat

e Cu

rren

t Den

sity

JG (A

/cm

2 )Inversion Charge Density (cm-2)

( ) oxUTBbulk

oxUTB

oxbulktBB

tBUTB

tBbulk

UTBtunn

bulktunn eeAeA

J

J −−

−

−

∝∝,

,

July 5, 200313

Double Gate IG• As much as 4x

reduction in IG

• Symmetry cancels electric field

0 1x1013 2x1013

10-4

10-2

100

102

104 SiO2

Bulk DG (Tbody=25nm)

20

15

Tox=10

Gat

e Cu

rren

t Den

sity

JG (A

/cm

2 )

Inversion Charge Density (cm-2)Gate

Source Drain

Gate

July 5, 200314

UTB MOSFET Scaling

• Issues for bulk-Si MOSFET scaling obviated— Body does not need to be heavily doped— Tox does not need to be scaled as aggressively

• EOT can be 5% lower for same Ig however (L. Chang et al., IEDM 2001)

— Ultra-shallow S/D junction formation is not an issue

• Body thickness must be less than ~1/3 x Lg– Formation of uniformly thin body is primary

challenge– For TSi < 4 nm, quantum confinement & interface

roughness " Vt variation and degraded gmK. Uchida et al., IEDM 2002

July 5, 200315

Thin-Body MOSFET Challenges

• Formation of uniformly thin SOI— Thin body needed to control leakage

e.g. TSi = 5 nm for Lg = 10 nm— Quantum confinement effects are

significant

• Series resistance of S/D extensions— Ultra-abrupt S/D doping profiles needed— Ultra-low-contact-resistance Schottky S/D

technology needed for TSi < 5 nm• increased process complexity

July 5, 200316

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 200317

Double-Gate MOSFETsGate

Drain

GateGate 1

Gate 2Current flow

S

Planar DG MOSFET

FinFETVertical DG

MOSFET

S

S

D

D

D

Current flow

Current flow

Gate 1Gate 1 Gate 2

Gate 2

July 5, 200318

Double-Gate FinFET

• Rotation allows for self-aligned gates• Layout similar to standard SOI FET

Gate

Drain Drain

Gate

Drain

Gate

Source

Gate

Source

Source

Drain

Gate

PlanarDG-FET

90°Rotation FinFET

Gate

Source Drain

Gate

July 5, 200319

Experimental Goals• Demonstrate scalability

— Electron-beam + optical lithography

— UC Berkeley Microlab

Gate

Source Drain

• Demonstrate compatibility with existing processing tools— Viability for future CMOS technologies— Technology transfer to industry— Collaboration with AMD

July 5, 200320

Poly Gate Deposition/Litho

Gate EtchSpacer Formation

S/D Implant + RTASilicidation

FinFET Process FlowSiO2

SOI SubstrateFin Patterning

Si Fin

BOX

Poly

Resist

Si3N4Spacer

NiSi

July 5, 200321

FinFET Device Structure

• All features defined by optical lithography and aggressive trimming

Gate

Source

Drain

July 5, 200322

Short-Channel Effects

• Acceptable DIBL and subthreshold slope down to below 20nm Lgate

• Nearly ideal (60mV/dec) subthreshold slope at long Lgate

• NMOS better than PMOS due to slower As diffusion 0 20 40 60 80 100

0

40

80

120

160

0

40

80

120

160

NMOS PMOS

Wfin=26nm

DIB

L (m

V/V)

Subt

hres

hold

Slo

pe (m

V/de

c)Gate Length (nm)

July 5, 200323

10nm FinFET TEM

220ÅSiO2 cap

Lg=10nm

BOX

NiSi

Poly-Si

Si Fin

B. Yu et al., IEDM 2002

July 5, 200324

10nm FinFET I-V• Dual N+/P+ poly

gates:- Need VT control

• Low DIBLNMOS: 120 mV/V PMOS: 71 mV/V

• Good SCE despite thick Tox (27Å EOT) & Wfin (26nm)- Due to large S/D

doping gradient &spacer thickness

-1 0 110-9

10-7

10-5

10-3

10-9

10-7

10-5

10-3

NMOS PMOSS=101

mV/decS=125

mV/dec

Vd=1.2V

0.1V

Vd=-1.2V

Drai

n Cu

rren

t [A/µm

]

Gate Voltage [V]

-0.1V

July 5, 200325

-1 0 1 20.0

0.5

1.0

Out

put V

olta

ge [V

]

Input Voltage [V]

Lgate ~ 100nmWfin ~ 60nmVDD = 1VWp/Wn = 10/5 fins

FinFET Inverter

• Functional proto-type circuits

• Threshold voltage needs further optimization…

In Out

VDD

In Out

July 5, 200326

Recent FinFET Developments

• H2 annealing to smoothen fin sidewalls→ improved carrier mobility and

low-frequency noiseY.-K. Choi et al., IEDM 2002

• Metal gate electrodes— N+/P+ NiSi J. Kedzierski et al., IEDM 2002— Mo2N/Mo Y.-K. Choi et al., IEDM 2002

July 5, 200327

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 200328

VT: What CMOS Needs…

• Need symmetrical VT’s for proper CMOS operation

• Need low VT’s for speed

InputO

utp

ut

Inverter Response

VDD

VDD0

VIN=VTN

VIN=VDD-VTP

July 5, 200329

• Single gate material— VTn = -VTp = 0.4V

• N+/P+ Poly— VTn = -VTp = -0.2V

• For low body doping, desired ΦM values are:

~ 4.5 eV for NMOS~ 5.0 eV for PMOS

• Need two separate work functions for NMOS and PMOS!

Gate Work Function

4.2 4.4 4.6 4.8 5.0 5.2-0.2

0.0

0.2

0.4

0.6

0.8

1.0

4.95eV

VT=0.2V

4.52eVP+ P

oly

N+ Pol

y

VT=0.4V

VTn -VTp

Thre

shol

d Vo

ltage

[V]

Gate Workfunction [eV]

July 5, 200330

The Challenge:• Gate Work Function Engineering

— New materials: NiSi, Mo…

• Near-term solutions:

G

S D

G

Arbitrary Workfunction

(undoped channel)

AsymmetricDG

Channel Doping

G

S D

GN+ Poly

P+ Poly

G

S D

G

Midgap or N+/P+ Poly

July 5, 200331

Asymmetric Gate Offers Low Vt

• Vt determined by Tox & TSi

—sensitive to TSi variation10% σTSi ⇒ 15 mV σVt

$ Large Ey

" lower Idsat, higher GIDL

Source Drain

N+ SiN+ Si Vg

SOI

P+ SiP+ Si

• Dual n+/p+ gates can be used to adjust Vt of FinFET

5 10 15 200.0

0.1

0.2

0.3

0.4

Tox,eq=20A

Tox,eq=15A

Tox,eq=10A

Thre

shol

d Vo

ltage

[V]

Wfin [nm]

July 5, 200332

VT Control Implications

• Near-term solutions increase vertical electric field— Degraded performance— Increased gate leakage

∴ Need gate work functionengineering to realize fullbenefits of UTB and DG

July 5, 200333

Molybdenum ΦM Engineeringby Ion Implantation

% ΦM can be lowered by N+ implantation and thermal anneal∆ΦM increases with

% dose% energy

(N segregates to SiO2interface & forms Mo2N)

Anneal time = 15m except for 900oC (15s)TMo = 15nm

P. Ranade et al., IEDM 2002

July 5, 200334

Mo-Gated FinFETs (PMOS)Y.-K. Choi et al., IEDM 2002

-0.8 -0.6 -0.4 -0.2 0.0 0.210-13

10-11

10-9

10-7

10-5

10-3

Drai

n Cu

rren

t, Id

[A/u

m]

Gate Voltage, Vg[V]

Mo MoN(N2=5x1015cm-2)

Vt shift

Lg=80nm, TSi=10nmVds=0.05V

• Alternative technique:Full silicidication (NiSi) of n+/p+ Si gates(J. Kedzierski et al., W. Maszara et al., Z. Krivokapic et al., IEDM 2002)

• |Vt|=0.2V for lightly doped body, and is adjustableby N+ implantation

Potential issues include: - dopant penetration- thermal stability - stress/adhesion- gate dielectric reliability

July 5, 200335

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 200336

Orientation Effects

• Rotation by 45º changes orientation from (110) to (100)— Intermediate rotation similar to (111)

<100>

<110>

(110)Surface

Gate

Sour

ceDr

ain

(110) (100)

~(111) (110)

July 5, 200337

FinFET Mobility

0.0 0.2 0.4 0.60

500

1000 (100) Takagi '94 (110) Takagi '94 (110) Measured

Wfin~65nm

Elec

tron

Mob

ility

(cm

2 /Vs)

Effective Field [MV/cm]

• Fin orientation is (110)— Electron mobility is degraded— Hole mobility is enhanced

0.0 0.2 0.4 0.6 0.80

100

200

300

(100) Takagi '94 (110) Measured

Wfin~65nm

Hole

Mob

ility

[cm

2 /Vs]

Effective Field [MV/cm]

July 5, 200338

0.2 0.4 0.6 0.8 1.00

100

200

300

400

500Oxynitride

(111)

(110)

(100)

Elec

tron

Mob

ility

[cm

2 /Vs]

Effective Field [MV/cm]0.2 0.4 0.6 0.8 1.0

0

100

200

300

400

500Oxynitride

(111)

(110)

(100)

Hole

Mob

ility

[cm

2 /Vs]

Effective Field [MV/cm]

How Mobility Changes

• By shifting away from (100):— µe is degraded, µh is enhanced

• Can we benefit from changing the N/P ratio?

July 5, 200339

0

5

10

15

20

Oxynitride

Fanout=4

% D

elay

Spe

edup

vs.

(100

)

Orientation(100) (111) (110) (100) NMOS

(110) PMOS

↑µh, ↓µe

NAND

Inv

NOR

Gate Delay• PMOS enhancement

(20%) is larger than NMOS degradation (8%)

— Net delay improvement

• Trade off µh and µe

— NOR: PMOS stack• µh very important• Most improvement

— NAND: NMOS stack• µh less important• Least improvement

Lgate=35nm

July 5, 200340

Optimized FinFET

• Trade off layout area for performance

Gate

Source

Drain

Source

Drain

Gate

Source

Drain

SourceDrain

(100) NMOS(110) PMOS

July 5, 200341

FinFET Layout Area

• Non-(100) orientation saves area— Higher PMOS Idsat reduces drawn W

• 45º orientation is less area efficient for smaller W— These devices are small anyway…does it matter?— Use only in critical path?

0.0

0.2

0.4

0.6

0.8

(100) (110) (111) 45oN / 90oP 90oN / 45oP

Idsatn,p=1.1mA

Layo

ut A

rea

[µm

2 ]0

10

20

30

40

50

Idsatn,p=110mA

Layo

ut A

rea

[µm

2 ]

Inverter

July 5, 200342

Concerns…

• Current designs emphasize NAND stacks because NMOS is much faster than PMOS—Widespread use of dynamic gates—Will we need to change our design methodology

if we equalize NMOS and PMOS devices?• Use more NOR stacks

• Interface traps and surface roughness in non-(100) surfaces—May not impact reliability—May not significantly affect VT, Swing, µ

H. S. Momose, et al., VLSI ‘01

July 5, 200343

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 200344

SDG vs. ADG (ION)

•Higher ON current for SDG due to lower vertical E-field (higher mobility)

•Fan-out of 4 structure is simulated by using ISE mixed-mode simulation

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

10-8

10-7

10-6

10-5

10-4

10-3

VGS (V)

NMO

S I DS

(A/µ

m)

0.0000

0.0004

0.0008

0.0012

Lgate = 25 nm

Log

Linear

SDG ADG

July 5, 200345

SDG vs. ADG (Inverter Delay)

0

5

10

15

20

25

30

35

Inve

rter

Del

ay, t

pd (p

s)

FO-1 FO-2 FO-3 FO-4

SDG ADG

0

20

40

60

80

100

(tpd, ADG - tpd, SDG ) / tpd, SDG

•Intrinsic Delay (w/o Cload)

•The SDG maintains a 10~20% inverter delay improvement over the ADG

July 5, 200346

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 200347

Multiple-Gate SOI

! Single-gate -> PDSOI, FDSOI, UTB (?) Tsi<1/3Lg

! Double-gate -> FinFET, Vertical (?), Planar (?)

Width < 2/3Lg, H no limit

! Triple-gate -> Width < ~Lg, Lower H (Intel)

Pi (π)-gate, Omega (Ω) gate

Compatible Performance to Quad-gate, but easier fabrication (Modeling Problem)

! Quadruple-gate (surrounding-gate)

-> BEST Control, Hard to Fabricate (?)

July 5, 200348

Outline! Introduction

— Why Double-Gate?

! Review of Double-Gate Devices— Device fabrication— Threshold voltage control— Surface orientation effects— SDG vs. ADG

! Multiple-Gate!?

! Compact Model of DG

! Summary

July 5, 200349

DG MOSFET Model Directions

! Close collaboration with work done at UCSD

! Based on the same core of the new BSIM Surface Potential Plus (SPP) model

! Modular with some elements co-developed together with the bulk BSIM model

! Inherent features from the BSIM model (e.g. unified velocity saturation model)

! New core features unique to DG MOSFETs at very small dimensions

July 5, 200350

Outline

! Framework for Symmetric and Asymmetric DG MOSFET based on the Surface Potential Plus (SPP) approach

! Preliminary threshold voltage model (Incorporate SCE and QM effects from Task 2)

! Concept of extending charge formulation from bulk to DG MOSFET (e.g. consider the volume inversion effect)

! Initial implementation of the model in MDE format

July 5, 200351

From Physics to Engineering! Physical formulation is elaborately done in task 2

! Computational efficiency requirement in compact model

! Fast incorporation of many physical effects (body doping, velocity saturation, velocity overshoot, Symmetric vs. Asymmetric, etc.)

! Compatibility with mainstream modeling understanding and approaches

! Extendibility to include non-ideal effect

! SPP core is adopted with QM and SCE correction

# Consideration in this task

July 5, 200352

Initial assumptions in SPP core! Quasi-Fermi potential is constant along the

vertical direction! 2 channels are distinguishable and can be

combined by superposition! No current exchange between the 2 channels

VG VG

Quasi-Fermi potential

Source Drain

Gate

Gate

July 5, 200353

CSi

ψS1

Cox2

Cox1

ψS2

VG1

VG2

y

x

Formulation of Core Equations [1]

two boundary conditions)()( 121111 ssSiisgox ddCdQddVC ψψψ −−=−

)()( 122222 ssSiisgox ddCdQddVC ψψψ −+=−

chsi

i dVdqdq

−= 11

1 ψ( ) ( ) ( )[ ]yVyexpqyq chsii −= 1101 ψ

( ) ( ) ( )[ ]yVyexpqyq chsii −= 2202 ψchs

i

i dVdqdq

−= 22

2 ψ

differentiation

normalized inversion charge in the channel

Assume Quasi-Fermi potential Vch(y) is contact along the x-direction

# charge formulation (with the help from Prof. Yuan Taur)

July 5, 200354

))(())(1(2

2

11

1

111

i

i

ox

si

i

i

ox

sichGi q

dqCC

qdq

CCdVdVdq ++−−=

))(())(1(1

1

22

2

222

i

i

ox

si

i

i

ox

sichGi q

dqCC

qdq

CCdVdVdq ++−−=

Note: qi1 is the charge normalized by Cox1Vthand qi2 is normalized by Cox2Vth

Formulation of Core Equations [2]

# eliminating ψS1 and ψS2 , we have

# rearrangement terms

( ) ( )1

111211211 11

i

ichGGii q

dqndVndVndVdqndq −−−+=−+

( ) ( )2

222212212 11

i

ichGGii q

dqndVndVdVndqdqn −−+−=+−

where

( )Sioxox

Siox

CCCCCn+

+=21

21 1

two coupled equations ( )Sioxox

Siox

CCCCCn+

+=12

12 1

July 5, 200355

Formulation of Core Equations [3]#combining qi1 and qi2 to evaluate the current

∫ +=D

Sch

iiDS dydy

dVqqL

WI ))(()( 21µ

( )

−

−+

−+−−++

−+

−= DDSSDDSS

DSDS qqqqn

nn

nqqqqn

qqnqq

LW

21212

2

1

12121

2

22

22

1

21

21

21

21

22µ

•where q1S, q2S (Vch=0) and q1D, q2D (Vch= VDS) are solved by integrating the two coupled equations

( ) ( )

−−−

−+−+=

1

21

1

21101

111

11)(exp11lnn

qnVn

VnVVn

nq ich

GTGi

( ) ( )

−−−

−+−+=

2

12

2

12202

222

11)(exp11lnn

qnVn

VnVVn

nq ich

GTGi

# need iteration to solve for qi1 and qi2

drift diffusion coupling

July 5, 200356

Threshold Voltage Formulation [1]( ) ( )

−−−

−+−+=

1

21

1

21101

111

11)(exp11lnn

qnVn

VnVVn

nq ich

GTGi

( ) ( )

−−−

−+−+=

2

12

2

12202

222

11)(exp11lnn

qnVn

VnVVn

nq ich

GTGi

−

−+= ch

TGi V

nVVnq

1

1111 exp1ln

−

−+= ch

TGi V

nVVnq

2

2222 exp1ln

•where VT1 and VT2 are given by

( ) ( ) 2121101 11 iGTT qnVnVV −+−−=

( ) ( ) 1212202 11 iGTT qnVnVV −+−−=

want approximate solution to qi1 and qi2

July 5, 200357

Threshold Voltage Formulation [2]

Si

SiaSiSSS

tqNtEε

ψψ2

2

112 +−=

# VT formulation

and ( )Si

SfbGoxS

VVCE

εψ 1111

1

−−=

•note that effect of doping is included in the VT expression•using the above boundary conditions and solve the 1D Poisson

equation, we have

1

222

1

2

0

211 1)(2

ox

sia

sifbG

oxIfbT C

tqNCCVV

CC

CCVV

++−−+= ψ

where210

1111

oxsiox CCCC++=

siox CCC111

11

+=siox CCC

111

22

+=; ;

ψI is the surface potential that causes inversion (=2φB for doped channel)

•consider back channel accumulated, depleted and inverted•boundary conditions at the 2 interfaces in depletion

July 5, 200358

-1.0 -0.5 0.0 0.5 1.00.25

0.30

0.35

0.40

0.45

0.50

0.55

Region 3Region 2Region 1

V th1 (

V)

VG2 (V)

# three region, back gate 1. accumulation

2. depletion 3. strong inversion

Threshold Voltage Formulation [3]•at back-side accumulation and inversion, the back surface

potential is more or less fixed at ψA, and ψI. The back-gate voltage has small impact on the front side threshold voltage

•3 regions of back gate coupling is modeled

July 5, 200359

Including SCE and QM Effects

! Details have been presented in Task 2 deliverables

! SCE included in ∆VT as a function of dimensions and drain bias

! QM included in ∆VT and as a correction to Tox

! Volume inversion mainly affects the subthreshold current and is included in the offset voltage term in the subthreshold region

July 5, 200360

Quantum Mechanical Correction# For QM, two parts are implemented (from task 2)

! Vth shift in subthreshold region

0.0 0.5 1.0 1.510-12

1x10-9

1x10-6

1x10-3

1x100

Mob

ile C

harg

e Sh

eet D

ensi

ty (1

0-6C/

cm2 )

Gate Voltage (V)

Classical QM 0

1

2

3

4

5

2. slope=C(Vg) degradation

1. Vt Shift

−∗

+∆−∆

∗+=∆m

sisioxsiTQM t

Ctt

BtAV exp

612

2φφ

• A, B, C, and m are fitting parameters.• and are work function difference

between gate electrode and silicon film.1φ∆ 2φ∆

! Mobile charge slope C(Vg) degradation

Distance (nm)

Elec

tron

Den

sity

10

total

86420

Tinv

si

ginv

ox

ox

g

VTtVC εε 2

)(2)(

1+=

)(1

)(1

)(1

21 sissiinv tfEgtfT+=

−

)16ln)(exp()( 21

21

11 CBtAtf si

si−−=

)exp()( 222 BtAtf sisi =

)exp()( 210 DEDDEg ss −+=

)exp( 43 DED s−+

Tinv only depends on EsTsi

July 5, 200361

Short-Channel Effect Correction

12/

21

1

11

21

11

2112min

)2

(1

))/2sin()/sin(

2()/cos(

)2

)(2

sin(4

222λπ

φφψλπλπλππ

φφψλ

πλφφ

εεφφψ L

gbi

dsgbi

g

I

sie

V

V

tt

WWt

VW

VW

tW

−

−∆+∆++

+

−∆+∆++

∆+∆−+

+

∆−∆=

# Calculated from shift in the minimum channel potential (Task 2)

Threshold voltage shift from long channel value due to SCE is then given by

The threshold voltage model is then given by

TSCETQMox

sia

sifbG

oxIfbT VV

CtqN

CCVV

CC

CCVV ∆−∆+

++−−+=

1

222

1

2

0

211 1)(2ψ

TSCETQMox

sia

sifbG

oxIfbT VV

CtqN

CCVV

CC

CCVV ∆−∆+

++−−+=

2

111

2

1

0

122 1)(2ψ

12

21

1

11

21

1

1

2

1

22

224

λπ

φ∆φ∆ψλπλπλπ

φ∆φ∆ψλπ

πλ

ψ∆∆ /L

gbi

ds

ii

siSii

gbisi

minTSCE e)V(

V

)t)/tsin()/tsin(t()/tcos(

)V)(tsin(V −

−+

++

+

−+

+==

July 5, 200362

Volume Inversion Modeling [1]# For DG MOSFETs with intrinsic channel doping, volume inversion

is valid and needed to be considered in the charge calculation

Intrinsic Channel DopingVolume Inversion

High Channel DopingReduced Volume Inversion

Ec

Ei=Ef

Ev

Vg=0

Ec

Ei

Ef

Ev

Vg=Vt

Ef

Ec

Ev

Vg=Vt

ψs 0ψs

Ef

Ef

Vg

Vg

Ec

Ev

Vg=0

Ef

S/D fermilevel

July 5, 200363

0.0 0.2 0.4 0.6 0.8 1.0

0.0

0.1

0.2

0.3

0.4

0.5

0.6 Nsub = 1015 cm-3

ϕs0, 10nm ϕs, 10nm ϕs0, 20nm ϕs, 20nm

Elec

tric

Pote

ntia

l (V)

Gate Voltage (V)0.0 0.2 0.4 0.6 0.8 1.0

1E-15

1E-13

1E-11

1E-9

1E-7

1E-5

Tsi

Nsub = 1015 cm-3

Tsi = 10 nm Tsi = 20 nm

Inve

rsio

n ch

arge

she

et d

ensi

ty (C

/cm

2 )Gate Voltage (V)

1. For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region.

2. The inversion charge (current) in the subthreshold region is proportional to Tsi.

Volume Inversion Modeling [2]

July 5, 200364

0.0 0.2 0.4 0.6 0.8 1.0

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6 Nsub = 1018 cm-3

ϕs0, 10nm ϕs, 10nm ϕs0, 20nm ϕs, 20nm

Elec

tric

Pote

ntia

l (V)

Gate Voltage (V)0.0 0.2 0.4 0.6 0.8 1.0

1E-16

1E-14

1E-12

1E-10

1E-8

1E-6

Tsi

Nsub= 1018 cm-3

Tsi = 10 nm Tsi = 20 nm

Inve

rsio

n ch

arge

she

et d

ensi

ty (C

/cm

2 )Gate Voltage (V)

1. For high channel doping, volume inversion will reduce for thicker Tsi in the subthreshold region.

2. The inversion charge (current) in the subthreshold region is inversely proportional to Tsi due to threshold voltage shift

Volume Inversion Modeling [3]

July 5, 200365

Volume Inversion Modeling [4]# Expression for volume inversion

( )( )

−−−

+

−−+

=

th/

)/(off/T/G

Si

/ox/

th/

ch/T/Gth/

/i

VnVmVV

expC

Cnm

VnVVVmexplnVn

q

21

2121212121

21

212121

21 1

1

2/102/1 offoffoff VVV ∆+=

∆−∆

+=∆thox

SithA

i

thoff VC

tVN

nqVnV

2/1

1/22/12

2/12/1

2exp

1ln

φφ

0.0 0.2 0.4 0.6 0.8 1.01E-14

1E-12

1E-10

1E-8

1E-6

1E-4

Tsi=20nm

Tsi=10nm

Nsi=1015cm-3 Tsi=10nm Nsi=1015cm-3 Tsi=20nm Nsi=1018cm-3 Tsi=10nm Nsi=1018cm-3 Tsi=20nm

Gate Voltage (V)

Drai

n Cu

rren

t (A/µm

)

0.0000

0.0001

0.0002

0.0003

Lg = 100 nm! Subthreshold current will be a

function of Tsi, Nsi, and work-function difference between the front and back gate

July 5, 200366

Preliminary I-V Expressions [1]# Effects included

! Symmetric and Asymmetric DG MOSFET with intrinsic and doped body

! Front and back channel coupling

! Quantum Mechanical correction to VT and Cox

! SCE correction to VT (in progress)

! Volume inversion in subthreshold region

! Universal mobility model

! Unified current saturation model

July 5, 200367

Preliminary I-V Expressions [2]# I-V expressions

( ) ( ) ( ) ( )

−+

−+

−+

−= 22

22

22

22

1221111

21

21

21121 22 dsth

ox

dsvsattheffdsth

ox

dsvsattheff

vsatvsatds qqV

CnqqfqqV

Cnqqf

LWI ξθµξθµξξ

( )

( )

−+

−

−+

+−

=

2/12/1

22/1

22/1

2/1

2/12/1

2/12/12/12/1

2/1

2

111

dsthox

dss

oxsat

dssths

th

qqVnC

qqW

LCvnqqLv

rrq

µ

µ

θ( ) [ ] mmththf 2/121/1 −+= θθwhere with

( )

−+=

satox

dseffvsa vLCn

qq

2/12/1

2/12/12/12/1 1

µξand

# Charge expression

( )( )

−−−

+

−−+

=

th

offTG

Si

ox

th

chTGth

i

VnVmVV

CCnm

VnVVVmVn

q

2/1

2/12/12/12/12/1

1

2/12/12/1

2/1 1exp

exp1ln

and

∆−∆

++=thox

SithA

i

thoffoff VC

tVN

nqVnVV

2/1

1/22/12

2/102/1

2exp

1ln

φφ

July 5, 200368

Preliminary I-V Expressions [3]# Universality of the I-V expressions

! with the constant vertical quasi-Fermi potential assumption, the I-V model is valid as long as the charge at the source and drain are known

! The current charge formulation represent a tradeoff between computational efficiency, physical accuracy, flexibility due to uncertain physics, and compatibility with existing modeling methodologies

! When more accurate charge models are fully formulated and derived, they can be incorporated into the existing framework

July 5, 200369

Output of Model from MDE Codes

July 5, 200370

Model Verifications# Model verification to AMD symmetric nFinFETs

0.0 0.5 1.010-9

10-8

10-7

10-6

10-5

10-4

Lg=105nm Tsi= 26nm

VD=0.1V Data VD=1.2V Data MDE simulation results

Gate Voltage (V)

Drai

n Cu

rren

t (A)

0.0 0.5 1.010-8

10-7

10-6

10-5

10-4

Lg=80nm Tsi= 26nm

VD=0.1V Data VD=1.2V Data MDE simulation results

Drai

n Cu

rren

t (A)

Gate Voltage (V)0.0 0.5 1.010-8

10-7

10-6

10-5

10-4

Lg=55nm Tsi= 26nm

VD=0.1V Data VD=1.2V Data MDE simulation results

Drai

n Cu

rren

t (A)

Gate Voltage (V)

Lg= 105nm Lg= 80nm Lg= 55nm

July 5, 200371

Limitation of the 1-D Current Equation

-500

50

1.5

1.0

0.5

-5

0

5Elec

tric

Pote

ntia

l (V)

Y axis (nm) X axis (nm)

Je1

Je2

Source

Drain -15-10

-50

510

15

1.5

1.0

0.5

-5

0

5

Elec

tric

Pote

ntia

l (V)

X axis (nm)Y axis (nm)

Je1

Je2

Source

Drain

Lg=100nm, Tsi=10nm, Nsi=1015cm-3 Lg=25nm, Tsi=10nm, Nsi=1015cm-3

July 5, 200372

2-D Current Flow Near the Drain

! dVch/dx = 0 is not valid near the drain end in the velocity saturation/overshoot region

! 2-D current effects are insignificant in long channel devices and in the gradual channel region

! It is important for impact ionization current!

! Some modifications for drain saturation charge calculation might be needed to capture this effect

July 5, 200373

Summary• Thin-body FETs can extend scaling to ~10nm

— Speed and power improvement— Reduction of gate leakage

• FinFET allows practical implementation of the DG structure— Enables surface orientation optimization— …But challenges exist: VT control

• Preliminary compact model of the DG MOSEFET is implemented in the C-code.