Analog Functional Testing in Analog Functional Testing in MixedMixed--Signal SystemsSignal Systems

JieJie QinQinDept. of Electrical & Computer EngineeringDept. of Electrical & Computer Engineering

Auburn UniversityAuburn University

CoCo--Advisors: Charles Stroud and Foster DaiAdvisors: Charles Stroud and Foster Dai

2

OutlineOutline

��Motivation and BackgroundMotivation and Background

��BuiltBuilt--In SelfIn Self--Test ArchitectureTest Architecture

��Design of Device Under Test (DUT)Design of Device Under Test (DUT)

��Experimental ResultsExperimental Results

��Conclusions and Future ResearchConclusions and Future Research

3

MotivationMotivation��Analog circuits are typically measured manuallyAnalog circuits are typically measured manually

��Cost and time inefficientCost and time inefficient

�� It is not easy to measure analog circuits in It is not easy to measure analog circuits in systems systems ��Lack of accessibilityLack of accessibility

��Performance variation caused by test equipmentPerformance variation caused by test equipment

��MixedMixed--Signal BuiltSignal Built--In SelfIn Self--Test (BIST) is promisingTest (BIST) is promising��Automated testing sequenceAutomated testing sequence

��InIn--system measurements with available resourcessystem measurements with available resources��Calibration and adaptive controlCalibration and adaptive control

44

Frequency Response MeasurementFrequency Response Measurement

�� Generate a tone to Generate a tone to stimulate the device under stimulate the device under test (DUT)test (DUT)

�� Monitor the output and Monitor the output and perform spectrum analysisperform spectrum analysis

�� Sweep the tone over the Sweep the tone over the whole interested bandwhole interested band

Amplifier Transfer

Function

Test tones generated using DDS

Frequency

Magnitude

�� Almost the most popular and important analog functional Almost the most popular and important analog functional measurementmeasurement

�� Can be performed through single tone testCan be performed through single tone test

55

Nonlinearity MeasurementNonlinearity Measurement

�� Generate two tones with close frequency spacing to stimulate Generate two tones with close frequency spacing to stimulate the device under test (DUT)the device under test (DUT)

�� Monitor the output of the DUT and perform spectrum analysisMonitor the output of the DUT and perform spectrum analysis

�� ThirdThird--order intercept point (IP3) is one of the most order intercept point (IP3) is one of the most important nonlinearity measuresimportant nonlinearity measures

�� Can be measured through a twoCan be measured through a two--tone testtone test

2 4 6 8 10 12 14 16 18 200 22 24

f2 – f12f1 – f2 2f2 – f1

f1 f2

f1 + f2

2f1 2f2

3f1 3f2

66

Noise MeasurementNoise Measurement�� Noise Figure (NF) is a measure of the noise generated by Noise Figure (NF) is a measure of the noise generated by

a device itselfa device itself�� Defined as the ratio of the input signalDefined as the ratio of the input signal--toto--noise ratio (noise ratio (SNRSNRinin) to ) to

output output SNRSNRoutout

�� Can be measured through a oneCan be measured through a one--tone SNR measurementtone SNR measurement�� Generate a tone to active the Generate a tone to active the

DUTDUT

�� Monitor the output of the DUT Monitor the output of the DUT at the whole interested bandat the whole interested band

�� The noise level can be The noise level can be obtained with the signal level obtained with the signal level as a reference pointas a reference point

7

Requirements for BISTRequirements for BIST��Goals for mixedGoals for mixed--signal BISTsignal BIST

��Extract the frequency spectrum information from DUTExtract the frequency spectrum information from DUT11

response forresponse for��Frequency ResponseFrequency Response��Linearity MeasurementLinearity Measurement��Noise MeasurementNoise Measurement

��Implementation using simple circuitryImplementation using simple circuitry��Small area penalty Small area penalty ��Minimal performance penalty to analog circuitry.Minimal performance penalty to analog circuitry.

��Conventional way to obtain frequency spectrum is Conventional way to obtain frequency spectrum is FFTFFT22

��High area penaltyHigh area penalty��High power consumptionHigh power consumption

1.1. DUT: Device Under TestDUT: Device Under Test2.2. FFT: Fast Fourier TransformFFT: Fast Fourier Transform

8

Proposed BISTProposed BIST��Proposed BIST approach usesProposed BIST approach uses

��DDSDDS11--based Test Pattern Generator (TPG)based Test Pattern Generator (TPG)��Can generate various stimuli required forCan generate various stimuli required for

��Frequency ResponseFrequency Response

��Linearity MeasurementLinearity Measurement

��Noise Measurement Noise Measurement

��MACMAC22--based Output Response Analyzer (ORA)based Output Response Analyzer (ORA)��Can be realized in a much simpler, cheaper and Can be realized in a much simpler, cheaper and

more flexible circuitmore flexible circuit��compared with the FFTcompared with the FFT--based ORA based ORA

1.1. DDS: Direct Digital SynthesizerDDS: Direct Digital Synthesizer2.2. MAC: Multiplier/MAC: Multiplier/ACcumulatorACcumulator

9

DDSDDS--based TPGbased TPG��NCONCO11 generates a digitized sinusoidal waveformgenerates a digitized sinusoidal waveform

��Frequency word Frequency word ffw and initial phase word hase word θθθθw

��Phase truncation for smaller LUTPhase truncation for smaller LUT22 sizesize

��TPG consists of 3 NCOs TPG consists of 3 NCOs ��Required for test stimuli and ORA Required for test stimuli and ORA

Z-1

n

n nfw

θθθθw

fclk=1/Tclk

Phase Accumulator

n

n PhaseTruncation

sin/cosLUT

sin(2ππππfnTclk+θθθθ)p

'

2w clk

n

f ff

⋅=

1.1. NCO: Numerically Controlled OscillatorNCO: Numerically Controlled Oscillator2.2. LUT: LookLUT: Look--Up Table Up Table

Basic Structure of NCOBasic Structure of NCO

10

MACMAC--based ORAbased ORA

2DC ( ) sin( )clk clkn

f nT nTω= ⋅∑1DC ( ) cos( )clk clkn

f nT nTω= ⋅∑

Accm1

Accm2

DC1

DC2

MUL1

MUL2

cos(nωωωωTclk)

sin(nωωωωTclk)

f(nTclk)Output Response Analyzer (ORA)

�� ORA performs spectral analysis with only two ORA performs spectral analysis with only two MACsMACs�� One MAC for inOne MAC for in--phase while the other for outphase while the other for out--ofof--phasephase

22

21)( DCDCA +=ω 1 2

1

( )( )

( )

DCtg

DC

ωφ ωω

−∆ =

�� Magnitude response A(Magnitude response A(ωω) and phase delay ) and phase delay ΔΔΦΦ((ωω))

�� Analysis is done at one frequency at a timeAnalysis is done at one frequency at a time

��Sweep the whole interested Sweep the whole interested band to capture the complete band to capture the complete spectrumspectrum

��Much more efficient in terms Much more efficient in terms of hardware resources of hardware resources compared with FFTcompared with FFT--based based ORAORA

11

Phase Delay in MACPhase Delay in MAC--based ORAbased ORA��To build To build arctanarctan LUT to calculate LUT to calculate ΔΔΦΦ((ωω)) for onfor on--chip chip

teststests��LUT can be reduced to value range of LUT can be reduced to value range of ΔΔΦΦoo (0(0°° to 45to 45°°))

211 2

1

111 2

2

( )( ) ( )

( )( )

( )( ) ( )

( )

o

DCtg DC DC

DC

DCtg DC DC

DC

ωω ω

ωφ ω

ωω ω

ω

−

−

≥

∆ = ≤

|DC|DC11||≥≥≥≥≥≥≥≥| DC| DC22|| |DC|DC11||≤≤≤≤≤≤≤≤| DC| DC22||

DCDC11>0; DC>0; DC22>0>0 ∆φ(ω∆φ(ω)) ==∆φ∆φοο(ω(ω)) ∆φ(ω∆φ(ω)) =90=90°°−−∆φ∆φοο(ω)(ω)

DCDC11>0; DC>0; DC22<0<0 ∆φ(ω∆φ(ω)) =360=360°°−−∆φ∆φοο(ω)(ω) ∆φ(ω∆φ(ω)) =270=270°°++∆φ∆φοο(ω)(ω)DCDC11<0; DC<0; DC22>0>0 ∆φ(ω∆φ(ω)) =180=180°°−−∆φ∆φοο(ω)(ω) ∆φ(ω∆φ(ω)) =90=90°°++∆φ∆φοο(ω)(ω)DCDC11<0; DC<0; DC22<0<0 ∆φ(ω∆φ(ω)) =180=180°°++∆φ∆φοο(ω)(ω) ∆φ(ω∆φ(ω)) =270=270°°−−∆φ∆φοο(ω)(ω)

��LUT can be further compressedLUT can be further compressed�� When DC2/DC1 is very small, When DC2/DC1 is very small, arctan(arctan(DC2/DC1) can be approximated by DC2/DC1) can be approximated by

DC2/DC1DC2/DC1�� Taylor Series ExpansionTaylor Series Expansion

12

Magnitude Response in MACMagnitude Response in MAC--based ORAbased ORA�� Once phase delay is obtained, Once phase delay is obtained, A(A(ωω)) can be calculated 3 can be calculated 3

different ways: different ways: �� Approach #1Approach #1

�� Approach #2Approach #2

�� Approach #3Approach #3

( )( ) ( ) ( ) cos( ( ))jclk clk

n

A F e f nT nTφ ωω ω ω φ ω− ∆= = ⋅ −∆∑

)(sin)(cos)( 21

ωφωφω

∆=

∆= DCDC

A

22

21)( DCDCA +=ω

1DC ( ) cos( )clk clkn

f nT nTω= ⋅∑

ApproachApproach # 1# 1 # 2# 2 # 3# 3

HardwareHardwareoverheadoverhead lowlow highhigh highhigh

Test timeTest time longlong shortshort shortshort

ConstraintsConstraintscannot be used for noise cannot be used for noise

measurementmeasurementnonenone nonenone

PropagationPropagationerrorerror yesyes yesyes nonenone

Pros and Cons of 3 approaches

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BuiltBuilt--In SelfIn Self--Test ArchitectureTest Architecture

��Number and location of Number and location of MUXsMUXs in analog systemin analog system��determines accuracy of functional measurementsdetermines accuracy of functional measurements

Test Controller

MU

X1

MU

X2

NCO1

NCO2

NCO3

Sin(2ππππf1’nTclk+θθθθ1)f1

’, θθθθ1

Sin(2ππππf2’nTclk+θθθθ2)f2

’, θθθθ2

f3’, θθθθ3 Sin(2ππππf3

’nTclk+θθθθ3)

DAC

DUTMU

X3

ADC

MUX4

Accm1

Accm2

DC1

DC2

MUL1

MUL2

f1(nTclk)

f2(nTclk)

f(nTclk)Test Pattern Generator (TPG)

Output Response Analyzer (ORA)

Amp

14

AnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalog

CircuitCircuitCircuitCircuitCircuitCircuitCircuitCircuit

AnalogAnalog

SystemSystem

InputsInputs

ADCADCADCADCADCADCADCADCSystemSystem

FunctionFunction

DigitalDigital

SystemSystem

OutputsOutputs

AnalogAnalog

SystemSystem

OutputsOutputs

SystemSystem

FunctionFunction

DigitalDigital

SystemSystem

InputsInputs

DigitalDigital

CircuitryCircuitry

DACDACDACDACDACDACDACDAC

AnalogAnalog

CircuitryCircuitry

AnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalog

CircuitCircuitCircuitCircuitCircuitCircuitCircuitCircuit

BIST for MixedBIST for Mixed--Signal SystemsSignal Systems

ORAORAORAORAORAORAORAORA

TPGTPGTPGTPGTPGTPGTPGTPG

TestTestTestTestTestTestTestTest

ControlControlControlControlControlControlControlControl

MuxMux

AnalogAnalogMUXMUXBIST DoneBIST Done

BIST StartBIST Start

ResultResult

101011000111011010101011000111011010

101011000111011010101011000111011010

��Digital circuitry tests analog circuitryDigital circuitry tests analog circuitry��Minimize impact to analog circuitryMinimize impact to analog circuitry

��Use existing DAC/ADC in mixedUse existing DAC/ADC in mixed--signal systemsignal system

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Test and Evaluation of BISTTest and Evaluation of BIST��Practical Issues of a BIST implementationPractical Issues of a BIST implementation

��Quality of test stimuli Quality of test stimuli

��Wide operation rangeWide operation range

��BIST itself need to be evaluatedBIST itself need to be evaluated��An operational amplifier with tunable performance An operational amplifier with tunable performance

was fabricated and served as a DUTwas fabricated and served as a DUT��Implemented BIST could be evaluated over its Implemented BIST could be evaluated over its

performance variation rangeperformance variation range

��BIST results can be compared with BIST results can be compared with ��Simulation resultsSimulation results

��Measurement results from test equipmentMeasurement results from test equipment

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Basic Structure of OpBasic Structure of Op--AmpAmp

��Input differential pair: Input differential pair: M1 and M2��Second Stage CommonSecond Stage Common--Emitter Amplifier: Emitter Amplifier: M5M5��Output Stage: Output Stage: M6 and Q1M6 and Q1��Compensation Capacitor: Compensation Capacitor: CC

Frequency Response Frequency Response TunabilityTunability��The GBWThe GBW11 of the opof the op--amp is bias dependent amp is bias dependent

��The first two stages (The first two stages (M1, M2 and M5M1, M2 and M5))

17

, 81 2

2D Mm m

T

Ig gGB

C C V C≈ = =

ET

E B

RGB

R Rω≈

+��The output stage (The output stage (M6 and Q1M6 and Q1))

��The bandwidth could be The bandwidth could be tuned with its bias tuned with its bias currentcurrent

10 100 1k 10k 100k 1M 10M 100M-10

0

10

20

30

40

50

60

70

80

90

Frequency (Hz)

Gai

n (d

B)

b3b

2b

1b

0=1000

b3b

2b

1b

0=0100

b3b

2b

1b

0=0010

b3b

2b

1b

0=0001

1.1. GBW: unitGBW: unit--gain bandwidthgain bandwidth

Simulated Frequency Response Tunability

Linearity Linearity TunabilityTunability��The linearity of the opThe linearity of the op--amp is bias dependentamp is bias dependent

��The IM3The IM311 product of an BJTproduct of an BJT22 differential pair isdifferential pair is

�� It works for CMOS differential pair as wellIt works for CMOS differential pair as well

��The linearity could be tuned with bias currentThe linearity could be tuned with bias current

18

3

3 QIM I−

∝

1.1. IM3: 3IM3: 3rdrd--order interorder inter--modulation productmodulation product2.2. BJT: bipolarBJT: bipolar--junction transistorjunction transistor

(a) Current switch b3b2b1b0=1000. (b) Current switch b3b2b1b0=0100. (c) Current switch b3b2b1b0=0010.

90 92 94 96 98 100 102 104 106 108-140

-120

-100

-80

-60

-40

-20

-0

Frequency (kHz)

Pow

er (

dBm

)

90 92 94 96 98 100 102 104 106 108-140

-120

-100

-80

-60

-40

-20

-0

Frequency (kHz)

Pow

er (

dBm

)

90 92 94 96 98 100 102 104 106 108-140

-120

-100

-80

-60

-40

-20

-0

Frequency (kHz)

Pow

er (

dBm

)

Simulated Linearity Tunability

Noise Figure (NF) Noise Figure (NF) TunabilityTunability

19

( ) ( )1 2 31 1 2

1 11 1F F F F

G G G= + − + −

��The NF of the opThe NF of the op--amp is determined by early stageamp is determined by early stage��The noise figure of a cascaded systemThe noise figure of a cascaded system

��Resistor at the inputs could be used to tune noise figureResistor at the inputs could be used to tune noise figure

�� as thermal noise source as thermal noise source 4nV kTRB=

Simulated NF Tunability

Extra Block for Extra Block for TunabilityTunability

20

( )3 2 1 08 4 2ref BIASI b b b b I= + + +

�� Programmable current Programmable current source for the opsource for the op--ampamp�� Controlled by current Controlled by current

switchswitch

�� Programmable resistor bank Programmable resistor bank for the opfor the op--ampamp�� Controlled by resistor switchControlled by resistor switch

31 2 40

1 2 3 4

0

,

0,

RR R Rb

b b b bR

b

= 0

= =1

Overall Design of DUTOverall Design of DUT

21

�� A builtA built--in shift register to accept in shift register to accept command word from outsidecommand word from outside�� To control the To control the tunabilitytunability of the DUTof the DUT

�� To decrease the number of required pins To decrease the number of required pins effectivelyeffectively

�� Three pins of CLK, EN and DINThree pins of CLK, EN and DIN

�� DUT was fabricated with 0.5um DUT was fabricated with 0.5um BICOMS technology and occupied an BICOMS technology and occupied an area of area of 1.6×1.2-mm2

Die PhotoLayout Diagram

Implemented BIST circuitry

PC Interface

DUT

DACDAC Buffer

ADC Buffer

FPGA

ADC

FPGADAC

ADCAnalogMUX

PC Interface

BIST Implementation v1 BIST Implementation v2

�� Two implementations with same architectureTwo implementations with same architecture

��different resolution and speeddifferent resolution and speed

DDSDDS--generated Test Tonesgenerated Test Tones

23

Tone from DDS-based TPG (fs=12.5MHz, Word Length = 8bit)

Tone from Agilent 33250A waveform generator

1010 log ( )actual displayeddBcSNFR SNFR RBWHz = − �� Actual signalActual signal--toto--noise floor rationoise floor ratio

�� Noise Floor of DDSNoise Floor of DDS--generated Tones is mainly contributed by the generated Tones is mainly contributed by the quantization noise from finite word lengthquantization noise from finite word length�� Calculated SNR from measured SNFR over [0, fs/2] is around 32dBCalculated SNR from measured SNFR over [0, fs/2] is around 32dB

�� Simulated SNR in time domain is 36.2dBSimulated SNR in time domain is 36.2dB

SNFRdisplayed=90dBc/Hz

SNFRactual=110dBc/Hz

SNFRdisplayed=80dBc/Hz

SNFRactual=100dBc/Hz

ORA with Finite ResolutionORA with Finite Resolution

24

Spectral analysis done by ideal ORA Spectral analysis done by ORA with finite resolution

SNFRactual=89dBc/HzSNFRactual=101dBc/Hz

�� ORA with finite resolution also introduces calculation noiseORA with finite resolution also introduces calculation noise

��Simulation result shows around 12dB degradation.Simulation result shows around 12dB degradation.

Dynamic Range of BIST Dynamic Range of BIST CirctuitryCirctuitry

25

Spectral analysis done by actual BIST circtuitry

SNFRactual=60dBc/Hz

�� The actual measurement done by BIST is around 60dBc/HzThe actual measurement done by BIST is around 60dBc/Hz�� Mainly limited by switching noise from the digital circuitryMainly limited by switching noise from the digital circuitry

Frequency Response MeasurementFrequency Response Measurement

26

1k 10k 100k 1M 10M-5

0

5

10

15

20

25

Frequency (Hz)

Mag

nitu

de R

espo

nse

(dB

)

Simulation Results with Spectre Simulator

Measured Results with External Equipment

Measured Results with BIST circuitry

1k 10k 100k 1M 10M0

50

100

150

200

Frequency (Hz)

Pha

se R

espo

nse

(deg

ree)

Simulation Results with Spectre Simulator

Measured Results with External Equipment

Measured Results with BIST circuitry

1k 10k 100k 1M 10M-5

0

5

10

15

20

25

Frequency (Hz)

Mag

nitu

de R

espo

nse

(dB

)

Simulation Results with Spectre SimulatorMeasured Results with External Equipment

Measured Results with BIST circuitry

1k 10k 100k 1M 10M-50

0

50

100

150

200

Frequency (Hz)

Pha

se R

espo

nse

(deg

ree)

Simulation Results with Spectre Simulator

Measured Results with External EquipmentMeasured Results with BIST circuitry

(a) Current switch b3b2b1b0=0100. (b) Current switch b3b2b1b0=0010.

�� BIST results match the other resultsBIST results match the other results�� Magnitude Response matches the manually measurementMagnitude Response matches the manually measurement

�� FFT function provided by the oscilloscope (fairly accurate)FFT function provided by the oscilloscope (fairly accurate)

�� Phase Response matches the simulation resultsPhase Response matches the simulation results�� Time lag read from the oscilloscope (very rough estimation)Time lag read from the oscilloscope (very rough estimation)

Linearity MeasurementLinearity Measurement

27

-38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -411

12

13

14

15

16

17

18

19

20

21

Input Power (dBm)

Gai

n (d

B)

Measured Results with External Equipment

Simulation Results with Spectre Simulator

-38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -411

12

13

14

15

16

17

18

19

20

21

Input Power (dBm)

Gai

n (d

B)

Measured Results with External Equipment

Simulation Results with Spectre Simulator

(a) Current switch b3b2b1b0=1000. (b) Current switch b3b2b1b0=0100.

�� P1dBP1dB11 is measured for linearity performance is measured for linearity performance �� Easier to measure with test equipments Easier to measure with test equipments

�� Measurement results with external equipment match simulated resuMeasurement results with external equipment match simulated resultslts�� Maximum difference of 1dB for 4 configurationsMaximum difference of 1dB for 4 configurations

�� BIST results donBIST results don’’t matcht match�� A design mistake of output buffer (without enough current drivabA design mistake of output buffer (without enough current drivability)ility)

�� Limited voltage swing also limits the effective dynamic range ofLimited voltage swing also limits the effective dynamic range of the BIST the BIST circuitrycircuitry

1.1. P1dB: 1dB compression pointP1dB: 1dB compression point

TYPE# OF

SLICES# OF BLOCK

RAM# OF 18××××18

MULTTRANSFORM FREQUENCY

Pipelined 1769 4 12 195 kHzBurst I/O 1411 7 9 92 kHz

Minimum Resources 1365 0 3 37 kHz

28

FPGA ATTRIBUTE

USED BY BIST

TOTAL IN FPGA

% USAGE

# of slices 371 768 48%# of flip-flops 263 1,536 17%

# of 4-input LUTs 656 1,536 42%Maximum BIST Clock Frequency = 48.5 MHz

Resource Usage of Proposed BISTResource Usage of Proposed BIST

Resource used by proposed BIST

Resource used by FFT processor

�� Comparison between the Comparison between the proposed BIST and an FFT proposed BIST and an FFT processor processor �� Five times more slice number Five times more slice number

�� Block ram and 18x18 multiplier Block ram and 18x18 multiplier as a plusas a plus

�� Proposed BIST circuitry is much simpler and cheaper, and can Proposed BIST circuitry is much simpler and cheaper, and can

also achieve more flexibility than FFTalso achieve more flexibility than FFT--based approachbased approach�� Able to tune the step size, frequency range easilyAble to tune the step size, frequency range easily

29

Summary and ConclusionsSummary and Conclusions��The proposed BIST circuitry is able to perform a The proposed BIST circuitry is able to perform a

suite of analog functional testssuite of analog functional tests��Accurate frequency response measurementAccurate frequency response measurement��Linearity and noise measurement is somewhat Linearity and noise measurement is somewhat

constrained by the effective dynamic range of the constrained by the effective dynamic range of the proposed BIST systemproposed BIST system

��The proposed BIST circuitry is efficient in terms of The proposed BIST circuitry is efficient in terms of area, power consumption, and costarea, power consumption, and cost

��Future workFuture work��It is hard to apply the current architecture to RF system It is hard to apply the current architecture to RF system

directly due to various practical issuesdirectly due to various practical issues��GoalsGoals

��Simple analog modulesSimple analog modules��Work in RFIC environmentWork in RFIC environment

30

Publication ListPublication List[1][1]JieJie Qin, Charles Stroud, Foster Dai, Qin, Charles Stroud, Foster Dai, ““Phase Delay in MACPhase Delay in MAC--

based Analog Functional Testing in Mixedbased Analog Functional Testing in Mixed--Signal SystemsSignal Systems””, , Proc. IEEE North Atlantic Test Workshop, Proc. IEEE North Atlantic Test Workshop, 20062006

[2][2]JieJie Qin, Charles Stroud, Foster Dai, Qin, Charles Stroud, Foster Dai, ““Phase Delay Phase Delay Measurement and Calibration in BuiltMeasurement and Calibration in Built--In Analog Functional In Analog Functional TestingTesting””, , Proc. IEEE Southeastern Proc. IEEE Southeastern SympSymp. on System . on System TheoryTheory, 2007, 2007

[3][3]JieJie Qin, Charles Stroud, Foster Dai, Qin, Charles Stroud, Foster Dai, ““Noise Figure Noise Figure Measurement Using MixedMeasurement Using Mixed--Signal BISTSignal BIST””, , Proc. IEEE Proc. IEEE International International SympSymp. on Circuits and Systems, . on Circuits and Systems, 20072007

[4][4]JieJie Qin, Charles Stroud, Foster Dai, Qin, Charles Stroud, Foster Dai, ““FPGAFPGA--Based Analog Based Analog Functional Measurements for Adaptive Control in MixedFunctional Measurements for Adaptive Control in Mixed--Signal SystemsSignal Systems””, , IEEE Trans. on Industrial Electronics, IEEE Trans. on Industrial Electronics, Vol. 54, No. 4, 2007Vol. 54, No. 4, 2007

[5][5]JieJie Qin, Charles Stroud, Foster Dai, Qin, Charles Stroud, Foster Dai, ““Test and Verification Test and Verification of Mixedof Mixed--Signal BIST ApproachesSignal BIST Approaches””, , Submitted to Submitted to International Test Conference, International Test Conference, 20082008