Outline
description
Transcript of Outline
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Outline MOSFET Basics
– Ideal MOSFET physics– Main parameters : threshold, leakage and speed– What MOSFET for what application ?– Scaling theory and good design rules of CMOS Devices
The Real World– Threshold voltage control limitations– Gate oxide leakage and capacitance scaling
Technological Solution ?– Gate alternative : High-K and Metal Gate– Channel engineering : Strained-Si– Alternative devices and substrates– Basic logic functions
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MOSFET Basics
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Making a Switch with Metal, Oxide and Silicon
Energy Barrier
xCarrier reservoir
SourceDrain
E
Energy Barrier
xCarrier reservoir
SourceDrain
MetalOxideSi (p)n+ n+
0
Vg
= S D
C
Silicon channelNiSiNiSi
Source Drain
Gate
Silicon channelNiSiNiSi
Source Drain
Gate
Vd
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What is an ideal MOS Transistor ?
VS=0V VD>0V
VG=0V
S D
G+ + + + + +
- - - - - - - VS=0V VD>0V
VG>0V
S D
G
IDSCanal vide : courant nul Canal rempli : courant non nul
A BTMOS bloqué TMOS passant
OFF-STATE ON-STATE
A MOS capacitor is modulating the transport between two carrier reservoir
MOS capacitance : Field Effect MOSFET
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n-type & p-type MOSFETs
nMOSFETElectron conduction
pMOSFETHole conduction
MetalOxide
0
Vg<0
p+ p+Si (n)
Vd<0
MetalOxide
Si (p)n+ n+
0
Vg>0
Vd>0
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Si
MOSFET morphology
STI STI
W
Contact drainContact source
Contact grille
Zone Active de Si
DrainSource
Gate (Poly-Si)
Source Drain
MétalOxydeSemi-conducteur
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Basic Physics of MOSFET
Vgate
Log(Idrain) Ideal switch
Threshold (Vth)
ON state Current
OFF state Current
MOSFET switch
OFF State Current (Thermal)
3 main parameters
1. Threshold Voltage2. Ion (=speed)3. Ioff (=stand-by power)
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MOSFET Physics
L
WS/CWD/C
source drain
grille
canal
BCN
P
d--- -- - N--- -- -
VG=0
VDVS
VB
LTox
« Off State»
N P N+ + + +--- ---
nMOSFET L
WS/CWD/C
source drain
gate
channel
BC
P
NVD
N -- --- - - - -
-- -
VG=VD
VDVS
VB
LTox
N P N--- - - ---+ + + + +
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Threshold Voltage (Vth)
Fox
depFBth C
QVV 2
L
WS/CWD/C
source drain
gate
channel
BC
P
NVD
N -- --- - - - -
-- -
Gate Material
Oxide Thickness
Channel Doping
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On State Current (Ion)
Lgate
Source Drain
Gatet
QI inv
DS
DSDS
thGoxeDS VVVVL
WCµI
2
L
Eµv eL
VE DS
DSeVµLt
2
WLV
VVCWLQQQ DSthGox
Dinv
Sinvinv
22
1
Vg-Vth Vg-Vth-VDS
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Off – State Current (Ioff)
- - -- - -
VD>0
VG1<Vth
- - -- - -
VD>0
VG1<VG2<Vth
Ithermique Idiffusion Ithermique Idiffusion
kTV
qS
VII DSGT
thDS exp110lnexp
SV
II ththoff )log()log(
Modulation of barrier heigth by Capacitive coupling1/S
Vth
Log Idrain
Vgate
+ dec Ioff
S should be as small as possible
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The Static Leakage Componentsi) Gate leakage (oxide thickness dependance)
iii) Junction leakage (doping dependance)
ii) Channel Leakage (Vth and S dependant)
Ioff = IS + IG + IB
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CMOS Scaling
CMOS090
CMOS065CMOS045
CMOS032
CMOS120
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Gordon Moore, a co-founder of Intel said in 1965:“Component count per unit area doubles every two years”
- Last 40 years : technological advances achieved mainly by reducingtransistors size
- However current trend of miniaturization causes undesired effects degrading the electrical parameters and transistor performance
Scaling Theory: Moore’s law
In reality:• µ decreases • Tox levels-off• Off current increases as transistor size is reduced
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Ideal MOSFET Basics summary
Source Drain
Gate Electrode
Source Drain
Gate Electrode
Source Drain
Gate Electrode
Source Drain
Gate Electrode On-State : MOS gate capacitance lowers channel barrier electrons(holes) flow from Source to Drain Ion current Carrier transit time is Cgate*Vgate / Ion the higher Ion the
faster the device
Off-State : MOS gate capacitance potential = 0 electrons(holes) flow from Source to Drain due to Thermionic
current Ioff current Static Power dissipation is Pstat = VDS * Ioff
Threshold Voltage : Determines the gate voltage transition Vth between Off-state and
On-state regimes Vth depends (at the 1st order) on the channel doping and gate
electrode material
Log(IDS)
VGS
Low Vth
High VthLog(IDS)
VGS
Low Vth
High Vth
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Part 2.
The Real World
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Vth Control : Short Channel EffectsZone de charge d’espace
ZCE L
BC
SCE=Short Channel Effect
SCEDIBL
DIBL=Drain Induced Barrier Lowering
VDS
Vth
Log Idrain
Vgate
SCE
Vth1
DIBL
Vth2
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MOSFET Typical Lenghts and Ratios
Lgate,phys
draingate
Tdep
source
Lel
Xj
Tox
; ; 31
el
j3040
1
el
ox
LT
31
el
dep
L
T
L
X 51
dd
th
V
V
jphysgateel XLL 8.0,
SBdB
Sidep V
qNT
2
Good design rules of MOSFET architecture :
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dsel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
2
21
biel
dep
el
ox
el
j
ox
SiV
L
T
L
T
L
XSCE
2
2 1
0.8
0.8
dsatgoxeffdsat V(VLel
WelCI 21 m -Vth)
T. Skotnicki et al. IEEE EDL, March’88 & IEDM’1994
Scaling rules (MASTAR Model)VTH(short Mosfet)=VTH(long)-SCE-DIBL
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Why is it so difficult to get a « Good Scaling » ?
Lgate,phys
draingate
Tdep
source
Lel
Xj
31
el
jLX
31
el
jLX
30401
el
ox
LT
30401
el
ox
LT
31
el
dep
L
T
31
el
dep
L
T
51
dd
th
V
V
51
dd
th
V
V
Oxide Scaling Junction Scaling
Subthreshold controlDoping increase
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Tox/Lel ratio : Gate Oxide Scaling
Lgate,phys
drainPoly-Si
gate
Tdep
source
Lel
Xj
zzzz
Tox
BC
BV
SiliciumSiliciumOxydeOxydePolyPoly--SiliciumSiliciumTox
BC
BV
SiliciumSiliciumOxydeOxydePolyPoly--SiliciumSiliciumTox
BC
BV
SiliciumSiliciumOxydeOxydePolyPoly--SiliciumSilicium
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The Gate-Poly Silicon Depletion
poly
pSipolydep qN
T2
2
22
42
FFBG
ppp VV
kk
ox
pSip C
Nqk
2
Ref.: E. Josse et al., IEDM’99
N+ P+
Tdeppoly = 0.4nm 0.6nm
02468
101214161820
0 10 20 30 40CMOS relevant Tox , A
NMOS ( Npoly =1e20cm-3)
Tp (EOT)@1.8V1.3V1.0V0.7V0.5V0.35V0.25V
EOT
of p
olyd
eple
tion ,
A02468
101214161820
0 10 20 30 40CMOS relevant Tox , A
NMOS ( Npoly =1e20cm-3)
Tp (EOT)@1.8V1.3V1.0V0.7V0.5V0.35V0.25V
Tp (EOT)@1.8V1.3V1.0V0.7V0.5V0.35V0.25V
EOT
of p
olyd
eple
tion ,
A
Vdd scaledwith Tox
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The problem of Gate Leakage
Poly-Si
Si
EfEvEf
Ec
Gate N+SiO2
Substrate Si P
Ec
Ev
Wpd
2A reduction in Tox ~ 1 dec increase in gate leakage
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1.E+03
1.E+05
0 1 2 3Gate bias, V
Gat
e cu
rren
t, A/
cm2
1nm
1.5nm
2nm
.5nm
3nm
3.5nm
SiO2
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1.E+03
1.E+05
0 1 2 3Gate bias, V
Gat
e cu
rren
t, A/
cm2
1nm
1.5nm
2nm
.5nm
3nm
3.5nm
SiO2
2
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Impact of Gate Leakage on Circuits
In Static Mode, two gate leakages: IgOff & IgOn : increase of Ioff
If Tox , Ig , Power
0
10
0
Ioffcanal
Igoff
1
00
0
IgOn
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Vth/Vdd Ratio
51
dd
th
V
V
51
dd
th
V
V If Vdd drops, just decrease the Vth too keep a good Ion. But …
S degrades at smaller L !
VgsVth
Log(IDS )
Ioff
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What Did We Learn ?
Controlling Vth (Ioff)
Increasing Doping
Scaling Jonctions
Scaling Tox
Darkspace
Polydepletion
Junc. Leak.
Rs increase Ion (speed) reduction
Ioff (power) increase
Higher Ioff
Limited Scaling Ion reduction
Gate leakage
Reducing Vdd (power) Ion reduction
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Technological Boosters to recover a Healthy Scaling
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What can we do to retrieve a Healthy Scaling ?
Silicon channelNiSiNiSi
Source Drain
Gate
30401
el
ox
LT
30401
el
ox
LT
Oxide Scaling Junction Scaling
Subthreshold control Vs Overdrive
Doping increase
31
el
dep
L
T
31
el
dep
L
T
Less Gate LekageNo Poly Depletion
DIBL-Free Architecture
Low RSD for lower Xj Better Contact Resistance
Better Ion at the same overdriveBetter Subthreshold Slope
51
dd
th
V
V
51
dd
th
V
V
31
el
jLX
31
el
jLX
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Mobility Enhancement
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Ion Enhancement by materials
DSDS
thGoxeDS VVVVL
WCµI
2
Transistor ArchitectureMaterial Properties
Carrier velocity under electric field E in the linear regime: v = µ E
µEcritical
Efield
Velocity Velocity saturation regime
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Mobility In Silicon
E
carrier, mass m*
Shockwave from lattice vibration, or impurities, or
gate oxide rugosity every t seconds 1. Small m* : ligth
electrons or holes
*2mE
v c
2. High t (less possible collision)
*mqµt
Effective mass of carrierLinked to valence/conduction bands
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Gate Capacitance Scaling : High-K dielectrics
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Figthing against Gate Leakage
EfEvEf
Ec
Gate N+SiO2
Substrate Si P
Ec
Ev
Wpd
Reducing Tunneling…Increasing Tox !But without reduction of Cox !Increasing permitivity
HIGH K materials
ox
oxox T
εC
Leakage issue
Polydepletion issueReplacing Poly-Si by Metal
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5252
Context Down to 90nm gate length, N+ and P+ polysilicon gate was used for CMOS
integration compatible with oxide or oxynitride gate dielectric.
Due to aggressive scaling of the gate dielectric, the gate leakage is becoming unacceptably high (>Ioff), requiring the use of high-k dielectric
Due to the incompatibility of polysilicon gate with high-k dielectric (Fermi pinning, large Vt, mobility degradation) and the need to boost performance (elimination of polydepletion, boron penetration,…), metal gate electrodes will likely be needed
For bulk technology, two metals with WFs close to the bandgap edges are needed (high channel doping required to control SCE).
For FDSOI or double gate devices, WFs within 250meV from midgap are preferred, requiring more complex integration
Two integration approaches are considered: gate first and gate last.
Figthing against Gate Leakage
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5353
High-k dielectric
C. Fenouillet et al IEDM 2007
0,00001
0,0001
0,001
0,01
0,1
1
10
100
17 19 21 23 25 27CET (A)
J g ON (A
/Cm
²)
MG/HfO2
2 Dec
FD SOI nMOS, Vg = 1.1V
2 DecPoly-Si/SiON1 Dec
MG/Hf SiON
MG/SiON
MASTAR Exp data.
High-K At an equivalent CET of SiON dielectric, the gate leakage current is reduced by more than 2 decades
For EOTs below 20Å, gate leakage currentbecomes higher than off-state leakage current.
High-k dielectric
High-k (HfO2, ZrO2, Hf-based or Zr-based,LaO2, Al2O3,… ALCVD or MOCVD deposition
Pre-deposition clean and post depositionanneals affect the quality of high-k
Large Vt: Fermi pinning at the poly-Si/Metal oxide interface but occurs also metal gate electrodes
Compatibility of polysilicon gate with high-k is unlikely !
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5454
High-k Dielectric : Issues Mobility degradation
- Many publications have reported mobility degradation using high-k dielectrics.
- Possible cause is coupling of soft optical phonons in high-k with inversion channel charge carrier
Vt instabilities and reliability and noise issues Large k and large dielectric thickness result in fringing field (FIBL)
and loss of control of the channel by the gate
B. Tavel et al, PhD Thesis 2002
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Gate Capacitance Scaling : Metal Gates
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56
Choosing The « Good Metal »
Mid-gap Gate
Ec
Ev
nMOS Gatepoly-Si N+ Metal Gate « N+like »
1.12 V
pMOS Gatepoly-Si P+
Metal Gate « P+like »
Fox
depFBth C
QVV 2
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5757
The use of metal gate suppress:– the polysilicon depletion : a reduced CET of 3-5Å for performance
improvement– and suppress the boron penetration problem
Two approaches have been proposed: gate first or gate last
– Gate first approach requires to take care of FE contamination tool, metal etching and to the high temperature anneal
– Gate last approach (replacement gate): dummy gate removal and replacement, gate dielectric integrity has to be kept
But for some applications CMOS requires 2 different metal gates in order to separate WFs for NMOS and PMOS devices (Dual metal gate integration)
Metal gate integration
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Why is Metal Workfunction so important ?
Vg
Log Id
Id
Vg
Vth,nVth,p
Ion,nIon,p
VddVdd
Regular Poly-gate n+/p+
Vg
Id
Vg
Vth,nVth,p
Ion,nIon,p
VddVdd
Mid-gap Metal Gate
+0.5V+0.5V
Vg
Log Id
Id
Vg
Vth,nVth,p
Ion,nIon,p
VddVdd
Dual n+/p+ Metal GateLog Id
+25%Polydepreduction
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5959
Why midgap metal gate ? Why high-k ?
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
N+ like gate
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, TBOX= 145 nm, TSi= 8 nm, Tox = 1.9 nm
P+ like gate
pFET Midgap gate
nFET Midgap gate
-0.2
0
0.2
0.4
0.6
0.8
1
1.E+16 1.E+17 1.E+18 1.E+19Channel doping (cm -3)
V th(V
) @ V
d=|0
.1V|
Lg= 200 nm, T = 145 nm, TSi
P+ like gate
Midgap electrode with undoped channel : symmetrical Vth for NMOS and PMOS for high Vth applications
With Band edge gate electrodes (as poly-Si), FDSOI requires very high channel doping > 8e18 at/cm3 for HVT -> Variability degradation
Metal gate interest for FDSOI
![Page 42: Outline](https://reader035.fdocuments.in/reader035/viewer/2022062323/5681636c550346895dd448e6/html5/thumbnails/42.jpg)
60
Device Architecture
![Page 43: Outline](https://reader035.fdocuments.in/reader035/viewer/2022062323/5681636c550346895dd448e6/html5/thumbnails/43.jpg)
61
Bulk PD SOIScalability ? Scalability
as BULKScalability much improved if GP
FD SOIScalability may be better or worse (GP,BOX)
FD SON
GP
Scalability very much improved
DG (Delta, FinFET, SON, Vertical,TriGate, Omega, etc., etc.
el
dep
el
ox
el
j
LT
LT
L
X
EI
2
21
1
el
dep
el
ox
el
j
LT
LT
L
Xx
EI
2
21
1
el
boxsi
el
ox
el
si
LTT
LT
LT
EI
2
21
1
el
boxsi
el
ox
el
si
LTT
LT
LT
EI
2
21
1
el
si
el
ox
el
si
LT
LT
LT
EI
2/
4/1
5.0
2
2
Xj Tdep
dsd VEIDEISCE ox
si
ox
si 0.8IBL 64.0
REF.:T. Skotnicki, invited paper
ESSDERC 2000, pp. 19-33, edit. Frontier Group
Device Architecture