OSK Week 1 -...

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IntroductionIntroduction

Computer System Organization

Tb. Maulana Kusuma Week 1 | Session 1

Sarjana Magister Program

Languages, Levels, Virtual Machines

A multilevel machine

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Contemporary Multilevel Machines

A six-level computer. The support method for each level is indicated below it .

Evolution of Multilevel Machines

• Invention of microprogramming• Invention of operating system• Migration of functionality to microcode• Elimination of microprogramming

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Operating System Tasks

A sample job for the FMS operating system

Milestones in Computer Architecture (1)

Some milestones in the development of the modern digital computer.

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Milestones in Computer Architecture (2)

Some milestones in the development of the modern digital computer.

Computer Generations• Zeroth Generation

Mechanical Computers (1642 – 1945)

• First GenerationVacuum Tubes (1945 – 1955)

• Second GenerationTransistors (1955 – 1965)

• Third GenerationIntegrated Circuits (1965 – 1980)

• Fourth GenerationVery Large Scale Integration (1980 – ?)

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Von Neumann Machine

The original Von Neumann machine.

PDP-8 Innovation – Single Bus

The PDP-8 omnibus

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IBM 360

The initial offering of the IBM product line.

Technological and Economic Forces

Moore’s law predicts a 60-percent annual increase in thenumber of transistors that can be put on a chip. The data points given in this figure are memory sizes, in bits.

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The Computer Spectrum

The current spectrum of computers available. The prices should be taken with a grain (or better yet, a metric ton) of salt.

Personal Computer

A printed circuit board is at the heart of every personal computer. This figure is a photograph of the Intel D875PBZ board. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission.

1. Pentium 4 socket2. 875P Support chip3. Memory sockets4. AGP connector5. Disk interface6. Gigabit Ethernet7. Five PCI slots8. USB 2.0 ports9. Cooling technology10. BIOS

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Example Computer Families

• Pentium 4 by Intel• UltraSPARC III by Sun Microsystems• The 8051 chip by Intel, used for embedded systems

Intel Computer Family (1)

The Intel CPU family. Clock speeds are measured in MHz (megahertz) where 1 MHZ is 1 million cycles/sec.

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The Pentium 4 chip. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission.


Moore’s law for (Intel) CPU chips.

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MCS-51 Family

Members of the MCS-51 family.

Metric Units

The principal metric prefixes.

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Architecture & Organization 1

Architecture is those attributes visible to the programmer

Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques.e.g. Is there a multiply instruction?

Organization is how features are implementedControl signals, interfaces, memory technology.e.g. Is there a hardware multiply unit or is it done by repeated addition?

Architecture & Organization 2

All Intel x86 family share the same basic architectureThe IBM System/370 family share the same basic architecture

This gives code compatibilityAt least backwards

Organization differs between different versions

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Structure & Function

Structure is the way in which components relate to each otherFunction is the operation of individual components as part of the structure

Function

All computer functions are:Data processingData storageData movementControl

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Functional view

Functional view of a computer

DataMovementApparatus

ControlMechanism

DataStorageFacility

DataProcessingFacility

Operations (1)

Data movemente.g. keyboard to screen


ControlMechanism

DataStorageFacility


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Operations (2)

Storage e.g. Internet download to disk


ControlMechanism

DataStorageFacility


Operation (3)

Processing from/to storage e.g. updating document


ControlMechanism

DataStorageFacility


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Operation (4)

Processing from storage to I/Oe.g. printing a document


ControlMechanism

DataStorageFacility


Structure - Top Level

Computer

Main Memory

InputOutput

SystemsInterconnection

Peripherals

Communicationlines

CentralProcessing Unit

Computer

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Structure - The CPU

Computer Arithmeticand Logic Unit

ControlUnit

Internal CPUInterconnection

Registers

CPU

I/O

Memory

SystemBus

CPU

Structure - The Control Unit

CPU

ControlMemory

Control Unit Registers and Decoders

SequencingLogin

ControlUnit

ALU

Registers

InternalBus

Control Unit

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Computer System Organization

Tb. Maulana Kusuma Week 1 | Session 2

Sarjana Magister Program

Computer Systems OrganizationComputer Systems Organization

Central Processing Unit

The organization of a simple computer with one CPU and two I/O devices

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CPU Organization

The data path of a typical Von Neumann machine.

Instruction Execution Steps

1. Fetch next instruction from memory into instruction register

2. Change program counter to point to next instruction3. Determine type of instruction just fetched4. If instructions uses word in memory, determine where

Fetch word, if needed, into CPU register5. Execute the instruction6. Go to step 1 to begin executing following instruction

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Interpreter (1)

An interpreter for a simple computer (written in Java).

. . .

Interpreter (2)

An interpreter for a simple computer (written in Java).

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CPU components

Memory Address Register: holds main memory addresses when fetching instructions or data

CPU components

Memory Data Register(Memory Buffer Register, MBR): stores instruction and data just fetched and data to be written to

the main memory

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CPU components

Instruction Register:contains the instruction currently

being executed

CPU components

Control Unit: generates control signals that cause the execution of an instruction or the fetch of

another instruction

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CPU components

Arithmetic-Logic Unit:where calculations and

manipulations take place

CPU components

General Purpose Registers:special memory cells for

temporary storage of data

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CPU components

Program Counter: contains the address of the next instruction to

be executed

CPU components

Processor Status Register (Processor Status Word, PSW): contains information about the

state of the CPU

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CPU components

Fetch-Execute Cycle

• Defines how instructions are retrieved and executed inside the computer

• Sometimes called the Instruction Cycle or Automatic Sequence Control

• Fetch the instruction from memory to IR• Increment the PC • Execute the instruction in IR• Repeat steps 1 to 3 until termination

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Fetch-Execute Cycle

CPU

001101PC

001100

001101

001110

001111

010000

111100…

100001…

001010…

000101…

111100…

Fetch next instruction from memory to IR

1Increment the PC

IR

Execute the instruction…

100001…

Memory

dataaddress

Fetch-Execute Cycle: Fetching

• Fetch Stage:

– Copy contents of PC into MAR

– Increment PC (point to the next instruction)

– Copy an instruction from MDR into IR

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Fetch-Execute Cycle: Executing

• Execute Stage:

– Decode the instruction from IR

– Run the instruction in IR (may require getting data from the main memory)

– Unless the current instruction is HALT (stop), repeat the cycle

Illustration

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Design Principles for Modern Computers

• All instructions directly executed by hardware• Maximize rate at which instructions are issued• Instructions should be easy to decode• Only loads, stores should reference memory• Provide plenty of registers

Instruction-Level Parallelism

a) A five-stage pipelineb) The state of each stage as a function of time. Nine clock

cycles are illustrated

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Superscalar Architectures (1)

Dual five-stage pipelines with a common instruction fetch unit.

Superscalar Architectures (2)

A superscalar processor with five functional units.

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Processor-Level Parallelism (1)

An array of processor of the ILLIAC IV type.

Processor-Level Parallelism (2)

a) A single-bus multiprocessor.b) A multicomputer with local memories.

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Primary MemoryMemory Addresses (1)

Three ways of organizing a 96-bit memory.

Primary MemoryMemory Addresses (2)

Number of bits per cell for some historically interesting commercial computers

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Byte Ordering (1)

(a) Big endian memory (b) Little endian memory

Byte Ordering (2)

(a) A personal record for a big endian machine. (b) The same record for a little endian machine.(c) The result of transferring from big endian to little endian.(d) The result of byte-swapping (c).

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Error Correcting Codes (1)

Number of check bits for a code that can correct a single error


(a) Encoding of 1100(b) Even parity added(c) Error in AC

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Construction of the Hamming code for the memory word 11110000010101110 by adding 5 check bits to the 16 data

bits.

Cache Memory

The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located.

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Memory Packaging and Types

A single inline memory module (SIMM) holding 256 MB. Two of the chips control the SIMM.

Memory Hierarchies

A five-level memory hierarchy.

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Magnetic Disks (1)

A portion of a disk track. Two sectors are illustrated.

Magnetic Disks (2)

A disk with four platters.

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Magnetic Disks (3)

A disk with five zones. Each zone has many tracks.

SCSI Disks

Some of the possible SCSI parameters.

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RAID (1) Redundant Array of Inexpensive Disks

RAID levels 0 through 2. Backup and parity disks are shown shaded.

RAID (1) Redundant Array of Inexpensive Disks

RAID levels 3 through 5. Backup and parity disks are shown shaded.

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CD-ROMs (1)

Recording structure of a Compact Disk or CD-ROM.

CD-ROMs (2)

Logical data layout on a CD-ROM.

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CD-Recordables

Cross section of a CD-R disk and laser (not to scale). A CD-ROM has a similar structure, except without the dye layer and with apitted aluminum layer instead of a reflective layer.

DVD

A double-sided, dual layer DVD disk.

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Input/OutputBuses (1)

Physical structure of a personal computer.


Logical structure of a simple personal computer.

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A typical modern PC with a PCI bus and an ISA bus.

CRT Monitors

(a) Cross section of a CRT(b) CRT scanning pattern

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Flat Panel Displays

(a) The construction of an LCD screen.(b) The grooves on the rear and front plates are perpendicular

to one another.

Mice

A mouse being used to point to menu items.

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Printers (1)

(a) The letter “A” on a 5 x 7 matrix. (b) The letter “A” printed with 24 overlapping needles.

Printers (2)

Operation of a laser printer.

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Printers (3)

Halftone dots for various gray scale ranges. (a) 0 – 6. (b) 14 – 20. (c) 28 – 34.

(d) 56 – 62. (e) 105 – 111. (f) 161 – 167.

Telecommunications

a) Transmission of the binary number 01001010000100 over a b) telephone line bit by bit. (a) Two-level signal. (b) Amplitude c) modulation. (c) Frequency modulation. (d) Phase modulation.

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Digital Subscriber Lines (1)

Operation of ADSL.

Digital Subscriber Lines (2)

A typical ADSL equipment configuration.

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Internet over Cable (1)

Frequency allocation in a typical cable TV system used for Internet access

Internet over Cable (2)

Typical details of the upstream and downstream channels in NorthAmerica. QAM-64 (Quadrature Amplitude Modulation) allows

6 bits/Hz but only works at high frequencies. QPSK (Quadrature Phase Shift Keying) works at low frequencies

but allows only 2 bits/Hz.

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Digital Cameras

A digital camera.

ASCII Character Codes (1)

The ASCII Character set: characters 0 – 31.

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ASCII Character Codes (2)

The ASCII Character set: characters 32 – 127.

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