osaki2012.pdf

1776 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012

A Low-Power Level Shifter With Logic ErrorCorrection for Extremely Low-Voltage Digital

CMOS LSIsYuji Osaki, Student Member, IEEE, Tetsuya Hirose, Member, IEEE, Nobutaka Kuroki, and

Masahiro Numa, Member, IEEE

Abstract—This paper presents a level shifter circuit capable ofhandling extremely low-voltage inputs. The circuit has a distinc-tive current generation scheme using a logic error correction cir-cuit that works by detecting the input and output logic levels. Theproposed level shifter circuit can convert low-voltage digital inputsignals into high-voltage digital output signals. The circuit achieveslow-power operation because it dissipates operating current onlywhen the input signal changes. Measurement results demonstratedthat the circuit can convert a 0.23-V input signal into a 3-V outputsignal. The power dissipation was 58 nW for a 0.4-V 10-kHz inputpulse.

Index Terms—Level converter, level shifter, low power, lowvoltage, subthreshold.

I. INTRODUCTION

T HE most effective and direct way to reduce powerdissipation in digital LSIs is to reduce their supply

voltage because of their quadratic dependence of the powerdissipation on the supply voltage. Several low-power designtechniques have been investigated. Subthreshold LSIs—LSIswhose supply voltage is lower than the threshold voltageof a MOSFET—have attracted much attention for use inpower-aware LSI applications such as wireless sensor net-works, implantable bio-medical systems, and environmentalmonitoring devices [1]–[4]. However, there are a number ofdesign challenges, and several studies have been carried out.Among them, one of big issues is in a level shifter (LS) circuitdesign [5]. In this paper, we describe and demonstrate an LScircuit suitable for extremely low-voltage digital LSIs [6], [7].In low-voltage LSI systems, subthreshold digital LSIs will

be implemented with conventional circuits that operate at highsupply voltage. Therefore, an LS circuit is required to enablecorrect communication with other circuits. Moreover, it is alsorequired when LSI designers must test the functionality of the

Manuscript received November 15, 2011; revised January 31, 2012; acceptedFebruary 19, 2012. Date of publication May 11, 2012; date of current versionJune 21, 2012. This paper was approved by Guest Editor Atila Alvandpour. Thiswork was supported in part by the VLSI Design and Education Center (VDEC),The University of Tokyo with the collaboration with Cadence Design Systems,Inc. and Mentor Graphics, Inc., STARC, KAKENHI (21680004), and the NewEnergy and Industrial Technology Development Organization (NEDO).The authors are with the Department of Electrical and Electronic En-

gineering, Kobe University, Nada, Kobe 657-8501, Japan (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2012.2191320

low-voltage subthreshold digital circuits. However, communi-cation and function tests are difficult when conventional LS cir-cuits are used because the supply voltage of the subthresholddigital circuits is below 0.5 V and that of the peripheral cir-cuits is still high (e.g., the supply voltage of input/output (I/O)peripheral circuits is 3.3 V). This is because the drive current ofthe low-voltage circuit significantly lowers as the supply voltagereduces and conventional LS circuits cannot pull down voltages.To mitigate this problem, several level shifters and remedieshave been investigated [4], [8]–[13]. One approach has been toincrease the drive current of the level shifter by enlarging thetransistor channel width. Another is to use a multi-stage levelshifters [4] or inverters with multiple supply voltages. However,these circuits still depend on the supply voltage difference, thecircuit configuration is complex, and it requires multiple refer-ence voltages. The problem discussed above is thus basicallyunresolved.To solve this problem, we present an LS circuit with a logic

error correction circuit (LECC) capable of handling extremelylow-voltage inputs [6], [7]. The proposed LS circuit can con-vert extremely low-voltage signals into high-voltage signals.The circuit is based on a conventional two-stage comparator cir-cuit and has a distinctive feature in a current generation circuitwith an LECC [7].This paper is organized as follows. Section II briefly describes

the problem with a conventional LS circuit and presents the op-eration principle of our proposed circuit. Section III shows thesimulation results, Section IV shows the experimental resultswith a fabricated proof-of-concept chip, and Section V con-cludes the paper.

II. LEVEL SHIFTER CIRCUIT

A. Conventional

Fig. 1 shows the schematic of a conventional LS circuit. Thecircuit consists of cross-coupled pMOSFETs (MP1 and MP2)and two nMOSFETs (MN1 andMN2) driven by complementaryinput signals IN and INB. The circuit has critical problemswhenthe voltage difference between low supply voltage andhigh supply voltage becomes large.When the voltages of IN and INB are Low and High, MN1

and MN2 are Off and On, respectively. MN2 then pulls downnode OUT, causing MP1 to turn On. Because node OUTB thenincreases to , MP2 turns off, and OUT drops to the GNDlevel. Note that the voltage of OUT is determined by the drive

0018-9200/$31.00 © 2012 IEEE

OSAKI et al.: A LOW-POWER LEVEL SHIFTER WITH LOGIC ERROR CORRECTION FOR EXTREMELY LOW-VOLTAGE DIGITAL CMOS LSIs 1777

Fig. 1. Schematic of conventional LS circuit.

Fig. 2. Architecture of proposed LS circuit.

currents of pull-up transistor MP2 and pull-down transistorMN2. Therefore, if the drive current of MP2 is larger thanthat of MN2, OUT cannot be discharged. Moreover, when weconsider the case of extremely low-voltage subthreshold digitalLSIs, because the on-current of MN2 becomes quite low, thedrive currents of the nMOSFETs are significantly smaller thanthose of the pMOSFETs, which operate in the strong inversionregion. Thus, OUT cannot be discharged. As a result, a con-ventional LS circuit cannot correctly operate in this situation.

B. Proposed

The architecture of the proposed LS circuit is shown in Fig. 2.It consists of a level conversion circuit and a logic error correc-tion circuit (LECC). The complementary input signals (IN andINB) and the output signal (OUT) are applied to the LECC. TheLECC supplies the operating current for the level conversioncircuit only when the LECC detects a logic error. Fig. 3 showsthe complete schematic of the LS circuit. The operation princi-ples of the circuits are described in the following sections.1) Level Conversion Circuit: The level conversion circuit,

which is shown on the right in Fig. 3, is based on a conven-tional two-stage comparator circuit. The comparator generatesoutput voltage signal, OUT, according to the difference in thevoltage of IN and INB. Note that the voltage of OUT is de-termined by the drive currents of pull-up transistor MP6 andpull-down transistor MN8, and that the currents flowing in MP6and MN8 depend on current flowing through MP2. Therefore,because both drive currents are determined by the same current,the circuit is free from the limitations discussed in the conven-tional ones.In the conventional comparator design, a current reference

circuit needs to operate steadily. However, because the currentreference circuit dissipates static current and increases powerdissipation, it cannot be used in our design. Therefore, we de-veloped a logic error correction circuit (LECC) in which thecurrent flowing in the circuit is generated only when the inputsignals change.2) Logic Error Correction Circuit (LECC): The LECC,

which is shown on the left in Fig. 3, consists of two circuitblocks: 1) a low logic error correction circuit (LLECC) and 2) ahigh logic error correction circuit (HLECC). They are driven

by IN, INB, and OUT. The LECC generates an operatingcurrent such that IN and OUT correspond to each other. Whenthe output logic level of the LS circuit corresponds to the inputlogic level, the LECC does not supply current . When theydo not correspond, the LECC detects the logic error, and theLLECC or HLECC supplies an operating current. In otherwords, because the LECC supplies an operating current onlywhen the input and output logic levels do not correspond toeach other, the power dissipation of the circuit is minimized.The correction circuit operations are described below.— LLECC: The low logic error correction circuit, LLECC,consists of two nMOSFETs (MN1 and MN2) connectedin series. The LLECC operates only when OUT does notcorrespond to the “Low” logic of IN. Fig. 4(a) depicts thewaveforms of IN, INB, and OUT. When IN changes fromHigh to Low, or when INB changes from Low to High,there is a period during which OUT does not correspondto IN. During this period, the LLECC generates fall-tran-sition current until OUT corresponds to the Low logicof IN.When the logic levels of IN and OUT are Low, the LLECCdoes not supply any current for the level conversion circuitbecause MN2 is off due to the Low logic level of OUT.However, when the logic levels of IN and OUT do notcorrespond (i.e., IN, INB, and OUT are Low, High, andHigh, respectively), flows because the voltages of bothINB and OUT are High; pulls OUT down to GND sothat the input and output logic levels correspond.

— HLECC: The high logic error correction circuit, HLECC,consists of three nMOSFETs (MN3, MN4 and MN5) anda pMOSFET (MP1). In contrast to the LLECC, the cir-cuit operates only when OUT does not correspond to the“High” logic of IN. Fig. 4(b) depicts the waveforms of INand OUT. When IN changes from Low to High, there isa period during which OUT does not correspond to IN.During this period, the HLECC generates rise-transitioncurrent until OUT corresponds to the High logic of IN.When the logic levels of IN and OUT are High, theHLECC does not supply any current because the outputvoltage of the first stage in the HLECC is Low. However,when the logic levels of IN and OUT do not correspond(i.e., IN, INB, and OUT are High, Low, and Low, re-spectively), the HLECC generates current , and theLS circuit operates so that the input and output logiclevels correspond. When IN and OUT are High and Low,the output voltage of the first stage is High because theoverdrive voltage of the MP1 is larger than that of MN3.This enables MN4 and MN5 to supply current to thelevel conversion circuit, and pulls OUT up to .

From the discussion above, current for the level conversioncircuit is expressed as

(1)

Because and are not generated and the LECC doesnot supply current when the input and output logic levelscorrespond, the power dissipation of the circuit is minimized.The amount of and generated depends on lower supplyvoltage of .


Fig. 3. Schematic of proposed LS circuit.

Fig. 4. Waveforms (a) when fall-transition current for LS is generated and(b) when rise-transition current for LS is generated.

TABLE ITRANSISTOR SIZES OF OUR CIRCUIT

When IN and OUT correspond, the LECC does not supplyany current to the level conversion circuit. However, in fact,leakage current flows in the circuit. Therefore, because thevoltage gain in the level conversion circuit is sufficient to keepthe output node, OUT is kept at a voltage, i.e. or GND.If some unexpected noise ever changes the OUT, the LECCdetects logic errors and supplies the operating current until INand OUT once again correspond. On the other hand, if the noisechanges the input logic levels of IN and INB, the LS circuitcannot operate properly due to the disrupted logic inputs. Thismeans that the noise immunity of the proposed LS circuit islimited by that of low-voltage digital circuit. In other words,the noise margin of the proposed LS circuit is determined bythat of the low-voltage digital circuits themselves.

III. SIMULATION RESULTS

The performance of the proposed LS circuit was evaluatedusing SPICE with a set of 0.35- m parameters. was setto 3 V.We used an inverter as a load circuit of the LS circuit andcalculated power dissipations including a charge and dischargecurrent for the load. Table I shows the transistor sizes of theproposed LS circuit.

Fig. 5. Simulated waveforms of proposed LS circuit. Frequency of input signalwas set to 1 kHz: (a) input signal and output signal; (b)–(d) currents flowing ineach circuit in Fig. 3.

A. Waveforms

Fig. 5 shows the simulated waveforms. The amplitude andfrequency of the input signal were set to 0.4 V and 1 kHz,respectively. As shown in Fig. 5(a), the 0.4-V input signal wasconverted into a 3-V output signal. Fig. 5(b)–(d) shows the cur-rent flowing in each logic error correction circuit in Fig. 3.When the input signal of IN changed to High level of ,

there was a period when the logic level of OUT did not cor-respond to that of IN, as shown in Fig. 5(a). The HLECC de-tected this and generated current , as shown in Fig. 5(b). Thiscurrent was supplied to the level conversion circuit, which con-verted the 0.4-V input signal into a 3-V output signal. Duringthis period, the LLECC did not generate current , as shownin Fig. 5(c). On the other hand, when the input signal of INchanged to Low level of GND, the LLECC generated current


Fig. 6. Simulated (a) delays and (b) power dissipations of LS circuits as a function of at V. Simulated (c) delays and (d) power dissipations ofLS circuits as a function of at V.

while the HLECC did not generate current . This currentwas supplied to the level conversion circuit, which convertedthe 0.4-V input signal into a 3-V output signal. As shown inFig. 5(b) and (c), the currents of and were generated al-ternately in accordance with the logic transition of IN. Fig. 5(d)shows the current generated and supplied to thelevel conversion circuit. It was generated only when the inputsignal changed. Comparing Fig. 5(c) with Fig. 5(d), the currentsupplied to the level conversion current was slightly higherthan . This was because the parasitic coupling capacitance be-tween the drain and gate terminals in MP6 in Fig. 3 affected thegate voltage ofMP2when OUT changed. This effect can be mit-igated by reducing the parasitic capacitance (e.g., by changingthe transistor sizes) or by adding a bypass capacitor between thegate voltage of MP2 and (or GND).

B. Comparison With Other Level Shifter Circuits

The performance comparison of the proposed LS circuit wasperformed using conventional circuit (Fig. 1) and other LS cir-cuits published in [8], [10], [12]. In the conventional circuit(Fig. 1), MN1 and MN2 were set 100 times larger than MP1and MP2 so that the low-voltage signals would be convertedcorrectly. We designed the LS circuits so that they occupy al-most same area as the proposed one for fair comparison [8],[10], [12].Fig. 6(a) and (b) shows delays and power dissipations of each

LS circuit as function of at V andkHz. The conventional LS circuit could not operate correctlyat V. This was because the drive current of thepull-down transistors decreased drastically as decreased.

TABLE IIMAXIMUM NOISE VOLTAGE

NOTE: was set to 0.4 V and conventional LS circuit could not operateat the .

The LS circuit in [12] dissipated more power than other onesbecause it was based on a current mirror circuit to achieve bal-anced drive current between pull-down and pull-up transistors.The power dissipation of the proposed LS circuit was compa-rable to other LS circuits. Fig. 6(c) and (d) shows delays andpower dissipations of each LS circuit as function of at

V and kHz. Compared with other LScircuits, the proposed circuit showed almost the same perfor-mances as other ones.We simulated input noise characteristics in each LS circuit.

and were set to 0.4 and 3.0 V, respectively. We ap-plied sine wave as a noise signal into IN and INB, respectively.Because the delays of LS circuits operated at Vare large as shown in Fig. 6(a), the LS circuits cannot respondto high frequency signals. Therefore, we applied low frequencynoise signals of 1 Hz. Table II shows themaximum noise voltagewhen LS could not operate correctly. When the input noise wasapplied to IN, there was no difference among LS circuits. This


TABLE IIICHIP AREA COMPARISON AND RESULTS OF MONTE CARLO SIMULATIONS FOR 500 RUNS

NOTE1: is the simulated minimum supply voltage of Monte Carlo simulation results.NOTE2: Numbers represent number of successes.

was because the switching voltage of the inverter determines thenoise immunity of the LS circuits. When the input noise was ap-plied to INB, the proposed LS circuit was more tolerant to otherLS circuits because the proposed LS circuit generates OUT ac-cording to the difference in the voltage of IN and INB. In con-trast, the output node of the other LS circuits were affected di-rectly by the noise voltage at INB because the drive current ofthe pull-down transistor for the output node was sensitive to thenoise voltage of INB.To investigate circuit operation against process and temper-

ature variations, we performed Monte Carlo statistical circuitsimulations assuming die-to-die (D2D) global variations andwithin-die (WID) random mismatch variations in all MOSFETsusing the parameters provided by the manufacturer with varioustemperature conditions [14]. We compared the performance ofthe proposed circuit with those of a conventional circuit andother circuits [8], [10], [12]. The amplitude of was setto 0.4 V, 0.5 V, or 0.6 V. The input pulse frequency wasset to very slow frequency (i.e., 1 Hz) to evaluate correct levelconversion operation at lower . Table III shows the eval-uated results of each chip area, the number of success runs thatthe LS circuits correctly converted the low-voltage signals intohigh-voltage signals, and the minimum , which each LScircuit could convert all the inputs correctly, with Monte Carlosimulations for 500 runs. Note that we calculated each chip areafrom their transistor sizes and the areas were normalized withthat of the proposed circuitThe conventional and reported LS circuits could not operate

correctly under lower-temperature and lower-supply-voltageconditions due to their poor drive current. In contrast, theproposed LS circuit could operate robustly under all condi-tions because it does not depend on the balance between thenMOSFET and pMOSFET drive currents. The minimumof the proposed circuit was 0.35 V. The minimum wasdecided by functional errors either in the low-voltage digitalcircuits or in the differential pair of the LS circuit.In advanced CMOS process technologies, the impact of

process variations will increase [14]. However, from abovesimulation results and discussions, it is proved that the proposedLS circuit is more tolerant to the variations than other ones.

IV. EXPERIMENTAL RESULTS

We fabricated a proof-of-concept chip using a 0.35- m,2-poly, 4-metal standard CMOS process. Fig. 7 shows a micro-

Fig. 7. Chip micrograph and partially enlarged view (area: 1880 m ).

Fig. 8. Measurement setup.

graph of the chip and a partial enlarged view of the proposedLS circuit, which had occupied an area of 1880 m . Thetransistor sizes of the fabricated LS circuit were the same asthose of the simulated LS circuit (see Table I). Fig. 8 shows ameasurement setup for the LS circuit. We used an inverter as aload circuit of the LS circuit. The power dissipation of the LScircuit was measured excluding a charge and discharge currentfor the I/O buffer.

A. Logic Error Correction Circuit (LECC)

As discussed in Section II, the characteristics of the LECC de-pend on output voltage . Therefore, we measured the cir-cuit performance for various values of . andwere set to 0.4 and 3.0 V, respectively.Fig. 9(a) shows current measured in the LECC shown in

Fig. 3 as a function of . IN and INB were respectivelyset to 0 and 0.4 V. When increased from Low, the circuit


Fig. 9. Measured current as function of (a) when IN and INB were Low and High and (b) when IN and INB were High and Low.

Fig. 10. Measured maximum current as function of (a) when IN and INB were Low and High and (b) when IN and INB were High and Low.

generated when exceeded 0.5 V. That is, the increase inunder the condition V caused the logic levels of

IN and OUT to no longer correspond, which caused the circuitto generate current (and not ), which pulled OUT down toGND (Low level). The maximum current was about 20 nA.Fig. 9(b) shows the measured current in the LECC shown

in Fig. 3 as a function of . IN and INB were respectivelyset to 0.4 and 0 V, the opposite of the case shown in Fig. 9(a).When decreased from High, the circuit generated when

dropped below 2.5 V. That is, the decrease in underthe condition V caused the logic levels of IN andOUT to no longer correspond, which caused the circuit to gen-erate current (and not ), which pulled OUT up to(High level). The sharp drop in at 2.5 V was because thefirst stage, consisting of MP1 and MN3 in the HLECC, is basedon of a common source amplifier, which leads to sharp currenttransitions.Fig. 10 shows the measured maximum in the LECC as a

function of (a) when IN and INB were Low and Highand (b) when IN and INB were High and Low. The maximumcurrents under both conditions had the same characteristics andincreased exponentially with in the range 0.4 to 0.6 V.When the voltage was higher than 0.6 V, they increased gradu-ally with because both maximum currents are determinedby .

B. Level Shifter Circuit

Fig. 11 shows the measured input and output waveforms ofthe proposed LS circuit at 10 kHz. The circuit converted the0.4-V signal into a 3-V signal.Fig. 12 shows a shmoo plot of the operating frequency as a

function of . The maximum operating frequency increased

Fig. 11. Measured waveforms of proposed LS for 10-kHz input pulse.

Fig. 12. Shmoo plot.

exponentially with in the range 0.4 to 0.6 V because thecurrent generated in the LECC increased exponentially with


TABLE IVPERFORMANCE SUMMARY AND COMPARISON

[12] , [13] : Simulation results.

Fig. 13. Measured power dissipations as a function of at input pulsefrequencies of 0.1, 1, and 10 kHz.

Fig. 14. Measured power dissipation as a function of at the input pulsefrequency of 10 kHz.

, as shown in Fig. 10. When the voltage was higher than0.6 V, the operating frequency increased gradually withbecause the current when is above the threshold voltagealso increases in the same manner.Figs. 13 and 14 show the measured power dissipation as a

functions of and , respectively. For Fig. 13, thepower was measured at input pulse frequencies of 0.1, 1, and10 kHz, and for Fig. 14, it was measured at 10 kHz. As shownin Fig. 13, the power dissipation decreased as input pulse fre-quency decreased and was independent of at a fixedpulse frequency. As shown in Fig. 14, the power dissipation in-creased with the square of . These results can be explainedas follows.The maximum current generated by the LECC is expressed

as different equations according to . When is lower

and higher than the threshold voltage of the MOSFET, thecurrents are expressed as

(2)

(3)

respectively, where is the aspect ratio of the tran-sistor, is the process-dependent param-eter, is the carrier mobility, is the gate-oxidecapacitance, is the oxide permittivity, is the oxide thick-ness, is the subthreshold slope factor, is thethermal voltage, is the Boltzmann constant, is the abso-lute temperature, and is the elementary charge [15]. Becauseperiod during which the LECC generates the current dependson the propagation delay of the low voltage digital circuit, canbe expressed as

(4)

where is a constant and is the next-stage load capacitanceof the LS circuit. Note that, from (2), (3), and (4), we can ex-plain the performance characteristics of measured current andoperating frequency as shown in Figs. 10 and 12. The powerdissipation of the proposed LS circuit can be expressed asthe sum of the internal power dissipation of the LS circuitand the power dissipation for a charge and discharge cur-rent of the load capacitance . Note that leakage power of thecircuit is ignored in this analysis and that the includes thepower dissipation for a charge and discharge current of the in-ternal node. Because the LECC generates operating current onlywhen IN and OUT do not correspond, the power dissipation ofthe proposed LS circuit can be expressed as

(5)

where is the average current flowing through the circuit.Equation (5) shows that is independent of and dependson and the square of .The active power dissipation of the LS circuit was extremely

low, 58 nW at an input frequency of 10 kHz; the corre-sponding energy was 5.8 pJ. Static power dissipation


without applying input pulses was 225 pW. The measuredminimum , which the LS circuit converted into 3 V, was0.23 V.Table IV summarizes the performance of the proposed LS

circuit and compares it with that of other ones [8]–[13]. Thes and the input frequencies for energy are shown

in parentheses. The proposed circuit can convert low voltageinput signals in subthreshold digital circuits to high output sig-nals independently of the supply voltage difference. In addition,it reduces the static power dissipation because current is gener-ated only when IN and OUT do not correspond.

V. CONCLUSION

We presented a level shifter circuit for extremely low-voltagedigital LSIs. The proposed circuit consists of a logic error cor-rection circuit and a level conversion circuit. It can convertlow-voltage digital input signals into high-voltage digitaloutput signals and achieve low power operation because itdissipates current only when the input signal changes. Wefabricated a proof-of-concept chip using a 0.35- m CMOSprocess and demonstrated its operation by measurements. Thecircuit converted a 0.23-V input signal into a 3-V output signal.The power dissipation was 58 nW for a 0.4-V 10-kHz inputpulse. The proposed circuit is applicable to ultra-low-voltagedigital circuit systems co-existing with high-voltage digitalcircuit systems.

REFERENCES

[1] A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-threshold De-sign for Ultra Low-Power Systems. New York: Springer, 2006.

[2] A. Wang and A. Chandrakasan, “A 180 mV FFT processor using sub-threshold circuit techniques,” in IEEE ISSCC Dig. Tech. Papers, 2004,pp. 292–293.

[3] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “CMOS smart sensorfor monitoring the quality of perishables,” IEEE J. Solid-State Circuits,vol. 42, no. 4, pp. 798–803, 2007.

[4] B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand,S. Pant, D. Blaauw, and T. Austin, “A 2.60 pJ/inst subthreshold sensorprocessor for optimal energy efficiency,” in Dig. Symp. VLSI Circuits,2006, pp. 154–155.

[5] S. Henzler, PowerManagement of Digital Circuits in Deep Sub-MicronCMOS Technologies. New York: Springer, 2007.

[6] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “A level shiftercircuit design by using input/output voltage monitoring technique forultra-low voltage digital CMOS LSIs,” in Proc. NEWCAS Conf., 2011,pp. 201–204.

[7] Y. Osaki, T. Hirose, N. Kuroki, and M. Numa, “A level shifter withlogic error correction circuit for extremely low-voltage digital CMOSLSIs,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), 2011, pp.199–202.

[8] Y. Kim, D. Sylvester, and D. Blaauw, “LC : Limited contention levelconverter for robust wide-range voltage conversion,” in Dig. Symp.VLSI Circuits, 2011, pp. 188–189.

[9] Y. Moghe, T. Lehmann, and T. Piessens, “Nanosecond delay floatinghigh voltage level shifters in a 0.35 m HV-CMOS technology,” IEEEJ. Solid-State Circuits, vol. 46, pp. 485–497, 2011.

[10] H. Shao and C.-Y. Tsui, “A robust, input voltage adaptive and lowenergy consumption level converter for sub-threshold logic,” in Proc.ESSCIRC, 2007, pp. 312–315.

[11] Y. Kanno, H. Mizuno, K. Tanaka, and T. Watanabe, “Level converterswith high immunity to power-supply bouncing for high-speed sub-1-VLSIs,” in Dig. Symp. VLSI Circuits, 2000, pp. 202–203.

[12] S. Lütkemeier and U. Rückert, “A subthreshold to above-thresholdlevel shifter comprising a wilson current mirror,” IEEE Trans. CircuitsSyst. II, Exp. Briefs, pp. 721–724, 2010.

[13] O.-S. Kwon and K.-S. Min, “Fast-delay and low-power level shifter forlow-voltage applications,” IEICE Trans. Electron., vol. E90-C, no. 7,pp. 1540–1543, 2007.

[14] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers,“Matching properties of MOS transistors,” IEEE J. Solid-State Cir-cuits, vol. 24, pp. 1433–1439, 1989.

[15] Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices.Cambridge, U.K.: Cambridge Univ. Press, 2002.

Yuji Osaki (S’09) received the B.E. and M.E.degrees in electrical and electronic engineering fromKobe University, Kobe, Japan, in 2008 and 2010,respectively. He is currently working toward thePh.D. degree in electrical and electronic engineeringat Kobe University, Kobe, Japan.His current research interests are in ultra-low-

power CMOS circuits.Mr. Osaki is a member of the Institute of Elec-

tronics, Information and Communication Engineers(IEICE).

Tetsuya Hirose (M’05) received the B.S., M.S., andPh.D. degrees from Osaka University, Osaka, Japan,in 2000, 2002, and 2005, respectively.From 2005 to 2008, he was a Research Asso-

ciate at the Department of Electrical Engineering,Hokkaido University, Japan. He is currently anAssociate Professor of the department of Electricaland Electronics Engineering, Kobe University,Kobe, Japan. His current research interests are inthe field of nano-watt-power analog/digital mixedsignal integrated circuits design and human-centric

intelligent electronic systems.Dr. Hirose is a member of the Institute of Electronics, Information and

Communication Engineers (IEICE) and the Japan Society of Applied Physics(JSAP).

Nobutaka Kuroki received the B.E., M.E., andDr. Eng. degrees in electronic engineering fromKobe University, Japan, in 1990, 1992, and 1995,respectively.From 1995 to 2005, he was a Research Associate

in the Department of Electrical and ElectronicEngineering, Kobe University. He has been an As-sociate Professor since 2006. His research interestsinclude digital signal processing and digital imageprocessing.Dr. Kuroki is a member of the IEEJ, IEICE, and

ITE.

Masahiro Numa (M’96) received the B.E., M.E.,and Dr. Eng. degrees in precision engineering fromthe University of Tokyo, Tokyo, Japan, in 1983,1985, and 1988, respectively.He is currently a Professor with the Department of

Electrical and Electronic Engineering, Kobe Univer-sity, Kobe, Japan. His research interests include CADand low-power design methodologies for VLSI, andimage processing.Prof. Numa served as the Technical Program Com-

mittee Chair of the 17th Workshop on Synthesis AndSystem Integration of Mixed Information technologies (SASIMI 2012). He is amember of the ACM, IPSJ, and IEICE.

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