ORI001101 RAC6610 Hardware System ISSUE2.0

72
Wireless Curriculum Development Section Wireless Curriculum Development Section ISSUE ISSUE ORI001101 RAC6610 ORI001101 RAC6610 Hardware System Hardware System 2.0 2.0

Transcript of ORI001101 RAC6610 Hardware System ISSUE2.0

Page 1: ORI001101 RAC6610 Hardware System ISSUE2.0

Wireless Curriculum Development SectionWireless Curriculum Development SectionWireless Curriculum Development SectionWireless Curriculum Development Section

ISSUEISSUE

ORI001101 RAC6610 ORI001101 RAC6610 Hardware System Hardware System

ORI001101 RAC6610 ORI001101 RAC6610 Hardware System Hardware System

2.02.0

Page 2: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

ObjectiveObjective

State the structure of RAC6610.

Know about the function of all

boards in RAC6610.

Once completion of this course, you will:

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Security Level: Internal

ContentsContents

Chapter 1 Overview

Chapter 2 CIPS

Chapter 3 CRPS

Chapter 4 Clock System

Chapter 5 Summary

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Chapter 1 Overview of WLL BSCChapter 1 Overview of WLL BSC

CDMA WLL Network Structure

RAC6610 Configuration

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CDMA WLL Network StructureCDMA WLL Network Structure

LE

MIP HA

AAA

PDSN/FA

Abis

BTS

A10/A11

Um

V5

LEV5Optical

FiberSoftsite

Um

Remote Model

AbisE1/STM-1

Module

RAC6610

BTS

BTS

SMC

Abis

FWT

INTERNET

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Configuration for 10,000 SubscribersConfiguration for 10,000 Subscribers

BHCA: 120kTraffic amount: 900 ErlChannels on Um interface: 1,350TCETranscoder (TC): 1,024Echo Canceller (EC): 1,024Maximum number of carrier sectors: 96BTS trunking capability: 32E1 PSTN trunking capability: 32E1 Number of V5 interface circuits: 960Number of PPP connections:3,5000Number of PPP activated connections:

25,00 Packet data service throughput: 10MbpsBusy Hour Short Message processibility: 120K BHSM

CRPS

CIPS

A3/A7

V5 Abis

A10/A11

BAM

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Configuration for large capacity(1,500,000)Configuration for large capacity(1,500,000)

BHCA: 120k15 Traffic amount: 900Erl15 Channels on Um interface: 1,350TCE15 Transcoder: 1,024(15 Echo Canceller (EC): 1,024 15 Maximum number of carrier sectors: 96 15 (according to the actual needs) BTS trunking capability: 32E1 15 PSTN trunking capability: 32E1

15 Number of V5 interface circuits:

960 15 Number of PPP connections and

PPP activated : set according to the actual needs

CRPS

CIPS

CSWS

Abi s

V5

CIPS Abi s

V5

CIPS Abi sV5

CIPS Abi s

V5

A3/A7A10/A11

For Large capacity, CSWS must be used!

….

BAM

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Security Level: Internal

Structure of CabinetStructure of Cabinet

Power distribution box

Mouse Keyboard and LCD

Air guide subrackFan box

Cable trough

Air guide subrack

Fan boxCable trough

Cable trough

Dummy panel

Cable trough

Lanswitch

BAM Switch

Lanswitch

BAM Server

BAM Server

BAM Server

BAM Server

Satellite clock receiving module

CRPS

CIPS

Control cabinet

Servicecabinet, used for more than

10,000 subscribers

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Security Level: Internal

ContentsContents

Chapter 1 Overview of WLL BSC

Chapter 2 CIPS

Chapter 3 CRPS

Chapter 4 Clock System

Chapter 5 Summary

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Chapter 2 CIPSChapter 2 CIPS

Session 1 Overview of CIPSSession 1 Overview of CIPS

Session 2 Introduction to Boards in

CIPS

Session 3 Traffic & Signaling Flow

in CIPS

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CIPS Subrack layoutCIPS Subrack layout

CXI E/CBIE

CFMR

CFMR

CFMR

CIWF

CEVC

CEVC

CMUX

CMUX

CEVC

CEVC

CLCB

CSPU

CSPU

CIWF

CAI E

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Main function of CIPSMain function of CIPS

V5 physical interface

V5 signaling processing

AbisPhysicalinterface

Signaling control

Speech encoding and decoding.

Service frame

selection, data

allocation

To CRPSTo CRPS

To STE/LETo STE/LE

To STE/LETo STE/LE

Abis OMLAbis OML

Abis signalingAbis signaling

Abis trafficAbis traffic

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Chapter 2 CIPSChapter 2 CIPS

Session 1 Overview of CIPS

Session 2 Introduction to boards in Session 2 Introduction to boards in

CIPSCIPS

Session 3 Traffic & Signaling Flow

in CIPS

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Security Level: Internal

Function of CXIEFunction of CXIE

1#E1

2#E1

n#E1… ...

IMA Chip

IMA Chip

E1 Interface Module

IMA Processing Module

IMA Processing Module

E1 Interface Module

High -rate ATM flow High -rate ATM flow

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Function of CXIEFunction of CXIE

E1/T1 interface function: supporting 24 standard E1s/T1s.

Providing a processing capability of 24 E1/T1 IMAs and supporting pure ATM over E1 mode (namely UNI mode);

While providing the Abis interface between BTS and BSC, it performs the function of AAL2 switching and AAL5 transparent transmission;

While providing the Abis interface between BTS and BSC, it performs the function of AAL2 switching and AAL5 transparent transmission;

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Panel Description of CXIEPanel Description of CXIE

Normal status:Status Indicator (RUN): flash slowlyAlarm indicator (ALM): offOperation indicator(ACT): on

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CBIECBIE

32 standard E1/T1 interfaces

Providing a processing capability of 32 E1/T1 IMAs and supporting pure ATM over E1 mode (UNI mode)

the channels for inter-working between CIPS and CRPS (Small capacity BSC)

Board’s introduction

CBIE is responsible for:

Supporting Fractional ATM function

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CBIE AppearanceCBIE Appearance

To BTS

Board’s introduction

To BTS

J18

RUN

ALM

ACT

CLK1

E1/T1

CLK2

E1/T1

E1/T1

E1/T1

S14

S12

S13

S11

S10

S6

S5

S15

S16

S9

S8

S7

S17

J19 J18

J21

To BTS

To BTS

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Function of CFMRFunction of CFMR

Selection/DistributionSelection/Distribution

BTS1 BTS2

Power controlPower control

Service Frame

Service Frame

Frame protocol processing

Frame protocol processing

Frame protocol processing

Frame protocol processing

Best Frame

Multiplexing/DemultiplexingMultiplexing/Demultiplexing

LAC SARLAC SAR

LAC PDU

TRAU frame TRAU frame RLPRLP

CSPUCSPU CEVCCEVC CPPUCPPU

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Panel Description of CFMRPanel Description of CFMR

RUN

ALM

ACT

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Function of CEVCFunction of CEVC

Supporting three coding modes: EVRC,

QCELP8K and QCELP13K; Performing ISLP rate adaptation for circuit

data services below 64k;

Checking and Inserting DTMF signals;

Providing the echo cancellation function

between MS-PSTN;

Notes: The CEVC’s hardware structure is the same as that of CFMR’s.So does the indicator meanings of CEVC.

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The switching and multiplexing functions of the

ATM services;

Function of CMUXFunction of CMUX

AAL2 switching function;

Providing a synchronization clock function;

Managing and monitoring the software loading of all boards in the local subrack;

Monitoring the power subrack, fan box and envir

onment operating status.

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Panel Description of CMUXPanel Description of CMUX

ETH

1PPS

COM1

COM2

¹ â¿ Û° å

RUN

ALM

ACT

RESET

TX

RX

Optical Pinch Plate

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Function of CIWFFunction of CIWF

Asynchronous data;

G3 fax ;

Analog fax

IWF service processing board, optional. It is configured when the IWF function is required. A CIWF is able to process 60 integrated IWF service. A CIPS may be configured with up to 2 CIWFs in slots 4 and 14 in which the former is preferable.

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Function of CSPUFunction of CSPU

Processing the upper-layer signaling :Um interface,Abis interface, V5 interface, A3 interface,A7 interface A9 interface;

Allocating various resources needed for setup signaling and traffic connections;

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Panel Description of CSPUPanel Description of CSPU

RUN

ALM

ACT

Page 27: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

Function of CLCBFunction of CLCB

V5 signaling proceesing.(Layer2)

Measurement, maintenance and troubleshooting

of V5 signaling

Page 28: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

CAIECAIE

Provide 32 E1/T1 interfaces

TDM switching and rate conversion

Clock extraction

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Security Level: Internal

CAIE AppearanceCAIE Appearance

S5 S4 S9 S8

S6

S7

S11

S12S15S18

S3 S2 S16 S17 S10 S13

J18

RUN

ALM

ACT

CLK1

E1/T1

CLK2

E1/T1

E1/T1

E1/T1

Used to connect to GCKP

Used to connect to LE

Page 30: ORI001101 RAC6610 Hardware System ISSUE2.0

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Chapter 2 CIPSChapter 2 CIPS

Session 1 Overview of CIPS

Session 2 Introduction to boards in

CIPS

Session 3 Traffic & Signaling Flow Session 3 Traffic & Signaling Flow

in CIPSin CIPS

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Security Level: Internal

Voice Traffic Flow in CIPSVoice Traffic Flow in CIPS

CXIE CFMR CMUX CEVC CAIE

ATM Bus

Expand TDM Bus

TDM Bus

Page 32: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

Data Traffic Flow in CIPSData Traffic Flow in CIPS

CXIE CFMR

ATM Bus

CBTS CRPS

CMUX

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Voice Signaling Flow in CIPSVoice Signaling Flow in CIPS

CXIE CFMR CSPU CMUX CAIE

ATM BUS

Expand TDM Bus

TDM BUS

CLCB

Outband Signaling

Inband Signaling

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Data signaling Flow in CIPSData signaling Flow in CIPS

CXIE CFMR CSPU

ATM Bus

Outband signaling To CRPS

Inband signaling

To CBTS

CMUX

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ContentsContents

Chapter 1 Overview of WLL BSC

Chapter 2 CIPS

Chapter 3 CRPS

Chapter 4 Clock System

Chapter 5 Summary

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Chapter 3 CRPSChapter 3 CRPS

Session 1 Overview to CRPSSession 1 Overview to CRPS

Session 2 Introduction to CRPS

Session 3 Traffic & Signaling

Flow in CRPS

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CRPS Subrack layoutCRPS Subrack layout

CXI E

CLIU

CRMU

CRMU

CSMU

CSMU

CUMB

CMUX

CMUX

CUMB

CPPU

CBPU

CPCU

CHAC

CLIU

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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Provide periodical time synchronization

Inter-subrack interworking switching

Packet data service processing

Main function of CRPSMain function of CRPS

Provide A3/A7

physical interface

Subscriber data management

Resource management

Packet data AAL5 CellsPacket data AAL5 Cells

From original CIPSFrom original CIPS

From original CIPSFrom original CIPS

To Service SubrackTo Service SubrackFrom UTCPFrom UTCP

To IWFTo IWF

GRE PacketGRE Packet

To target CIPSTo target CIPS

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Chapter 3 CRPSChapter 3 CRPS

Session 1 Overview to CPRS

Session 2 Introduction to CRPSSession 2 Introduction to CRPS

Session 3 Traffic & Signaling

Flow in CRPS

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Security Level: Internal

Function of CUMBFunction of CUMB

Subscriber Data Management

Paging control

Notes:

The CUMB’s hardware structure is the same as that of CSPU’s.

So does the indicator meanings of CUMB.

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Function of CRMUFunction of CRMU

Notes: The CRMU’s hardware structure is the same as that of CSPU’s.So does the indicator meaning of CRMU.

Processing and distributing the signaling of the A3 interface, A7 interface and A9 interface.

Maintaining, managing and distribution of the A2

interface, A3 interface and A8 interface resources;

Page 42: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

Function of CSMUFunction of CSMU

Providing Reduced TDMA Frame Numbers (RFN) and a 32-bit

Providing two sets of backplane interfaces

RFN counterPerforming SAR processing for AAL5 cells at 400Mbps

RUN

ALM

ACT

ETH1

ETH2

Page 43: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

Function of CLIUFunction of CLIU

CLIU provides ATM optical interface for the connection with the CMUX in CIPS. It bears the inter-subrack signaling and traffic.

The switching and multicast functions of the ATM services

Providing synchronization clock distribution function

Providing optical interface backup

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A9 Signaling

Function of CPCUFunction of CPCU

Signaling Processing A11 Signaling

CBPU and PPU Session resource management

Setup of signaling and traffic connection

Packet call status

Maintaining Notes:

The CPCU’s hardware structure is the same as that of CSPU’s.

So does the indicator meanings of CPCU.

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Security Level: Internal

Function of CPPUFunction of CPPU

Packet processing on A10

GRE packet encapsulating & unencapsulating

Packet storing and transferring

Performance Statistics

Resource checking

Notes: The CPPU’s hardware structure is the same as that of CSPU’s.So does the indicator meanings of CPPU.

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Function of CBPUFunction of CBPU

Downlink data buffering, processing and transferring

Transferring SDB data to CPCU

Re-sequencing the packet

Notes: The CBPU’s hardware structure is the same as that of CSPU’s.So does the indicator meanings of CBPU.

Page 47: ORI001101 RAC6610 Hardware System ISSUE2.0

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Function of CHACFunction of CHAC

Transferring the A10 traffic data from PDSN to CBPU;

Processing the A8 traffic data from CPPU and SDB data from

CPCU, and transferring them to PDSN via the A10 interface;

Transferring directly the A11 signaling data from PDSN to

CPCU;

Transferring directly the A11 signaling data from CPCU to

PDSN;

Providing 1000M Ethernet interface to PDSN and supporting RFC826 (Ethernet ARP) protocol.

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Security Level: Internal

Panel Description of CHACPanel Description of CHAC

RUNALM

RESET

O1GIE

TX

RX

SW1

¿ Û° å

TX

RX

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Chapter 3 CRPSChapter 3 CRPS

Session 1 Overview to CPRS

Session 2 Introduction to CRPS

Session 3 Traffic & Signaling Session 3 Traffic & Signaling

Flow in CRPSFlow in CRPS

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Downlink Data Flow in CRPSDownlink Data Flow in CRPS

CHAC CBPU CPPU CLIU

To PDSN To CIPS

ATM Bus

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Uplink Data Flow in CRPSUplink Data Flow in CRPS

CHAC CBPU CPPU CLIU

To PDSN To CIPS

ATM Bus

Page 52: ORI001101 RAC6610 Hardware System ISSUE2.0

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Data Signaling flow in CRPSData Signaling flow in CRPS

CHAC CPCU CRMU CLIU

To PDSN To CIPS

ATM Bus

Page 53: ORI001101 RAC6610 Hardware System ISSUE2.0

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ContentsContents

Chapter 1 Overview of WLL BSC

Chapter 2 CIPS

Chapter 3 CRPS

Chapter 4 Clock System

Chapter 5 Summary

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Types of SynchronizationTypes of Synchronization

Transmission Synchronization

Synchronization between BSC and LE

Time Synchronization

Synchronize the radio frame number between BSC and BTS

Clock system

Page 55: ORI001101 RAC6610 Hardware System ISSUE2.0

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CCRMCCRM

CCRM (Satellite synchronization Clock Receiver Module ) is compose

d of two parts:

GCKP (GPS/GLONASS& ClocK Processing Board )

GCKB (Backplane of CCRM )

Panel of GCKP (Active/Standby) RUNALM ACT COM IN0 IN1 OUT ANT RUNALM ACT COM IN0 IN1 OUT ANT

CLK_B COM_B ETH_B CLK_A COM_A ETH_A

Panel of GCKB

Panel of GCKP (Active/Standby)

Functions

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BSC Clock System StructureBSC Clock System StructureFunctions

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Physical ConnectionPhysical Connection

TXRX

ETH

1PPS

COM1

COM2

RUN

ALM

ACT

RESET

7#CMUX(CRPS)

CLK1

CLK2

E1/T1

E1/T1

E1/T1

E1/T1

RUN

ALM

ACT

CAIE

GCKP

RUNALM ACT COM IN0 IN1 TEST ANT

ETH_BCOM_BCLK_B ETH_ACOM_ACLK_A

GCKB

TXRX

ETH

1PPS

COM1

COM2

RUN

ALM

ACT

RESET

8#CMUX(CRPS)

Functions

Page 58: ORI001101 RAC6610 Hardware System ISSUE2.0

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Security Level: Internal

ContentsContents

Chapter 1 Overview of WLL BSC

Chapter 2 CIPS

Chapter 3 CRPS

Chapter 4 Clock System

Chapter 5 Summary

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Chapter 5 SummaryChapter 5 Summary

Session 1 Software Loading Flow

Session 2 Summary of Signaling Flow

Session 3 Summary of Traffic Flow

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Software Loading FlowSoftware Loading Flow

BAM

CMUXin CRPS

Other boards in CRPS

CMUXin CIPS

Download Data/Software

Download Data/Software

Other boardsIn CIPS

…… ……

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Chapter 5 SummaryChapter 5 Summary

Session 1 Software Loading Flow

Session 2 Summary of Signaling FlowSession 2 Summary of Signaling Flow

Session 3 Summary of Traffic Flow

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Voice Signaling FlowVoice Signaling Flow

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Packet data signalling flow Packet data signalling flow

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IWF signalling flowIWF signalling flow

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receive a short message receive a short message

CUMB

CSMU

CXIE

CFMR

CSPU

CBTS

MC

CRPS

Outband signaling

AbisMS

Um

(a)(b)

(e)(c)

(d)

(f)

(g)

(h)

(i)

CIPS

CRMU

CUMB of target RAC6610

(b)

(c)

(i)

/CBIE

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send a short message send a short message

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Chapter 5 SummaryChapter 5 Summary

Session 1 Software Loading Flow

Session 2 Summary of Signaling Flow

Session 3 Summary of Traffic FlowSession 3 Summary of Traffic Flow

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Voice traffic flow Voice traffic flow

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Packet data traffic flow Packet data traffic flow

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IWF traffic flowIWF traffic flow

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Voice Traffic FlowVoice Traffic Flow

CAI E

CIWF

CSPU

CLCB

CEVC

CMUX

CFMR

CXI E

CPPU

CBPU

CRMU

CMUX

CUMB

CPCU

CHAC

CLI U

CXI E

CAI E

CIWF

CSPU

CLCB

CEVC

CMUX

CFMR

CXI E

Original CIPSTarget CIPS

V5 subscribers are bound to V5 Interface.

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