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Fl Fl ITI I B l R U Fl IV E R S ITY 13 Starch Street T: +264 61 207 2258 Private Bag13388 F: +264 61 207 9258 OF SCIEIICE HUD TECHNOLOGY Windhoek E: [email protected] NAMlBlA W; www.nust.na Faculty of Computing and Informatics Department of Computer Science FACULTY OF COMPUTING AND INF ORMATICS DEPARTMENT OF COMPUTER SCIENCE QUALIFICATION: Bachelor of (Computer Science, Informatics & Cyber Security) QUALIFICATION CODE: 07BACS,07BAIF,O7BCCS LEVEL: 5 COURSE: Computer Organisation and Architecture COURSE CODE: COA51 IS DATE: JULY 2017 SESSION: THEORY DURATION: 2 Hours MARKS: 100 SECOND OPPORTUNITY/SUPPLEMENTARY EXAMINATION PAPER EXAMINER(S): MR. JULIUS SILAA MS. ALBERTINA SHILONGO MR. JEREMIAH LUMBASI MR. PINTO BAULETH MS. EUNICE MBASUVA MODERATOR: DR. FUNGAI BHUNU SHAVA THIS PAPER CONSISTS OF 5 PAGES (INCLUDING THIS FRONT PAGE) INSTRUCTIONS Answer all questions in the answer sheet provide. Ensure that your writing is legible, neat and presentable. No notes or any other additional material may be used in this examination. Calculators may be used, but remember to show step by step process of your working. PWN.‘ Page 1 of 5

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Fl Fl ITI I B l R U Fl IV E R S ITY 13 Starch Street T: +264 61 207 2258

Private Bag13388 F: +264 61 207 9258

OF SCIEIICE HUD TECHNOLOGY Windhoek E: [email protected] W; www.nust.na

Faculty of Computing and Informatics

Department of Computer Science

FACULTY OF COMPUTING AND INFORMATICS

DEPARTMENT OF COMPUTER SCIENCE

QUALIFICATION: Bachelor of (Computer Science, Informatics & Cyber Security)

QUALIFICATION CODE: 07BACS,07BAIF,O7BCCS LEVEL: 5

COURSE: Computer Organisation and Architecture COURSE CODE: COA51 IS

DATE: JULY 2017 SESSION: THEORY

DURATION: 2 Hours MARKS: 100

SECOND OPPORTUNITY/SUPPLEMENTARY

EXAMINATION PAPER

EXAMINER(S): MR. JULIUS SILAA

MS. ALBERTINA SHILONGO

MR. JEREMIAH LUMBASI

MR. PINTO BAULETH

MS. EUNICE MBASUVA

MODERATOR: DR. FUNGAI BHUNU SHAVA

THIS PAPER CONSISTS OF 5 PAGES

(INCLUDING THIS FRONT PAGE)

INSTRUCTIONS

Answer all questions in the answer sheet provide.

Ensure that your writing is legible, neat and presentable.

No notes or any other additional material may be used in this examination.

Calculators may be used, but remember to show step by step process of your

working.

PWN.‘Page 1 of 5

SECTION A [10 MARKS]: Answer All Questions. Each Question Weighs 1 Mark.

1. The method of using the same lines for multiple purposes is known as time

multiplexing. [True/False]

2. Both sequential access and direct access involve a shared read-write

mechanism. [True/False]

3. To achieve greatest performance the memory must be able to keep up with

The processor. [True/False]

4. A static RAM will hold its data as long as power is supplied to it.[True/False]

5. Approach that allows for a high degree of instruction—level parallelism without

increasing circuit complexity or power consumption is called multithreading

[True/False]

6. Pipelining is a means of introducing parallelism into the essential sequential

nature of a machine-instruction program. [True/False]

7. The major cost in the life cycle of a system is hardware. [True/False]

8. Addition and subtraction can be performed on numbers in two

complement notation by treating them as unsigned integers. [True/False]

9. Claude Shannon, a research assistant in the Electrical Engineering

Department at M.l.T., proposed the basic principles of Boolean algebra.

[True/False]

10. A common measure of performance for a processor is the rate at which

instructions are executed, expressed as millions of instructions per

second (MIPS). [True/False]

SECTION B [10 MARKS]: Answer All Questions. Each Question Weighs 1 Mark.

1. A is a special type of programming language used to provide

Instructions to the monitor.

A. job control language B. multiprogram

C. kernel D. utility

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is implemented with combinational circuits.

A. Nano memory B. Random access memory

C. Read only memory D. No memory

provide storage internal to the CPU.

A. Control units B. ALUs

C. Main memory D. Registers

. The most fundamental type of machine instruction is the instruction.

A. conversion B. data transfer

C. arithmetic D. logical

. During the the opcode of the next instruction is loaded into the IR and

the address portion is loaded into the MAR.

A. Execute cycle B. Fetch cycle

C. Instruction cycle D. Clock cycle

.The determines the opcode and the operand specifiers.

A. decode instruction B. fetch operands

C. calculate operands D. execute instruction

. RAID level has the highest disk overhead of all RAID types.

A. O B. 1

C. 3 D. 5

instructions provide computational capabilities for processing number

data.

A. Boolean B. Logic

C. Memory D. Arithmetic

The only form of addressing for branch instructions is addressing.

A. register B. relative

C. base D. immediate

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10 Which of the following interrelated factors go into determining the use of the

addressing bits?

A. number of operands B. number of register sets

C. address range D. all of the above

SECTION C [80 MARKS]: Answer All Questions.

Question 1

(a)Briefly describe the following computing concepts [6 marks]

i. Aprocess

ii. Thread

iii. Multi-Threading

(b)Contemporary computer designs are based on concepts developed by John von

Neumann at the Institute for Advanced Studies, Princeton.

Summarise his main ideas of a contemporary computer [6 Marks]

(0) Why does the program execution speed generally increase as the number of

general purpose registers increases? [4 Marks]

(d) Briefly explain how data is stored on a magnetic mass storage device. [4 Marks]

Question 2:

(a) Briefly describe the significance of using multi-level caches? [4 Marks]

(b) Identify and fill in the blanks with the correct type of cache mapping scheme

[3 Marks]i. :a block can be placed anywhere in the cache

ii. :a block with a given address can only be placed in

a single location in the cache

iii. :a block can be placed anywhere within a set of

locations in the cache

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(c) Illustrate the concept of direct cache mapping by means of a simple diagram

[5 Marks]

(d) Briefly explain the key components of your cache diagram from question (c)

above [5 Marks]

(e) A cache is direct-mapped and has 64 KB data. Each block contains 32 bytes.

The address is 32 bits wide. [9 Marks]

i. What are the number of bits in each block? [2 Marks]

ii. What are the number blocks in cache? [2 Marks]

iii. Calculate the number of bits in the index field [2 Marks]

iv. Calculate the number of bits in the cache tag field [3 Marks]

Question 3

(a) What is a parity bit? [2 Marks]

(b) Perform binary Subtraction of (13)1ofrom 44)1oin 2’s complement method.

Show all of your working in Binary Coded Decimals on every step. [6 Marks]

(0) An Adder is a logical circuit that performs an addition operation on two binary

digits. The adder produces a sum and a carry value which are both binary digits

[20 Marks]

i) Draw a half adder circuit emphasizing the input, key logical gates and

output [10 Marks]

ii) Demonstrate input/out of your circuit by means of a truth table [5 Marks]

iii) Briefly describe how your half adder relates to the truth table [5 Marks]

(d) Explain any three components of an instruction set architecture. [6 Marks]

*****END OF PAPER*****

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