Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

25 NITTTR, Chandigarh EDIT-2015

Optimization for Minimum Noise Figure of RFLow Noise Amplifier in 0.18µm Technology

Minaxi Dassi1 and Rajnish Sharma2

Department of Electronics and Communication, Chitkara University, Himachal Pradesh, India1minaxi.dassi@chitkarauniversity.edu.in

2rajnish.sharma@chitkarauniversity.edu.in

Abstract – Using a modified Cascode topology a 2GHz LowNoise Amplifier (LNA) has been implemented in CadenceSpectre RF tool on UMC 0.18µm technology to work underreduced power supply. After simulation it is found that atresonance frequency of 2GHz, the minimum noise figure is2.5 dB and noise figure is 3 dB for a voltage gain of 17 dB.

Key Words:-RF circuit design, Low Noise Amplifier, 0.18µmtechnology.

I. INTRODUCTIONToday wireless communication is as ubiquitous aselectricity. At present no wireless device is incorporated inour ovens and refrigerators, but it is envisioned that awireless network will eventually be incorporated in ourhomes that will control every device and appliance.Flawless connections among our laptops, camcorders, cellphones, printers, digital cameras, TVs, microwave ovens,etc will be possible due to High-speed wireless links forexample Wi-Fi and Bluetooth connections. The mainreason for the recognition of wireless communication is the–decrease in the cost of electronics. Today’s cell phonesoffer many more functions and features: communicationmodes and many frequency bands, Wi-Fi, Bluetooth,storage, a digital camera, GPS, computing, and a user-friendly interface at about the same cost as those a decadeago. With the help of integration much more functionaldevices can be positioned on a single chip. The integration,in turn, is responsible for its steady rise to (1) innovationsin RF architectures, circuits, and devices and (2) thescaling of VLSI processes in CMOS technology. With thehigher integration levels there is improvement in theperformance of RF circuits. For example, the speed of RFcircuits for a given function has increased with thedecrease in the power consumption.

II. CHALLENGES IN RF DESIGNThe design and implementation of transceivers and RFcircuits remained very challenging irrespective of manydecades of research work on microwave theory, RF and onRF ICs [1]. There are three reasons for this condition.Firstly, RF design draws upon a huge number ofdisciplines and requires a good understanding of fields thatseems irrelevant to integrated circuits as shown in Fig 1.For more than half a century most of these fields have beenunder research and study, presenting a enormousknowledge required by a person to enter RF IC design.

Fig1: Various disciplines necessary in RF design [1]

Secondly, there are numerous trade-offs, summarized inthe “RF design hexagon” as shown in Fig 2 that RF circuitsand transceivers must deal with. For example, for a frontend amplifier in order to decrease the noise we need toconsume the greater power or sacrifice linearity.

Fig. 2 RF design hexagon [1]

Third, there are new challenges to meet the demand forlower cost, higher performance, and greater functionality.In 1990s, the early work on RF IC design strove tointegrate on a single chip only one transceiver with thedigital baseband processor. On the other hand, today’sefforts aim to accommodate on a single chip multipletransceivers operating in various frequency bands formultiple wireless standards (e.g., Wi-Fi, Bluetooth, GPS,etc.) [2] and [3]. Earlier RF and analog designers had somefreedom in the choice of their device and circuit topologiessince the silicon chip area of single-transceiver systemswas dominated only by the digital baseband processor. Butin today’s designs, RF and analog sections need to bedesigned with much care regarding their area consumption.For example, on-chip spiral inductors were utilized inabundance in older systems, but they are now used onlyscarcely.In the communication system, Low noise amplifier is the

Linearity

SupplyVoltage Gain

Noise Power

Frequency

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 26

second element after antenna which is used to raise thestrength of the weak information signal noise suppression.So, noise figure (NF) is the key issue of concern in thisdesign. Matching of each block of the receiver is also animportant issue in order to provide maximum power transferat a particular frequency the matching is required.Furthermore, input and output matching to the source andload can maximize the gain. Input and output impedancematching is characterized by the input and output returnloss. Since, it can affect the performance of the device. Thegain should be large enough and the same time noiseshould be as less as possible. However, the gain of LNAshould not be too high otherwise in the following stages,mixer is saturated. The LNA should present specificimpedance at the input, e.g. 50 Ω to interface with thefilter or antenna.

III. NOISE OPTIMIZATION METHODSIn low noise amplifier design, determination of theminimum noise figure is a common and well-understoodprocedure. Typically, a small-signal model of the amplifieris assumed, an expression for F is formed anddifferentiation leads to the unique conditions for optimizednoise performance [3]. In the noise optimizationtechniques we seek the conditions that guaranteeoptimized noise performance for a specified fixed designparameter, such as gain or power consumption, under thecondition of perfect input matching. Now, we fix thenecessary design criteria and determine the appropriatesmall-signal model through the optimization procedure.Because the architecture permits selection of QL and LS

independently, so we can optimize the noise performance thatcoincides with the input match. There are two approachesfor the optimization of noise figure. The first assumes afixed transconductance, Gm, for the amplifier. The secondassumes fixed power consumption. We know the equation ofnoise figure is [4]= 1 + + + (1)

To illustrate these approaches, the expression for F in“(1)”, can be recast to make its dependance on powerdissipation (PD). From “(2)”, it is clear that condition forconstatnt Gm is equivalent to the condition of constatnωTG = g Q = ( ) = =

(2)To maintain a fixed ωT, we need to fix the value of ρ.Hence we will formulate F in terms of PD and ρ to facilitateboth optimizations. The equation of F in terms of PD and ρis given below= 1 + ( , ) (3)

In this equation the gate resistance and inductor losses to thenoise factor have been neglected. In the above “(3)”, ( , )is the ratio of two sixth-order polynomials of ρ given by( , ) = ( ) ( ) ( )( ) (4)

With, ( ) = (1 + ) + (1 + ) 1 +( ) = 2| | 5 (1 + ) 1 + 2

( ) = 5 1 + 2 ( )Because F is a function of two variables, one can definecontours of constant noise figure in and PD. “(3)” suggeststhat optimization of proceeds by minimizing with respect toone of its arguments, keeping the other one fixed.To fix the value of the transconductance, Gm, we need onlyassign a constant value to ρ. We know,= = = = ρ

(5)

The appropriate value for Gm is easily determined bysubstituting “(5)” in to the expression for as found in “(2)”.The value of Gm relates to ρ is= ( ) (6)

Once ρ is determined, we can minimize the noise factor bytaking( , )( ) = 0 (7)

Which, after some algebraic manipulations result in

, , = ( )( ) = 1 + 1 + 5(8)

The expression gives the power dissipation which yields thebest noise performance for a given Gm under theassumption of matched input impedance. The value of QL is= ( ) (9)

By comparing “(8)” to”(9)”, the optimum occurs when= , , = 1 + ≥ 1.87 (10)

Hence the best noise performance for a giventransconductance is achieved at some specific input. The of1.87 is only valid for the long channel devices. For shortchannel lengths, where α < 1, we can expect the optimum QLto be somewhat larger. By substituting”(10)”in to “(1)”, wecan determine that the minimum noise factor (neglectinginductor and gate losses) is

, = 1 + | | + 1 + ≥ 1 +1.33(11)

The value of 1.33 is only valid for long channel devices; itmay be three to four times larger in the presence of highelectric fields.An alternate method of optimization fixes the powerdissipation and adjusts ρ to find the minimum noise factor.If we assume that α < < 1, then P (ρ, PD) can be simplified to:

(ρ, P ) = 1 + 5 + 2| | 5 ρ + 5(12)

This expression is minimized for a fixed PD when( , )( ) = 0 (13)

The solution of this equation under the assumption that α≪ 1 is :

, = | | 1 + 1 + | | 1 + (14)

By comparing “(14)” t0 “(9)”, it is that this value for ρ isequivalent to an optimum QL of

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

27 NITTTR, Chandigarh EDIT-2015

, , = | | 1 + 1 + | | 1 + = 3.9 (15)

So it is clear that the optimum QL for fixed powerdissipation is larger than the optimum QL for a fixed Gm.From these equations, = 1 + 2.4 ≥ 1 + 1.62 (16)

Where the value of 1.62 is valid only in the long channel limit;the value will be somewhat larger for short- channel devicesin velocity saturation.

IV. TEST BENCH FOR SINGLE ENDED LNA ANDSIMULATION RESULTS

Transducer Power Gain (GT)It is defined as the ratio of the power delivered to the load andthe power available from the source.= | || | | | | || | (17)

Operating Power Gain (GP)It is defined as the ratio of the power delivered to the load ofthe network and the power input to the network.= | | | | (18)

Available Power Gain (GA)It is defined as the ratio of the power available from thenetwork and the power available from the source.= | | | | (19)

Because the power available from the source is greaterthan the power input to the LNA network GP > GT. Thecloser the two gains are, the better the input matching is.Similarly, because the power available from the LNAnetwork is greater than the power delivered to the load, GA

> GT. The closer the two gains are, the better the outputmatching is.The test bench for single ended LNA is shown in Fig. 3 andthe schematic for the same is shown in Fig. 4.

Fig 3 Test bench for Single Ended LNA

Fig 4 Schematic for Single Ended LNA In CADENCE VIRTUOSO

Fig 5 NF plot for single ended LNA

Fig 6 NFmin Plot for single ended LNA

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 28

Fig 7 GT, GP, GA plot for

Fig 8 VSWR PLOT for single ended LNA

V. CONCLUSIONThe single ended LNA is simulated in CADENCEVIRTUOSO environment and after certain iterations thevalue of noise figure is found to be 3 dB as shown in Fig 5and using the noise optimization technique the minimumnoise figure is found to be 2.5 dB as shown in Fig 6.Thegain plots are shown in Fig 7 and in Fig 8 the VSWR plotis shown.

References[1] Behzad Razavi, RF MICROELECTRONICS, 2nd ed., Prentice

Hall Publications,[2] T. Yamawaki et al., “A 2.7-V GSM RF Transceiver IC,” IEEE

J. Solid-State Circuits, vol. 32, pp. 2089–2096, Dec. 1997.[3] Derek K. Shaeffer and Thomas H. Lee, “A 1.5V, 1.5 GHz

CMOS Low Noise Amplifier”, IEEE J. Solid-State circuits,Vol. 32, pp. 745-759, May 1997.

[4] Trung-Kein Nguyen, Chung-Hwan Kim, Gook-JuIhm, Moon-Su Yang and Sang-Gug Lee, “CMOS Low-Noise AmplifierDesign Optimization Techniques”, IEEE Transactions OnMicrowave Theory And Techniques,Vol.52,No.5,pp.1433-1441,May 2004

[5] M. Sumanthi and S. Malarvizhi, “Performance Comparison ofRF CMOS Low Noise Amplifiers in 0.18 µm technologyscale”, International Journal of VLSI design & CommunicationSystems ,Vol.2, No.2, pp.June 2011.

[6] Tajinder Manku, “Microwave CMOS – Devices and Circuits”,IEEE Conference in Custom Integrated Circuits, pp. 59-66,1998

[7] Jeonghoon Lee, Youngsik Kim, “A 1.8 Fully DifferentialCMOS Low Noise Amplifier with a special care for MixerInput Stage”, IEEE SIRF, pp 178 – 181, 2006

[8] Hafez Foud, Khaled Sharaf, Essael-Diwany and Hadia El-Hennawy, “An RF CMOS modified Cascode LNA withInductive Source Degeneration”, In Proceedings of nineteenthNational Radio Science Conference, pp. 450-457, March 2002.

[9] W.R.Liou, C.A. Tsai, M.L. Yeh and G.E. Jan, “A 5.2 GHzlow-voltage Low-Noise amplifier with 0.35µm CMOStechnology”, International Journal Of Electronics, vol.91, No.9, pp. 551-561, September, 2004.

[9] Pranjal Rastogi, J. Karthik and Rajnish Sharma, “Design of anRF CMOS LNA using 0.25 micron technology”, VDAT.

[10] Thomas H. Lee and S. Simon Wong, “CMOS RF IntegratedCircuits at 5GHz and Beyond”, In Proceedings of IEEE,Vol.88, No.10, October 2000