Operating Systems{week 12b}

Rensselaer Polytechnic InstituteCSCI-4210 – Operating SystemsDavid Goldschmidt, Ph.D.

Hierarchical storage architecture

very small

very large

very fast

very slow

volatile

non-volatile

Main memory (i)

Locations in memoryare identified bymemory addresses When compiled, programs

consist of relocatable code Other compiled modules

also consist ofrelocatable code

symbolic addresses

in source code

relative addresses

in object code

Main memory (ii)

At load time, anyadditional librariesalso consist ofrelocatable code

physical addresses

generated by loader

Main memory (iii)

At run time, memoryaddresses of all objectfiles are mapped to asingle memory spacein physical memory

Contiguous memory allocation A pair of base and limit

registers define thelogical address space Also known as

relocation registers

Dynamic partitioning Variable-length or dynamic partitions:

When a new process enters the system, the process is allocated to a single contiguous block

The operating system maintains a list of allocated partitions and free partitions

OSProcess

5

Process 8

Process 2

OSProcess

5

Process 2

OSProcess

5

Process 2

Process 9

OSProcess

5Process 9

Process 2

Process 1

Placement algorithms

How can we place new process Pi in memory? First-fit algorithm: allocate the first free block

that’s large enough to accommodate Pi Best-fit algorithm: allocate the

smallest free block that’s largeenough to accommodate Pi

Next-fit algorithm: allocate thenext free block, searching from last allocated block

Worst-fit algorithm: allocate the largest free blockthat’s large enough to accommodate Pi

Fragmentation

Memory is wasted due to fragmentation,which can cause performance issues Internal fragmentation is wasted

memorywithin a partition or process memory

External fragmentation can reducethe number of runnable processes▪ Total memory space exists to satisfy

a memory request, but memory isnot contiguous

OSProcess

5Process

8

Process 2

Process 3Process

6

Process 12

Process 7Process 9

Noncontiguous allocation (i) A noncontiguous memory allocation

scheme avoids the external fragmentation problem Slice up physical memory into

fixed-sized blocks called frames ▪ Sizes typically range from 29 to 214

Slice up logical memory intofixed-sized blocks called pages

Allocate pages into frames▪ Note that frame size equals page size

Noncontiguous allocation (ii) When a process of size n pages is

ready to run, operating system finds n free frames

The OS keepstrack of pagesvia a page table

main memory

process Pi

== in use== free

Paging via a page table (i)

Page tables map logical memoryaddresses to physical memoryaddresses

Paging via a page table (ii) Example process Pi

needs 16MB oflogical memory Page size is 4MB Logical memory is

mapped to a 32MBphysical memory

Frame size is 4MB

binary 0 ==> 000000 4 ==> 000100 8 ==> 00100012 ==> 00110016 ==> 01000020 ==> 01010024 ==> 01100028 ==> 011100

Allocating a new process

Address translation (i)

Every logical address issliced into two distinctcomponents: Page number (p): used as an index into

thepage table to obtain the base physical memory address

Page offset (d): combined with the base address to identify the physical memory address

page numberpage offsetp d

Address translation (ii)

Covers a logical addressspace of size 2m withpage size 2n

page numberpage offsetp d

(m – n)

(n)

Address translation (iii)

Address translation (iv)

1

2

The page table is in main memory Every memory access request actually

requires two memory accesses:

Translation look-aside buffer Use page table

caching at thehardware levelto speed addresstranslation

Hardware-leveltranslation look-aside buffer(TLB)

Effective memory access time Given:

Memory access time is 100 nanoseconds TLB access time is 20 nanoseconds TLB hit ratio is 80%

The effective memory-access time (EMAT) is 0.80 x 120 ns + 0.20 x 220 ns = 140 ns What is the effective memory-access time

given a hit ratio of 99%? 50%?

Multilevel page tables

For large page tables, usemultiple page table levels Slice up the logical address

into multiple page indicators

Swapping

Processes in the ready queue have memory images waiting on disk Processes are

swapped in andout of memory

Can suffer from slow data transfer times