Opb Tutorial

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February 8, 2002 www.xilinx.com 11-800-255-7778

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Tutorial

Designing Cust om O PB Slav ePeripherals for MicroBlaz e

SummaryThis document offers recommended guidelines and practices for RTL designers to create

custom OPB slave peripherals for MicroBlaze embedded systems. An introduction to On-

chip Perip heral Bus (OPB) signals, basic transactions and tips for RTL coding are d iscussed

here.

OverviewIn an embedd ed system design, the peripherals (for examp le, timers, DMA, interrupt

controller, custom applications, etc.) must be connected to the microprocessor using the

data and address buses. The complexity of system-on-chip (SOC) devices makes

stand ardizing th e connection of different macro cells one of the top p riorities in defining an

embed ded system. Xilinx MicroBlaze hav e imp lemented IBM's CoreConnect architecture.

Ultimately, designing a complex chip based on existing intellectual property and design

reuse method ology could become a straightforward task.

On-chip Per ipheral Bus (OPB) version 2.1 of CoreConnect architecture is d esigned for easyconnection of on-chip peripheral devices. Any custom peripheral that connects to the OPB

bus m ust meet the pr inciples of the OPB protocol and the d esign m ust m eet the

requirements of Platform Generator an d CoreGen flow to take ad vantage of the simple

automated flow that generates the system-level architecture as well as other template

scripts supported by Xilinx.

FeaturesPlatform Generator supports the following features of on-chip peripherals and is a subset

of OPB v2.1 features:

Fully synchronous single clock edge

32-bit add ress bus, 32-bit data bus

Single-cycle transfer of data between OPB master and OPB slave

Supp orts master byte enables

Su p p o r t s s la v e t im e ou t s u p p r es s

Su p p o r t s s la v e r et r y

No tristate drivers required

Note that the d ynamic bus sizing feature is not sup ported in OPB v2.1.

Figure 1 is a block diagram of a MicroBlaze-based embedded system.
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2 www.xilinx.com February 8, 20021-800-255-7778

Tutorial: Designing Custom OPB Slave Peripherals for MicroBlazeR

An OPB periph eral of MicroBlaze can be p ortable to Virtex-II ProTM devices. Figure 2 is a

block diagram of a Virtex-II Pro-based embedded system.

Physical ImplementationFigure 3 shows a simplified physical implementation of the OPB. This bus architecture

allows for the add ition of peripherals to the system w ithout changing the existing I/ O on

either the OPB arbiter or other existing peripherals.

Figure 1: MicroBlaze-Based Embedded System

Figure 2: Virtex-II Pro-Based Embedded System

OPBArbiter

OPB Slave(Ex: UART)

OPB Slave(Ex: Interrupt

Controller)

OPB Slave(Ex: GPIO)

OPB Master(Ex: DMA)

MicroBlazeas

OPB Master

OPBBus

xip2043

OPBArbiter

PLBArbiter

PPC 405Processor

Block

OPBPeripheral

OPBPeripheral

OPBPeripheral

OPBPeripheral

PLB-to-OPBBridge

OPB-to-PLBBridge

PLBPeripheral

PLBPeripheral

D_Side PLB I/F

I_Side PLB I/F

PLB OPB xip2044
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Interface SignalsR

The mod ule opb_v20 in th e d iagram imp lements the OR gates defined by th e OPB v2.1

specification. Based on th e Micropro cessor H ard wa re Specification file (MHS) prov ided by

the u ser, Platform Generator coun ts the n um ber of devices (both masters and slaves)

attached to the OPB, instantiates opb_v20, and automatically connects the address bus,

da ta buses, control and arbitrat ion signals. The Platform Gen erator flow allows the u ser to

focus on d esigning the p eripherals without having to worry abou t the system-level

connections.

Note that all masters and slaves in the system mu st drive data bu ses to zero wh en they are

inactive, and this has to be done internally within m asters and slaves.

OPB sup ports m ultiple master devices as shown in the d iagram above. Therefore, an

arbiter is required to arb itrate the bu s own erships between masters. If there is only oneOPB master in the system, the OPB arbiter can still be included in the system, since the

arbiter also asserts the OPB time-out signal if a slave respon se is not d etected within 16

clock cycles.

Interface SignalsThe interface signals are usu ally d efined in the early design stages, with some ad justm ents

made in the later stages. This section lists the signals required for the OPB slave and

Figure 3: Physical Implementation of OPB in MicroBlaze System

OPBMaster

Device 1

m1m_dbus

m1m_requestmi_opb_mgrant

m1m_abus

opb_dbus

OPBMaster

Device 2

OPBArbiter

m2m_abus

m2m_request

opb_dbus

m2m_dbus

m2opb_mgrant

opb_v20

OPBSlave

Device 1

OPBSlave

Device 2

AND gateor

FDRE

opb_abus

opb_dbus

s1s_dbuss2s_dbus

AND gateor

FDRE

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includes op tional signals for reference. Figure 4 shows the OPBSlave Interface and Table 1

lists and d escribes the Global Signals.

Figure 4: OPB Slave Interface

Table 1: Global Signals

Signal

NameDirection Width Description

O PB_Clk In p u t 1 A ll s ig na ls o n th e O PB ar e a ctiv e h ig h an d a re e it he r

direct output of edge-triggered latches which are

clocked by the OPB_Clk or are derived from the

output of a register using several levels of

combinatorial logic. All input signals should be

captured in the OPB masters or OPB slaves on the

rising ed ge of the OPB_Clk.

O PB_Rst In p u t 1 Th e a ctiv e h ig h r es et v ect or is a sy n ch ro no u s t o th e

OPB_Clk. The sa me reset signal also goes to

MicroBlaze core reset.

OPB

Slave

_errAck

_retry

_DBus

_xferAck

_toutSup

OPB_RNW

OPB_seqAddr

OPB_ABus

OBP_select

OPB_BE

OPB_DBus

OPB

Bus

Logic

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Interface SignalsR

Table 2 lists an d d escribes the OPB Interface Signals.

Table 2: OPB Interface Signals

Signal Name Direction Width Description

O PB_A Bu s In p u t [0:31] O PB_A Bu s is t h e a d d r es s b u s d r iv en b y t he O PB

bus and received by all slaves. The address on this

bus is valid only wh en OPB_select is asserted.

O PB_BE In p u t [ 0:3 ] O PB_BE is t h e b yt e-e na ble d r iv en b y t h e O PB b u s .

This signal indicates the bytes to be transferred

within the data path. See the section, Read Data

Steering and Write Data Mirroring for

information on m app ing data byte enables to the

data paths.

O PB_D Bu s In p u t [0:31] O PB_D Bu s i s t h e w r it e d a ta b u s d r iv en b y t h e O PB

bus and received by all slaves. O PB_DBus rema ins

valid until the master receives transfer

acknowledgement for w rite operation.

O PB_RN W In pu t 1 O PB_RN W (rea d n ot w rit e) sig na l in d ica tes t he

direction of dat a tran sfer. The signa l will be validany time OPB_select is asserted .

1 Master performs read operation on slave

0 Master performs write operation on slave

O PB_sele ct In p u t 1 O PB_s ele ct is d r iv en b y t he O PB b u s t o in d ica te

wh en OPB transfer is in progress and to validate

th e follow ing sign als: OPB_ABus, OPB_BE,

OPB_RNW and OPB_seqAddr. OPB_select will

continue to be d riven un til the master receives

transfer acknowledge or retry.

Deasserting OPB_select b efore receiving transfer

acknowledge constitutes a master abort.

O PB_seq Ad d r In p u t 1 O PB seq u en tia l a d d re ss . Th e sig n al in d ica te s t ha t

the tran sfer being perform ed w ill be followed by a

transfer to the next sequential add ress in th e same

direction. When OPB_seqAddr is asserted, the

slave device can arrange a reservation buffer or

lock the secondary buses to improve d ata transfer

performance, or the slave can ignore

OPB_seqAddr. However, OPB_seqAddr does not

indicate a burst transaction.

< Sl n> _D Bu s O u t p u t [0:31] < Sln > _D Bu s is t h e r ea d d a t a b u s d r iv e n b y t h e

target slave.Th e slave device mu st drive valid data

on _Dbus p rior to the end of the

_xferAck assertion cycle.

indicates the name of the p eripheral.


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< Sl n> _xfe r Ac k O u t p u t 1 O P B t r an s fe r a ck n o w le d g e. Th e s ig n a l i s a ss er t ed

by the addressed slave to indicate the completion

of a data transfer between the OPB master and

slave. It is asserted for only one cycle per data

transfer. In the case of write oper ations, this mean s

that the slave has accepted the data, wh ichpresently appears on the d ata bus, or will do so at

the end of this cycle. In the case of read op erations,

this means that the slave has placed the d ata to be

transferred to the O PB master on th e data bu s or

will drive the d ata on the da ta bus pr ior to the end

of this cycle.

_xferAck must be asserted by the slave

dev ice within 16 cycles of OPB_select to preven t a

timeou t, unless _ToutSup is asserted.

_xferAck must not be asserted if _retry

is asserted.

_xferAck also qualifies _errAck.


< Sln >_r et ry O u tp u t 1 O PB b u s cy cle r et ry. Th is sig n al is a sse rt ed b y a n

OPB slave to indicate that it is unable to perform

the requested transfer at this time. _retry

remains asserted u ntil the slave becomes

deselected a s a result of OPB_select reassertion.

_retry implies the request to master to

terminate the transfer.

The primary use of _retry enables slave

devices to break possible arbitration deadlock.


Table 2: OPB Interface Signals (Continued)



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Interface SignalsR

Table 3 lists and describes the optional Interrupt Signals.

Xilinx pro vides scalable Interru pt Controller, which is includ ed in MicroBlaze

development kits, to support different styles of interrupts: level sensitive, edge sensitive,

active high, or active low. Custom OPB peripheral applications may have differentinterrupt styles and/ or mu ltiple interrupt signals. Table 4 lists and describes the optional

App lication Signals.

< Sln >_t ou t Su p O u t p u t 1 Sla ve t im e -o u t su p p r es s. Th e sig n al is a sse rt ed b y

an OPB slave to ind icate that the bus opera tion will

be delayed for an extended time. This signal must

be asserted with in 16 clock cycles from the

assertion of OPB_select to prevent a bus timeout.

_Tout Su p w ill be used b y the OPB Arbiter to

disable the timeout counter and su pp ress the

assertion of OPB_timeou t. _ToutSup m ust

remain asserted u ntil the slave can complete the

requested operation. Note: If the master deasserts

OPB_select prior t o the slave asserting

_xferAck or _retry, thereby aborting

the transfer request, the Sln_toutSup signal may

remain asserted for one additional clock cycle.


< Sln >_e rr Ack O u tp u t 1 O PB t ra n sfe r e rro r a ck n ow le d g e. Th e sig n al is

asserted by a slave d evice to indicate that the slaveencountered an error in performing the requested

transfer. _errAck may be asserted

immediately upon a slave device's decode of its

ad d ress du ring a t ransfer cycle (OPB_select

asserted) or any time thereafter. It must be valid

wh en _xferAck is asserted. Slaves mu st

drive their _errAck signal only when

selected; otherwise, the slave must keep its

_errAck signal deasserted.


Note: All inactive OPB slave devices should drive buses to zero.

Table 3: Interrupt Signals (Optional)


Example:

Interrupt

O u tp u t D efin ed

by User

An OPB slave device can implement one or

mu ltiple interrupt signals, depend ing on

the system requ irements.

Table 4: Application Signals (Optional)


D efin ed b y U se r D efin ed

by User

Defined

by User

Defined by User

Table 2: OPB Interface Signals (Continued)

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Each app lication ha s ap plication-specific signals, inclu ding RX and TX in UART designs

and Sda (Serial Data) an d Scl (Serial Clock) in IIC d esigns.

In the mod ule level of HDL design, ports should be d efined either as inp ut or ou tpu t.

Thus, users should expand a bidirectional (inout) port to 3 separate ports: 2 outp uts and 1

input. The 2 outpu ts will be the ou tpu t p ort and the tristate (enable) port of the inout. The

input w ill be the inp ut p ort to the inout. The nam es may correspond to the convention

_T, _O, and _I, where can be your bidirectional

signal n ame; for examp le, GPIO_T, GPIO_O and GPIO_I.

Generics (Optional)It is recommen ded that generics be used, rather th an h ard-coded values, to make the

design reusable and retargetable. For examp le, generics can be u sed in the bau d rate and

data bit for the UART, the time interval for the watchdog timer, etc. Therefore, when the

specification of a peripheral has to be u pd ated, the user can easily mod ify the generics

without changing th e source code.

Notice that Platform Generator has keyw ords tow ards attributes n ames. Platform

Generator does automatic expansion on certain reserved attributes, such as

C_OPB_DWIDTH and C_OPB_AWIDTH. Therefore, users will hav e to refer to the

Platform Generator reference guide for the list of reserved attribute names. Table 5 listsand describes the op tional Generic Nam es.

Table 5: Generics (Optional)

Generic Name Type Width Description

C _BA SEA D DR s td _ lo g ic_v e ct or [0 :3 1] The b a se a d d r e ss o f t h is m e m o r y-

map ped slave d evice. When a

master initiates an operation by

asserting OP B_select, the ad d ress

decode logic may reference this

value and compare with OPB_ABus

to determine w hether this slave has

been targeted by the master.

C_BASEADDR is a keyword

attribute for Platform Generator.

C _H I GH A D DR s td _ lo g ic_v e ct or [0:31] The h i gh a d d r e ss o f t h is m e m o ry -

mapped slave device. Together with

the base ad dress, the total memory

space is defined.

C_HIGHADDR is a keyword

attribute for Platform Generator.

C_OPB_DWIDTH in teger - OPB System d ata bu s w id th .

MicroBlaze employs 32 2-bit OPB

architecture, so this value should be

fixed to 32.

C_OPB_AWIDTH in teger - OPB System ad dress bu s w id th .

MicroBlaze employes 32-bit OPB

architecture, so this value should be

fixed to 32.

Others

(Defined by User)

- - -


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Generic Block DiagramR

Generic Block DiagramAn OPB slave design example consists of the following components:

A d d r e ss d e co d i n g l og ic

OPB slave interface logic

Application-specific logic

Figure 5 is a block diagram example for an OPB Slave.

Address Decoding Logic

Each OPB slave device should have its own address decoding logic. When OPB_select is

asserted an d OPB_ABus is valid , all OPB slave devices will d ecode the com ing add ress an d

determine w hether to respond or to ignore. If OPB slave devices are not targeted by the

master which has been granted th e ownership of the bus, the slaves must ou tpu t all zeros

for all OPB-related interface signals. The u ser will wan t to m ake su re there is no o verlap in

memory-mapped space allocation. Otherwise, multiple OPB slave devices may try to

respond to the same transaction, leading to system malfunctions.

Since add ress decod ing logic sometimes is a critical p ath for tim ing, the MicroBlaze

development kit provides a samp le for p arameterizable peripheral add ress decoding logic

written in VHDL. The file is named pselect.vhd. The file pselect.vhd is a general-purposedecod ing logic targeting Xilinx FPGA fam ilies for best area and timing op timization. This

module can also be reused in bus systems other than the OPB system. If this file is not

available in the d evelopm ent kit, users can always design a simple comp arator to

determine address.

Figure 5: A Block Diagram Example for an OPB Slave

OPB_ABus

OPB_select

Addr match(Peripheral select)

OPB_DBus

OPB_BE

Application-

specificlogic

REG

FDRE

REG

_DBus

_xferAck

Applications

Read data

Address decoding logic(EX: pslect.vhd)

OPB SlaveI/F logicREG

OPBBus

QDR xfer_Ack

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Table 6 shows the generics and I/ O interface of pselect.vhd. Note that pselect utilizes

pu rely combinatorial logic and the u ser must an alyze the timing arch throu gh p select and

register the output signal PS prior to use, if necessary.

Table 7 shows the I/ O signal names of the interface of pselect.vhd.

OPB Slave Interface Logic

Once the slave has d ecoded its address and determined to respond to the transaction, this

OPB slave int erface logic hand les the ha nd shake, p rotocol, etc. See Interface Signals andthe Timing Diagram for further details.

Application-Specific Logic

For each application, application-specific logic must be defined by the user.

Table 6: Generics of pselect.vhd

Generic

NameType Width Description

C_AB Integer - N um ber of the m ost sign ifican t bit on th eadd ress bus to be d ecoded . If C_ABgets larger

value, more bits must be comp ared with inpu t

add ress. In this case, less mem ory-mapped

space is defined for this slave peripheral.

C_AW Integer - Wid th of th e in p u t ad d ress bu s. In

MicroBlazes curre nt MDT flow, C_AW

should have a fixed value of 32.

C _BA R s td _lo gic_v ect or 32 Ba se a d d r ess o f t h is s la ve p e rip h e ra l. W h en

the C_AB most significant add ress bits match

the C_AB most significant C_BAR bits, PS

(periph eral select) is asserted.

Table 7: I/O Interface of psele ct.vhd


A In p ut [0:C_AW-1] Ad d ress in p ut. In t he O PB su bsy st em ,

this should be connected to OPB_ABus,

or a registered inp ut of OPB_ABus,

depending on timing requirement.

Avalid In p u t 1 Ad dress valid . In the OPB su bsystem ,

this shou ld be connected to OPB_select,

or a registered inp ut of OPB_select,depending on the timing requirement.

PS Ou tp u t 1 Perip h eral select. When the C_AB m ost

significant address bits match the C_AB

most significant C_BAR bits, PS is

asserted. As PSis not a registered ou tpu t

from pselect.vhd, the user must register

this signal before using it.


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Timing DiagramR

Timing DiagramFigure 6 shows basic OPB read transactions and Figure 7 shows basic OPB write

transactions. The OPB ma ster asserts OPB_select an d pu ts valid O PB_ABu s, OPB_BE and

OPB_RNW on th e buses. The slave comp letes the transfer by asserting OPB_xferAck,

wh ich causes the master to latch d ata from the d ata bus on read transfers, and d eassert

select.

Note th at the cycles for the OPBm aster dev ice asserting its requ est to the OPBa rbiter is not

show n in these d iagrams. Also refer to O PB 2.1 Specification from IBM for oth er p rotocoldefinition.

Figure 6: A Basic OPB Read Transaction (Example)
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Read Data Steering and Write Data Mirroring (MicroBlaze Only)In the MicroBlaze processor, an OPB master device performs read data steering and write

data mirroring. Users should be aw are of the data byte m app ing mechanism MicroBlaze

ap plies in OPB Read (load instru ctions) and OPB Write (store instru ctions) opera tions, in

order to design the slave peripherals that meet the expectations of MicroBlaze as the

master peripheral in the system.

MicroBlazes Read Data Steering (Load to register rD)

Table 8 shows how MicroBlaze performs read data steering, i.e., how the internal register

rD will be loaded w ith the data bytes ap pearing on the 32-bit read data bu s.

Figure 7: A Basic OPB Write Transaction (Example)

Table 8: Mi croBlazes Read Data Steering (Load to Registe r rD )

Register rD Data

OPB_ABus

[30:31]

OPB_BE

[0:3]

Transfer

SizerD[0:7] rD[8:15] rD[16:23] rD[24:31]

11 0001 Byte Byte 3

10 0010 Byte Byte 2

01 0100 Byte Byte 1

00 1000 Byte Byte 0

10 0011 H alfw ord Byte 2 Byte 3


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Bus AlignmentR

Users must pay attention to this table and p lace data bytes properly to the read d ata bus.

MicroBlazes Write Data Mirroring (Store from register rD)

Write data is mirrored to all byte lanes by MicroBlaze, giving the slave devices flexibility to

attach to the write bus. For example, a device with internal ping-pong buffers can benefit

from the w rite data mirror without extra mu xes and a byte d evice can be attached to any

byte lane. However, users cannot assume that all OPB master d evices perform write da ta

mirroring. Table 9 show s how MicroBlaze does w rite data m irroring. The field s in Bold ar e

defined by th e OPB spec an d PLB2OPB spec, and the fields in Italic are the m irroring

feature MicroBlaze p rovides ad ditionally.a

Bus AlignmentPlatform Generator requires OPB data buses to be 32 bits wide. Therefore, any legacy

devices of bus w idth less than 32 bits mu st expand the bus w idth p roperly. There are

several ways to hand le this case, dep ending on the n ature of the d evices. If a d evice

contains m emory based design that requ ires some restrictions in the storage mod e, the

ap prop riate steering logic ma y be includ ed to take care of the d ata alignmen t. The user can

compare the behavior of the legacy design with Table 8 and Table 9 to design the steering

logic for M icroBlaze.

If the legacy design contains register-based devices and physical bus connection is not an

issue, the unused byte lanes in a 32-bit Read Dada bus can be tied to zero as Figure 8

shows. In this case, the ad dressing mod e can always align to w ord bou nd ary, i.e., the

perip heral alw ays ignores OP B_ABus[30:31]. For examp le, in a C progr am, simp ly useint (integer, 32bit) instead of char (char acter, 8bit) declarations. Doing this w ill align

the OPB_ABus to the word boundaries and the slave devices may drop OPB_ABus[30:31]

internally.

00 1100 H alfw ord Byte 0 Byte 1

00 1111 Word Byte 0 Byte 1 Byte 2 Byte 3

In the big endian notation, byte 0 is Read Data Bus [0:7], byte 1 is Read Data Bus [8:15], byte 2 is Read Data Bus [16:23], andbyte 3 is Read Data Bus [24:31].

Table 8: Mi croBlazes Read Data Steering (Load to Registe r rD )

Table 9: Mi croBlazes Write D ata Mirroring (Store f rom Reg is ter rD )

Write Data BusOPB_ABus

[30:31]

OPB_BE

[0:3]

Transfer

Size

OPB_DBus

[0:7]

OPB_DBus

[8:15]

OPB_DBus

[16:23]

OPB_DBus

[24:31]

11 0001 Byte rD[24:31] rD[24:31] rD[24:31] rD[24:31]

10 0010 Byte rD[24:31] rD[24:31] rD[24:31] rD[24:31]

01 0100 Byte rD[24:31] rD[24:31] rD[24:31] rD[24:31]

00 1000 Byte rD[24:31] rD[24:31] rD[24:31] rD[24:31]

10 0011 H alfw ord rD[16:23] rD[24:31] rD[16:23] rD[24:31]

00 1100 H alfw ord rD[16:23] rD[24:31] rD[16:23] rD[24:31]

00 1111 Word rD [0:7] rD [8:15] rD [16:23] rD [24:31]


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In conclusion, the various factors designers mu st consider in determining h ow the d ata

bus should align includ e the nature of the device, the read data steering and write data

mirroring mechanism (MicroBlaze only), and communicating well with firmware

designers to avoid mistakes.

General Coding GuidelinesSome general RTL coding gu idelines:

Register input signals and output signals to improve timing

Use Clock Enables instead of using different clock domains

Register OPB signal outpu ts from slave devices by using FDRE compon ents. Use

OPB_xferAck to reset th e register synchron ously

For any device smaller than 32bit, expand the data buses to 32-bit width, with

appropriate steering logic, or tie unused byte lanes to zeros, as the case requires

Figure 8: Expand a Byte Device to 32 Bits Wide

zeros

_Dbus[0:31]

00 00 00 AB

24 8

Bytedevicecore

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General Coding GuidelinesR

The next section uses MYGPIO as a design example, based on the topics discussed in the

preceding sections. MYGPIO is a simple peripheral consisting of three memory-mapped

registers for software access. Figure 9 shows the block diagram for MYGPIO.

entity MYGPIO is

generic (

C_OPB_AWIDTH : integer := 32;

C_OPB_DWIDTH : integer := 32;

C_BASEADDR : std_logic_vector(0 to 31) := X"FFFF_8000";

C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFF_80FF"

);

port (

-- Global signals

OPB_Clk : in std_logic;

OPB_Rst : in std_logic;

Interrupt : out std_logic;

-- OPB signals

OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);

OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);

OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);

OPB_RNW : in std_logic;

OPB_select : in std_logic;

OPB_seqAddr : in std_logic;

GPIO_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);

GPIO_errAck : out std_logic;

GPIO_retry : out std_logic;

GPIO_toutSup : out std_logic;

GPIO_xferAck : out std_logic;

-- GPIO signalsGPIO_IO_I : in std_logic_vector(0 to 7); --GPIO input

GPIO_IO_O : out std_logic_vector(0 to 7); --GPIO output

GPIO_IO_T : out std_logic_vector(0 to 7) --GPIO tri-state ouput

);

end entity MYGPIO;

Figur e 10 shows the entity declaration that describes the interface of the design to its

external environ men t. In the generic declaration, C_OPB_AWIDTH an d C_OPB_DWIDTH

Figure 9: Block Diagram for MYGPIO

Figure 10: Entity of MYGPIO

OPBI/F

Offset x00

GPIO/I

Offset x04GPIO/O

Offset x08GPIO/T

GPIO

MYGPIOOPB

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define the w idth for add ress bus and data bu ses. The parameterized coding style provides

more flexibility to target different bus standards for future expansion. In the MicroBlaze

system, since dynamic bus sizing is not supported and Platform Generator supports 32-bit

address and data buses, C_OPB_AWIDTH and C_OPB_DWIDTH should be 32.

C_BASEADDR and C_HIGHADDR define the m emory -map ped space for MYGPIO in the

embedd ed system defined by the user.

The port declaration uses:

Global signals: OPB_Clk and OPB_Rst

OPB signals: OPB_ABus, OPB_BE, OPB_RNW, OPB_select, OPB_seqAddr,

OPB_DBus, GPIO_DBus, GPIO_errAck, GPIO_retry, GPIO_toutSup, GPIO_xferAck

GPIO signals: GPIO_IO_I, GPIO_IO_O, and GPIO_IO_T

The wid th of GPIO_DBus (the read bu s outp u t from MYGPIO) is 32 bits wid e, even th oug h

MYGIPO ha s an 8-bit core. In th is examp le, only GPIO_DBus[24:31] is u sed, w hile

GPIO_DBus[0:23] is tied to zero. Platform Genera tor requ ires that a ll OPB ad dress an d

OPB read/ write d ata bu ses in the VHDL entity be to std _logic_vector (0 to 31).

Figure 11 is an example VHDL code utilizing all the topics discussed in the preceding

sections.

architecture RTL of MYGPIO is

-- Special function to calculate number of bits need to be decoded

-- based on C_BASEADDR and C_HIGHADDR.

-- If C_BASEADDR = X"FFFF_8000" and C_HIGHADDR = X"FFFF_80FF",

-- the function returns 24.

function Addr_Bits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1))

return integer is

variable addr_nor : std_logic_vector(0 to C_OPB_AWIDTH-1);

begin

addr_nor := x xor y;

for i in 0 to C_OPB_AWIDTH-1 loop

if addr_nor(i) = '1' then return i;

end if;

end loop;

return(C_OPB_AWIDTH);

end function Addr_Bits;

constant C_AB : integer

:= Addr_Bits(C_OPB_HIGHADDR, C_OPB_BASEADDR);

...

...

begin -- architecture RTL

-----------------------------------------------------------------

-- Handling the OPB bus interface

-----------------------------------------------------------------

-- OPB address decoding using pselect.vhd.-- The generic map C_BASEADDR is passed from entity,

-- C_AB is the return value from function Addr_Bits().

-- If C_AB gets smaller, the logic of pselect gets smaller.

--

-- OPB_ABus and OPB_select come from the ports.

-- gpio_CS will be registered prior to usage.

-- Use OPB_ABus_reg and OPB_select_reg if non-registered

-- signals dont meet timing.

pselect_I : pselect

generic map (

C_AB => C_AB,


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C_AW => OPB_ABus'length,

C_BAR => C_BASEADDR)

port map (

A => OPB_ABus,

AValid => OPB_select,

p s = > jta g_ UA RT_ CS );

-- First register gpio_CS generated by pselect

-- uart_CS_1_DFF is synchronously reseted by xfer_Ack

-- (or OPB_xferAck) when the current transaction has

-- been completed by the slave.

gpio_CS_1_DFF : FDR

port map (

Q => gpio_CS_1, -- [out std_logic]

C => OPB_Clk, -- [in std_logic]

D => gpio_CS, -- [in std_logic]

R => xfer_Ack); -- [in std_logic]

gpio_CS_2_DFF : process (OPB_Clk, OPB_Rst) is

begin

if OPB_Rst = '1' then

gpio_CS_2


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-- Register all the OPB input signals

-----------------------------------------------------------------

WRDBUS_FF_GENERATE: for i in 0 to 7 generate

WRDBUS_FF_I: FDR

port map (

Q => opb_DBus_Reg(i),

C => OPB_Clk,

D => OPB_DBus(24 to 31),

R => OPB_Rst

);

end generate WRDBUS_FF_GENERATE;

ABUS_FF_GENERA TE: for i in 0 to C_OPB_AWIDTH-1 generate

ABUS_FF_I: FDR

port map (

Q => opb_ABus_Reg(i),

C => OPB_Clk,

D => OPB_ABus(i),

R => OPB_Rst

);

end generate ABUS_FF_GENERATE;

RNW_FF_I: FDR

port map (

Q => opb_RNW_Reg,C => OPB_Clk,

D => OPB_RNW,

R => OPB_Rst

);

-----------------------------------------------------

-- Memory Mapped Registers Write Access for MYGPIO

-----------------------------------------------------

-- The C program chose to use an integer(32bit) pointer

-- to addresses aligned to word boundaries (0,4,8,c..)

-- even though MYGPIO has 8 bit only.

-- So bit 30:31 of OPB_ABus are dropped so that the Address

-- port of GPIO core is always aligned to word boundary.

---- Generate enable signals based on address and write cmd.

gpdata_out_we


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g pd ata _o ut < = '0' ;

elsif OPB_Clk'event and OPB_Clk = '1' then

if (gpdata_out_we = '1')

gpdata_out


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Introduction to OPB IPIF (Preliminary)In the above d esign practice for MYGPIO, a simple way to d esign OPB slaves with only

memory-mapp ed registers was discussed. In ad dition to registers, an OPB slave peripheral

may contain other basic compon ents that m ust be accessed and controlled by the high-

level firmware. These components can be FIFOs, DMA, software reset, interrupt support,

etc. When the RTL designers start to bu ild the entire embedd ed system, man y p rocedu res

in the design of these components are repetitive.

The OPB IPIF provided via CoreGen flow, is a module for attaching an intellectualproperty to the OPB, providing comm on comp onents OPB slaves (and also masters) may

require. IPIF stand s for Int ellectual Property Int erface. The OPB IPIF was conceived to

provide a comm on interface for third-party IP providers and customers wanting to

integrate their own cores into MicroBlaze systems, designed to reduce the repetitive

development effort needed to connect IP to the OPBbu s, and prom oting h igher quality of

consistency. The O PB IPIF basically ha s tw o fun ctions: (1) to facilitate attachm ent of

devices to the OPB in a standard way and (2) to provide services that are u seful to various

classes of IPs.

Figur e 13 show s an O PB d evice using the fu ll set of IPIF features. This device has bo th

Master and Slave attachments, Address Decode, Interrupt Control, Read Packet FIFOs,

Write Packet FIFOs, DMA, an d Scatter Gather.

The IPIF is a par ametric soft IP core d esigned for Xilinx FPGAs, available throu gh CoreGen

flow. Therefore, it is very simp le to choose the m inimal set of requ ired fun ctions an d

appropriate master or slave attachment. In the MYGPIO example, because FIFOs and

DMAs are not u sed, CoreGen can generate the IPIF with n othing more th an OPB slave

access to the m emory-mapp ed registers. Figure 14 shows the minimal set of IPIF that fits

MYGPIOs requirements.

Figure 13: An OPB Device Using the Full set of IPIF Features

IPCand

"glue"

InterruptControl

Register I/F

Reset

SlaveAttachment

"SRAM" I/F

Addr_Decode

Write FIFO

Read FIFO

Master I/F

ScatterGather

DMA

MasterAttachment

OPB

ControlData Path

IPCore External

I/F

IPIF

Device

IP Interconnect

xip2053


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Design Practice Using OPB IPIF (Preliminary)R

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Design Practice Using OPB IPIF (Preliminary)Since OPB IPIF has handled the OPB protocol, the users have to learn only how to attach

their own IP core to the IP interconnect shown in the above d iagram.

Figur e 15 shows the same MYGPIO d esign but u sing OPB IPIFs simp le register interface.

Comparing to the p revious examp le, the logic required to d esign it has been redu cedbecause of instan tiating O PB IPIF.

architecture RTL2 of MYGPIO is

------------------------------------------------------------------

-- Calculate Number of bits in AddresS that need to decode

------------------------------------------------------------------

-- Special function to calculate number of bits need to be decoded

-- based on C_BASEADDR and C_HIGHADDR.

-- If C_BASEADDR = X"FFFF_8000" and C_HIGHADDR = X"FFFF_80FF",

-- the function returns C_AB=24.

function Addr_Bits (x, y : std_logic_vector(0 to C_OPB_AWIDTH-1))

return integer is

variable addr_nor : std_logic_vector(0 to C_OPB_AWIDTH-1);

begin

addr_nor := x xor y;

for i in 0 to C_OPB_AWIDTH-1 loop

if addr_nor(i) = '1' then return i;

end if;

end loop;

return(C_OPB_AWIDTH);

end function Addr_Bits;

constant C_AB : integer := Addr_Bits(C_HIGHADDR, C_BASEADDR);

Figure 14: An OPB Device Using Only the IPIF Features for Register Access

IPCand

"glue"

Register I/FSlaveAttachment

Addr_Decode

OPB

ControlData Path

IPCore External

I/F

IPIF

Device

IP Interconnect

xip2054
http://www.xilinx.com/http://www.xilinx.com/http://-/?-http://-/?-http://www.xilinx.com/


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-----------------------------------------------------------------

-- Component template from CoreGen

-----------------------------------------------------------------

-- The following component delaration can be generated by CoreGen

-- The generics contains full set of features provided by IPIF.

-- Users can turn on/off the features based on the applications.

-- Some generics will be over-written by the instantiation later

-- in the architecture section

--

-- The names of parameters and signals are self-document. Refer to

-- OPB IPIF Architecture Specification for detailes.

component ipif

generic (

C_DEV_BLK_ID : INTEGER := 0;

C_DEV_MIR_ENABLE : BOOLEAN := False;

C_DEV_BASEADDR : std_logic_vector := X"FFFF_8000";

C_OPB_ABUS_WIDTH : INTEGER := 32;

C_OPB_DBUS_WIDTH : INTEGER := 32;

C_OPB_BE_NUM : INTEGER := 4;

C_DEV_BURST_ENABLE : BOOLEAN := False;

C_D EV _M AX_ BU RS T_S IZ E : INT EG ER := 6 4;

C_RESET_PRESENT : BOOLEAN := False;

C_I NT ER RUP T_ PR ESE NT : BOO LE AN := T ru e;

C_INCLUDE_DEV_PENCODER : BOOLEAN := False;C_I P_ MA STE R_ PR ESE NT : BOO LE AN := F al se;

C_IP_REG_PRESENT : BOOLEAN := True;

C_IP_REG_NUM : INTEGER := 3;

C_IP_IRPT_NUM : INTEGER := 1;

C_IP_SRAM_PRESENT : BOOLEAN := False;

C_IP_SRAM_BASEADDR_OFFSET : std_logic_vector := X"00001000";

C_IP_SRAM_SIZE : INTEGER := 256;

C_WRFIFO_PRESENT : BOOLEAN := False;

C_WRFIFO_BASEADDR_OFFSET : std_logic_vector := X"00002100";

C_WRFIFO_REG_BASEADDR_OFFSET: std_logic_vector := X"00002000";

C_RDFIFO_PRESENT : BOOLEAN := False;

C_RDFIFO_BASEADDR_OFFSET : std_logic_vector := X"00002200";

C_RDFIFO_REG_BASEADDR_OFFSET: std_logic_vector := X"00002010";

C_DMA_PRESENT : BOOLEAN := False;

C_DMA_REG_BASEADDR_OFFSET : std_logic_vector := X"00002300";C_DMA_CHAN_NUM : INTEGER := 2;

C_DMA_CH1_TYPE : INTEGER := 2;

C_DMA_CH2_TYPE : INTEGER := 3;

C_DMA_ALLOW_BURST : BOOLEAN := False;

C_DMA_LENGTH_WIDTH : INTEGER := 11;

C_D MA _I NTR _C OA LES CE : BOO LE AN := F al se;

C_DMA_PACKET_WAIT_UNIT_NS : INTEGER := 1000000;

C_DMA_TXL_FIFO_IPCE : INTEGER := 8;

C_DMA_TXS_FIFO_IPCE : INTEGER := 9;

C_DMA_RXL_FIFO_IPCE : INTEGER := 7;

C_D MA _R XS_ FI FO _IP CE : INT EG ER := 1 5;

C_O PB _C LK_ PE RI OD_ PS : INT EG ER := 1 00 00;

C_IP_REG_BASEADDR_OFFSET : std_logic_vector := X"00000100";

C_DEV_ADDR_DECODE_WIDTH : INTEGER := 24;

C_IPIF_ABUS_WIDTH : INTEGER := 4;C_IPIF_DBUS_WIDTH : INTEGER := 32;

C_VIRTEX_II : Boolean := True;

C_INCLUDE_DEV_ISC : Boolean := False

);

port (

OPB_ABus :in std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1);

OPB_DBus :in std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1);

Sln_DBus :out std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1);

Mn_ABus :out std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1);

IP2Bus_Addr :in std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1);

Bus2IP_Addr :out std_logic_vector(0 to C_IPIF_ABUS_WIDTH - 1);

Bus2IP_Data :out std_logic_vector(0 to C_IPIF_DBUS_WIDTH - 1);


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Bus2IP_Reg_RdCE :out std_logic_vector(0 to C_IP_REG_NUM - 1);

Bus2IP_Reg_WrCE :out std_logic_vector(0 to C_IP_REG_NUM - 1);

Bus2IP_SRAM_CE :out std_logic;

IP2Bus_Data :in std_logic_vector(0 to C_IPIF_DBUS_WIDTH - 1);

IP2Bus_WrAck :in std_logic;

IP2Bus_RdAck :in std_logic;

IP2Bus_Retry :in std_logic;

IP2Bus_Error :in std_logic;

IP2Bus_ToutSup :in std_logic;

IP2DMA_RxLength_Empty : in std_logic;

IP2DMA_RxStatus_Empty : in std_logic;

IP2DMA_TxLength_Full : in std_logic;

IP2DMA_TxStatus_Empty : in std_logic;

IP2 IP _A ddr : in s td _lo gi c_ vec to r( 0 t o C_ IPI F_ AB US_ WI DT H - 1 );

IP2 RF IF O_D at a : in s td _lo gi c_ vec to r( 0 t o 31 );

IP2RFIFO_WrMark :in std_logic;

IP2RFIFO_WrRelease :in std_logic;

IP2RFIFO_WrReq :in std_logic;

IP2RFIFO_WrRestore :in std_logic;

IP2WFIFO_RdMark :in std_logic;

IP2WFIFO_RdRelease :in std_logic;

IP2WFIFO_RdReq :in std_logic;

IP2WFIFO_RdRestore :in std_logic;

IP2Bus_MstBE :in std_logic_vector(0 to C_OPB_BE_NUM - 1);

IP2Bus_MstWrReq :in std_logic;

IP2Bus_MstRdReq :in std_logic;IP2Bus_MstBurst :in std_logic;

IP2Bus_MstBusLock :in std_logic;

Bus2IP_MstWrAck :out std_logic;

Bus2IP_MstRdAck :out std_logic;

Bus2IP_MstRetry :out std_logic;

Bus2IP_MstError :out std_logic;

Bus2IP_MstTimeOut :out std_logic;

Bus2IP_MstLastAck :out std_logic;

Bus 2I P_ BE :ou t s td _l ogi c_ ve cto r( 0 to C_ OP B_B E_ NU M - 1 );

Bus 2I P_ WrR eq :ou t s td _l ogi c;

Bus 2I P_ RdR eq :ou t s td _l ogi c;

Bus 2I P_ Bur st :ou t s td _l ogi c;

Mn_request :out std_logic;

Mn_busLock :out std_logic;

Mn_select :out std_logic;Mn_RNW :out std_logic;

Mn_BE :out std_logic_vector(0 to C_OPB_BE_NUM - 1);

Mn_seqAddr :out std_logic;

OPB_MnGrant :in std_logic;

OPB_xferAck :in std_logic;

OPB_errAck :in std_logic;

OPB_retry :in std_logic;

OPB_timeout :in std_logic;

Freeze :in std_logic;

RFIFO2IP_AlmostFull :out std_logic;

RFIFO2IP_Full :out std_logic;

RFIFO2IP_Vacancy :out std_logic_vector(0 to 9 );

RFIFO2IP_WrAck :out std_logic;

OPB_select :in std_logic;

OPB_RNW :in std_logic;OPB_seqAddr :in std_logic;

OPB_BE :in std_logic_vector(0 to C_OPB_BE_NUM - 1);

Sln_xferAck :out std_logic;

Sln_errAck :out std_logic;

Sln_toutSup :out std_logic;

Sln_retry :out std_logic;

WFIFO2IP_AlmostEmpty:out std_logic;

WFIFO2IP_Data :out std_logic_vector(0 to 31 );

WFIFO2IP_Empty :out std_logic;

WFIFO2IP_Occupancy :out std_logic_vector(0 to 9 );

WFIFO2IP_RdAck :out std_logic;

Bus2IP_Clk :out std_logic;


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Bus2IP_DMA_Ack :out std_logic;

Bus2IP_Freeze :out std_logic;

Bus 2I P_ Res et :ou t s td _l ogi c;

IP2Bus_Clk :in std_logic;

IP2Bus_DMA_Req :in std_logic;

IP2Bus_IntrEvent :in std_logic_vector(0 to C_IP_IRPT_NUM - 1);

IP2 IN TC _Ir pt :ou t s td _l ogi c;

OPBClk :in std_logic;

Reset :in std_logic

);

end component;

...

...

...

begin -- architecture RTL2

---------------------------------------------------------------------------

-- Instantiate OPB_IPIF to handle OPB interface

---------------------------------------------------------------------------

--The following section overwrites default value of generics for

--MYGPIO example. Since MYGPIO only needs the "Register" feature,

--other IPIF features are set to "False"--*********************************************************

--* Because of readability in this document, the following*

--* instantiation lists only related signals, it is not a *

--* complete source code. *

--*********************************************************

u0_ipif: ipif

generic map (

...

...

C_D EV _B ASE AD DR = > C_ BAS EA DD R, - -p ass ed f rom e nt ity

C_OPB_ABUS_WIDTH => C_OPB_AWIDTH,--passed from entity

C_OPB_DBUS_WIDTH => C_OPB_DWIDTH,--passed from entity

C_DEV_ADDR_DECODE_WIDTH => C_AB, --cal. by function Addr_Bits

C_DEV_BURST_ENABLE => False, --set to false for MYGPIO

C_RESET_PRESENT => False, --set to false for MYGPIO

C_I NT ER RUP T_ PR ESE NT = > Fa lse , - -s et to f als e fo r MYG PI O

C_INCLUDE_DEV_PENCODER => False, --set to false for MYGPIO

C_I P_ MA STE R_ PR ESE NT = > Fa lse , - -s et to f als e fo r MYG PI O

C_IP_REG_PRESENT => True, --set to true for MYGPIO

C_IP_REG_NUM => 3, --X00/X04/X08 for MYGPIO

C_IP_REG_BASEADDR_OFFSET => X"00000000", --X00 for register offset

C_IP_SRAM_PRESENT => False, --set to false for MYGPIO

C_WRFIFO_PRESENT => False, --set to false for MYGPIO

C_RDFIFO_PRESENT => False, --set to false for MYGPIO

C_DMA_PRESENT => False, --set to false for MYGPIO

C_IPIF_ABUS_WIDTH => 4, --not usedC_IPIF_DBUS_WIDTH => 32, --expend 8bit GPIO to 32 to avoid confusion

C_INCLUDE_DEV_ISC => False,--set to false for MYGPIO

...

...

..

)

port map (

..

...

...

--Interface to OPB Bus


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Reset => OPB_Rst --I passed from entity

OPBClk => OPB_Clk, --I passed from entity

OPB_ABus => OPB_ABus, --I passed from entity

OPB_DBus => OPB_DBus, --I passed from entity

OPB_select => OPB_select, --I passed from entity

OPB_RNW => OPB_RNW, --I passed from entity

OPB_seqAddr => OPB_seqAddr, --I passed from entity

OPB_BE => OPB_BE, --I passed from entity

Sln_xferAck => GPIO_xferAck, --O passed to entity

Sln _e rr Ack = > GPIO _er rA ck , -- O pas se d to en tit y

Sln_toutSup => GPIO_toutSup, --O passed to entity

Sln_retry => GPIO_retry, --O passed to entity

Sln_DBus => GPIO_DBus, --O passed t o entity

...

...

--IP Interconnect Interface to MYGPIO registers

IP2Bus_Clk => IP2Bus_Clk, --O typically identical to OPB_CLK

Bus2IP_Reset => Bus2IP_Reset, --O OPB_Rst "ORed" with SW reset.

-- (SW reset is not implemented here)

Bus2IP_Addr => open, --O Not Connect

Bus 2I P_ Dat a = > Bus2 IP_ Da ta , -- O

Bus2IP_Reg_RdCE => Bus2IP_Reg_RdCE,--O

Bus2IP_Reg_WrCE => Bus2IP_Reg_WrCE,--O

IP2 Bu s_ Dat a = > IP2B us_ Da ta , -- I

IP2Bus_WrAck => IP2Bus_WrAck, --IIP2Bus_RdAck => IP2Bus_RdAck, --I

IP2Bus_Retry => IP2Bus_Retry, --I

IP2Bus_Error => IP2Bus_Error, --I

IP2Bus_ToutSup => IP2Bus_ToutSup, --I

Bus2IP_BE => Bus2IP_BE, --O

Bus2IP_WrReq => Bus2IP_WrReq, --O

Bus2IP_RdReq => Bus2IP_RdReq, --O

...

...

..

);

--Unused control signals tie to ground.IP2Bus_retry


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begin

if Bus2IP_Reset = '1' then

gpdata_out '0');

elsif Bus2IP_Clk'event and Bus2IP_Clk = '1' then

if ( Bus2IP_WrReq = '1' and Bus2IP_Reg_WrCE(1) = '1') then

gpdata_out


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------------------------------

--Since RdReq is 1-cycle pulse in this case,

--edge detection is not needed

RdAck_PROCESS:process (Bus2IP_Clk,Bus2IP_Reset )

begin

if (Bus2IP_Reset = '1') then

IP2Bus_RdAck_i


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Summary of OPB IPIF FeaturesThe above design practice provides an example using the simple register access feature of

OPB IPIF. The full outline of OPB IPIF features is sum mar ized below. Users can refer to the

OPB IPIF Architecture Specification for more d etails, including the fun ctional d escriptions,

design p arameters, interface signals and timing d iagrams.

Synchronous operation

Hardw are and optional software reset

Freeze signa l to facilitate debu gging

Interrupt Support Slave Attachment

- Register Interface

- SRAM Interface (for IP with SRAM-like interface)

- Supp ort for burst transactions (optional)

Master Attachment

- Supp ort single and burst transactions

- Transaction Qualification interface

- Transaction Response interface

Write FIFO

- BRA M b as ed- P ack et s u p p or t

- IP Status flags: Empty, Almost Empty, Occup ancy Count

Read FIFO

- BRA M b as ed

- P ack et s u p p or t

- IP Status flags: Full, Almost Full, Vacancy Count

DMA/ Scatter Gather

- M u lt ip l e ch a n n e ls

Figure 17: Write Transaction for IP Interconnect Using Register Access Feature

Bus2IP_Clk

Bus2IP_RegWrCE(i)

Bus2IP_WrReq

Valid WR DataBusIP2_Data

IP2Bus_RdAck

0

xip2056


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ReferencesR

- Can be used in conjunction with Read and Write FIFOs

- Optional packet capability for SG channels

- Optional interrupt coalescing feature for packet SG chann els

- Uses an IPIF-internal master interface

References MicroBlaze Software Reference Guide

MicroBlaze Hard wa re Reference Guide

OPB IPIF Architecture Specification

IBM On-Chip Peripher al Bus Architecture Specifications v2.1

Revision History

Date Description

September 7, 2001 Initial Release

Fe b ru a r y 8, 2002 M D K 2. 1


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