OPB PCI v1.02a User Guide...OPB PCI v1.02a User Guide 5 UG241 July 26, 2006 R Chapter 1 About This...

UG241 July 26, 2006 www.xilinx.com OPB PCI v1.02a User Guide

OPB PCI v1.02a User Guide

UG241 July 26, 2006

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OPB PCI v1.02a User Guide www.xilinx.com UG241 July 26, 2006

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

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UG241 July 26, 2006 www.xilinx.com OPB PCI v1.02a User Guide

OPB PCI v1.02a User Guide UG241 July 26, 2006

The following table shows the revision history for this document..

Version Revision

7/26/06 1.0 Initial Xilinx release.


OPB PCI v1.02a User Guide www.xilinx.com UG241 July 26, 2006


OPB PCI v1.02a User Guide www.xilinx.com 1UG241 July 26, 2006

Chapter 1: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2: Getting StartedAdditional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

OPB PCI Bridge Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Installing and Licensing the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Installing the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Licensing Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 3: CoreConnect and PCI Bus ArchitectureCoreConnect Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13PLB_V34 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PLB2OPB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14OPB2PLB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16OPB_V20 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PCI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Signaling Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Using the OPB PCI Bridge in Processor Based FPGAs . . . . . . . . . . . . . . . . . . . . . . . . 22Spartan PCI Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Recommended Parameter Settings for Other IP in an OPB PCI System . . . . . . . 27

Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27OPB2PLB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27OPB V20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 4: OPB PCI Bridge FunctionalityBlock Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

OPB PCI Bus Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table of Contents


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Configuration Header Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49PCI Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Using OPB PCI Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Chapter 5: ConfigurationOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Configuration Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57OPB PCI Bridge Configuration Generics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Bus Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Type 0 and Type 1 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62IDSEL Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Configuring Other Agents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Verifying the Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Configuring OPB PCI Bridge from PCI Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Chapter 6: PCI to OPB TransactionsGenerics and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83OPB PCI Bridge Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90PCI to OPB Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90PCI to OPB Read Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

FIFO Operation in PCI to OPB Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Non-Prefetchable Data Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Chapter 7: OPB to PCI TransactionsGenerics and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113OPB PCI Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120OPB to PCI Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Abnormal Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130OPB to PCI Read Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143FIFO Operation and Prefetchable Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Abnormal Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Chapter 8: Address TranslationRegisters and Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Address Translation Using High Order Bit Substitution . . . . . . . . . . . . . . . . . . . . 149

Chapter 9: Abnormal TerminationsRegisters and Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Abnormal Target Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Master Initiated Abnormal Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162



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Chapter 10: Error ConditionsRegisters and Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Parity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Reporting Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Chapter 11: InterruptsGenerics and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Device Interrupt Source Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Global Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176OPB PCI Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

PCI Bus Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Chapter 12: Design ConstraintsPinout and Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

UCF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Constraints Generated in EDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

IDelay Primitives in Virtex-4 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184Pin and Constraints Editor (PACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Chapter 13: Bus Functional Model SimulationSimulating Bus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Analyzing Bus Transactions in the Waveform Viewer. . . . . . . . . . . . . . . . . . . . . . . 192Running BFM Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Configuration from the On-chip Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Configuration from PCI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197PCI to OPB Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199PCI to OPB Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204OPB to PCI Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209DMA OPB to PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Reset Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Comprehensive OPB PCI Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221BFM Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223Running a BFM Simulation of the OPB PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Chapter 14: System SimulationSimulating with EDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Running System Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Setup of a System Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229



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Chapter 15: Software ProjectsDesign Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243SW Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Running the Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Chapter 16: Monta Vista LinuxBuilding and Booting a Linux Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Chapter 17: ChipscopeUsing ChipScope with OPB PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253



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Chapter 1

About This Guide

The OPB PCI User Guide provides information about the OPB PCI Bridge, which provides a fully verified, pre-implemented OPB PCI Bridge based on the Virtex™ and Spartan™ architectures. The guide serves as a comprehensive reference for use during the design phase of a project.

Guide ContentsPCI defines a double word (DWORD) as 32 bits. Double words in CoreConnect buses are 64 bits. Many of the chapters of this manual refer to generics, a term synonymous with parameters. Generics are used to define the configuration of the OPB PCI core, and always are prefixed with C_.

This manual provides many simulation waveforms to describe the functionality of the OPB PCI Bridge. A zip file allowing the simulation to be run and/or the waveform viewed interactively is provided at

http://www.xilinx.com/bvdocs/desfiles/ug241.zip

This manual contains the following chapters:

• The preface provides information about supporting documentation, getting technical support, and providing feedback to Xilinx about the PCI interface and its accompanying documentation.

• Chapter 2 Getting Started provides instructions for installing and licensing the PCI interface core. System requirements are listed.

• Chapter 3 OPB PCI Architecture provides the PLB, OPB, and PCI Bus overviews, and gives a reference system using the OPB PCI Bridge which illustrates its use in a CoreConnect based system. Within PCI, a double word is 32 bits. In CoreConnect, a double word is 64 bits.

• Chapter 4 OPB PCI Bridge Functionality provides functionality of the OPB PCI Bridge. This chapter provides a lot of detail, and can be used as a reference. Block diagrams of the components which comprise the OPB PCI Bridge are provided. Signal names and descriptions are given. Registers in the OPB PCI Bridge are defined. The use of generics to customize the OPB PCI Bridge is discussed. The PCI commands are given. It isn’t necessary to know the details in this chapter to understand the following chapters. It provides a quick reference for signal descriptions for simulation and debugging problems.

• Chapter 5 Configuration describes methods of configuring the OPB PCI Bridge and configuring external agents using the OPB PCI Bridge.



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• Chapter 6 provides instructions on executing PCI to OPB Write and Read transactions. This chapter provides an introductory, stand-alone sections on the PCI and OPB signals. This is followed by figures which define the functionality of the OPB and PCI signals together in the OPB PCI Bridge. This format sometimes requires the use of several figures to describe the transaction.

• Chapter 7 provides instructions on implementing OPB to PCI Write and Read transactions. This chapter provides an introductory, stand-alone sections on the OPB and PCI signals. This is followed by figures which define the functionality of the OPB and PCI signals together in the OPB PCI Bridge. This format sometimes requires the use of several figures to describe the transaction.

• Chapter 8 provides information on how to perform OPB to PCI Write and Read address translation and PCI to OPB Write and Read address translation.

• Chapter 9 Anormal Terminations defines abnormal PCI terminations, including Disconnect with Data, Disconnect without Data, Target Abort, and Master Abort

• Chapter 10 Errors describes error registers and reporting of errors

• Chapter 11 Interrupts describes interrupt support, principally from the OPB side.

• Chapter 12 Design Constraints defines how the PCI interface uses timing constraints during processing to ensure that the PCI timing requirements are met when the user design is added.

• Chapter 13 Bus Functional Model (BFM) Simulation discusses the BFM simulation of the OPB PCI Bridge. Waveforms of eight common transactions are provided in figures and as waveform (wlf/vcd files) output.

• Chapter 14 System Simulation shows how to simulate the OPB PCI Bridge in a system with a microprocessor running C code.

• Chapter 15 Software Projects provides software projects

• Chapter 16 MV Linux provides Monta Vista Linux projects

• Chapter 17 Chipscope describes how to insert Chipscope in the OPB PCI Bridge for debugging

• Chapter 18 Appendix provides a glossary of commonly used OPB and PCI terms.

Additional ResourcesFor additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging

http://support.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser Database of Xilinx solution records

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes Descriptions of device-specific design techniques and approaches

http://support.xilinx.com/apps/appsweb.htm


http://support.xilinx.com

http://support.xilinx.com/support/techsup/tutorials/index.htm

http://www.support.xilinx.com/xlnx/xil_ans_browser.jsp

http://support.xilinx.com/apps/appsweb.htm


ConventionsR

Conventions

TypographicalThe following typographical conventions are used in this document:

Data Sheets Device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging

Problem Solvers Interactive tools that allow you to troubleshoot your design issues

http://support.xilinx.com/support/troubleshoot/psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx design environment

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

Resource Description/URL

Convention Meaning or Use Example

Courier fontMessages, prompts, and program files that the system displays

speed grade: - 100

Courier boldLiteral commands you enter in a syntactical statement ngdbuild design_name

Italic font

Variables in a syntax statement for which you must supply values

ngdbuild design_name

References to other manualsSee the Development System Reference Guide for more information.

Emphasis in text

If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Square brackets [ ]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.

ngdbuild [option_name] design_name

Braces { } A list of items from which you must choose one or more lowpwr ={on|off}

Vertical bar | Separates items in a list of choices lowpwr ={on|off}


http://www.support.xilinx.com/support/troubleshoot/psolvers.htm

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp


Preface: R

Online DocumentThe following conventions are used in this document:

Vertical ellipsis . . .

Repetitive material that has been omitted

IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’ . . .

Horizontal ellipsis . . . Omitted repetitive material allow block block_name loc1 loc2 ... locn;



Blue textCross-reference link to a location in the current document

See “Additional Resources” for details.

See “Title Formats” in Chapter 1 for details.

Red text Cross-reference link to a location in another document

See Figure 2-5 in the Virtex-II Handbook.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.



R

Chapter 2

Getting Started

The OPB PCI Bridge is a fully verified 32-bit bridge between the OPB and PCI buses, with support for multiple Xilinx FPGA device families.

Additional DocumentationFor more information about the PCI interface core, see the following documents, located on the PCI product page:

• PCI Release Notes

• PCI Getting Started Guide

• LogiCORE PCI v3.0 UG159

• DS437 OPB PCI Product Specification

Additional information is available in the Mindshare PCI System Architecture text, and the PCI Local Bus Specification, available from the PCI Special Interest Group site.

Technical SupportFor technical support, visit www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the OPB PCI Bridge.

Xilinx provides technical support for use of this product as described in the OPB PCI v1.02.a User Guide, PCI User Guide and the PCI Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

FeedbackXilinx welcomes comments and suggestions about the OPB PCI Bridge and the documentation supplied with the core.

OPB PCI Bridge Core For comments or suggestions about the PCI interface core, please submit a webcase from www.xilinx.com/support. Be sure to include the following information:

• Product name

• Core version number

• Explanation of comments


http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-DI-PCI-AL

http://www.amazon.com/exec/obidos/tg/detail/-/0201409933/102-6399953-0414534?v=glance&vi=reviews

http://www.pcisig.com/home

www.xilinx.com/support



Chapter 2: Getting StartedR

Document For comments or suggestions about this document, please submit a webcase from www.xilinx.com/support Be sure to include the following information:

• Document title

• Document number

• Page number(s) of comments

• Explanation of comments

Installing and Licensing the CoreThis chapter provides instructions for installing and obtaining a license for the PCI interface core. The PCI core is provided under the terms of the Xilinx LogiCORE Site License Agreement or the Xilinx LogiCORE Project License Agreement, which conform to the terms of the SignOnce IP License/Project standard defined by the Common License Consortium. Purchase of the OPB PCI Bridge includes technical support and access to updates for a period of one year.

The evaluation and purchase process is described in

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=OPB_to_PCI_Full_Bridge

A second method to access the page is:

• Open XPS

• In the IP Catalog, right click on OPB PCI and select View License Status

• Click on Product Webpage and go to the core website

System Requirements

Windows

• Windows® 2000 Professional (Service Pack 2-4)

• Windows XP Home (Service Pack 1); Windows XP Professional (Service Pack 1)

Solaris/Linux

• Sun Solaris™ 8/9

• Red Hat™ Linux 7.3/8.0

Software

• ISE 8.1i or higher

• EDK 8.1i or higher

Note: If necessary, ISE 8.1i Service Packs can be downloaded from

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=8.1i

Installing the Core The OPB PCI Bridge is used in the EDK environment.



http://www.xilinx.com/ipcenter/doc/xilinx_click_core_site_license.pdf

http://www.xilinx.com/ipcenter/doc/xilinx_click_core_site_license.pdf

www.xilinx.com/ipcenter/doc/xilinx_click_core_project_license.pdf

http://www.xilinx.com/ipcenter/signonce.htm

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=ip&software=7.1i


Licensing OptionsR

Licensing Options

Evaluation For the OPB PCI Bridge core, register on the Xilinx IP Evaluation page at

www.xilinx.com/ipcenter/ipevaluation.

With the evaluation license, the core can be tested for a limited time (usually 8 hours) before timing out (ceasing to function), at which time it can be reactivated by reconfiguring the device.

Full The Full license is provided when the core is purchased, and provides full access to all core functionality both in simulation and in hardware, including:

• Gate-level functional simulation support

• Back annotated gate-level simulation support

• Full implementation support including place and route and bitstream generation

• Full functionality in the programmed device with no time-outs

To obtain a full license, purchase the core. Please contact your local Xilinx Sales Representative to purchase the core. After purchase, you will receive a letter containing a serial number. The serial number is used to register for access to the lounge, a secure area of the PCI product page.

Select PCI from

www.xilinx.com/company_contact.htm

and click Register to register and request access to the lounge. Xilinx will typically grant access to the lounge in 48 hours. (Contact Xilinx Customer Service if you need faster turnaround.) After receiving confirmation of lounge access, click Access Lounge on the PCI product page and log in. Follow the instructions in the lounge to fill in the license request form. Click Submit to automatically generate the license. An e-mail containing the license and installation instructions will be sent to you immediately.


www.xilinx.com/ipcenter/ipevaluation


Chapter 2: Getting StartedR



R

Chapter 3

CoreConnect and PCI Bus Architecture

The chapter provides reference information on the Processor Local Bus (PLB), On-Chip Peripheral Bus (OPB), and Peripheral Component Interface (PCI) Buses. The OPB PCI Bridge is used in systems which contain FPGAs with IBM PPC processor(s) or the MicroBlaze processor. These processors are connected to the PLB and OPB, respectively. Bus arbiters are discussed. Stand-alone signal waveforms illustrate PLB, OPB, and to a lesser extent, PCI bus operation. Waveforms for the PCI bus are given in many of the remaining chapters in this user guide.

An example illustrates how the OPB PCI Bridge is used with the PLB, OPB, and PCI buses.

CoreConnect ArchitectureFigure 3-1 illustrates the IBM CoreConnect™ architecture. This consists of the PLB, OPB, and DCR.

Figure 3-1: CoreConnect Architecture

Figure 3-2 shows the CoreConnect buses used for PLB to PCI bus transactions.

Processor Local Bus

On-

Chi

p P

erip

hera

l Bus

DMA

Controller

Memory Controller

SDRAM Controller

OPB Master

PLB to OPB Bridge

OPB to PLB Bridge

OPB Arbiter

OPB Slave

Internal Peripheral

DC

R B

us

Processor Core

Data Cache Unit

Instruction Cache Unit

PLB Arbiter

UG241_3-1_040606



Chapter 3: CoreConnect and PCI Bus ArchitectureR

PLB_V34 OverviewThe PLB is used for high speed peripherals. The PLB discussed in this manual is the PLB_V34. Documentation on the PLB is available in <EDK_install>/hw/XilinxProcessorIPLib/pcores/plb_v34_v1_01_a/doc. The PLB uses a split bus architecture. In a split bus architecture, the read and write data buses are independent. The address and request qualifier signals are shared. The PLB provides the capability for PLB slaves to queue address and qualifier requests, using address pipelining. Currently, no Processor IP PLB slaves support simultaneous read and write transfers or address pipelining. A PLB Master initiates PLB transactions, and a PLB slave responds to the PLB transaction requests.

The PLB Arbiter grants PLB access to the PLB Master and then routes the associated PLB slave reply to the master with the grant.

PLB Bus transactions involve address and data phases. In the address phase, address and transaction qualifiers are driven to the PLB slave by the PLB arbiter. The PLB address phase starts with the assertion of PLB_PAvalid by the PLB Arbiter, and terminates with the assertion of Sl_AddrAck by the target slave device. Data transfer occurs during the data phase. Read and write data phases can occur simultaneously on the PLB. The data phase starts with the assertion of Sl_AddrAck by the PLB slave and ends with the assertion of the Sl_wrDCmp or Sl_rdDCmp by the slave.

PLB Bus transactions can be either single data beat (1 to 8 bytes) or bursts, which can be of either fixed or indeterminate length. In fixed length bursts, 2-16 data beats are specified by the PLB Master using request qualifiers. In indeterminate length bursts, the PLB Master controls the length of the burst using M_wrBurst / M_rdBurst signals. The PLB Slave terminates the burst by asserting Sl_wrBterm or Sl_rdBterm.

The PLB Arbiter provides a 16 clock timeout monitor for the address phase. There is no timeout limit for PLB data phases, so a slave can hang the PLB if it does not complete the data phase of a request it has acknowledged. An address phase can be aborted by the requesting master. Data phases, once started, must complete.

Slave devices can throttle data transfers using Sl_rdDAck/Sl_wrDAck but PLB Masters cannot throttle data transfers.

PLB2OPB BridgeTo translate PLB transactions into OPB transactions, the PLB2OPB Bridge functions as a slave on the PLB side and as a master on the OPB side. The operation of the PLB2OPB

Figure 3-2: Buses and Bridges used for PLB to PCI bus transactions

Memory

PLB OPB

UG241_ch3-2_040606

OPB2PCIBridge

PPC405

PLB2OPBOPB2PLB

BridgesPCI



PLB_V34 OverviewR

Bridge is defined in DS403. This section, and the next on OPB2PLB Bridge, are intended to provide basic information needed to recognize retries and deadlocks.

Figure 3-3 is the pinout of the PLB2OPB Bridge. When a PLB write transaction is addressed to one of the address ranges of the PLB2OPB Bridge, the PLB slave of the PLB2OPB Bridge acknowledges the address phase of the PLB transaction by BGO_addrAck. The write data is accepted in the bridge and the PLB slave asserts BGO_wrDAck and BGO_wrComp to complete the data phase. This triggers the OPB master of the PLB2OPB Bridge to begin a write transaction on the OPB. If OPB_retry is asserted instead of OPB_xferAck, the OPB master retries the write transaction until successful.

When a PLB read transaction is addressed to one of the address ranges of the PLB2OPB Bridge, the PLB slave of the PLB2OPB Bridge asserts BGO_wait. The OPB master of the PLB2OPB Bridge starts the read transaction on the OPB. If an OPB retry is asserted instead of OPB_xferAck, the PLB slave asserts BGO_rearbitrate on the PLB. If OPB_xferAck is asserted, the PLB slave of the PLB2OPB Bridge acknowledges the address phase of the PLB transaction by asserting BGO_addrAck. The data phase is then completed in the following clock cycles by the PLB slave asserting BGO_rdDAck and BGO_rdComp because the OPB read transaction has already obtained the requested read data.




OPB2PLB BridgeTo translate OPB transactions into PLB transactions, the OPB2PLB Bridge functions as a slave on the OPB side and as a master on the PLB side. The operation of the OPB2PLB Bridge is defined in detail in DS404.

Figure 3-4 provides the OPB2PLB Bridge pinout.

Figure 3-3: PLB2OPB Bridge Pinout

PLB_PAValidPLB_busLockPLB_masterIDPLB_RNWPLB_BE[0:3]PLB_size[0:3]PLB_type[02]PLB_MSize[0:1]PLB_compressPLB_guardedPLB_orderedPLB_lockErrPLB_abortPLB_ABus[0:63]

BGO_addrAckBGO_waitBGO_SSize[0:1]BGO_rearbitrateBGO_MBusyBGO_MErrBGO_SAValidPLB_rdPrimPLB_wrPrimPLB_wrDBus[0:63]PLB_wrBurstPLB_rdBurst

BGO_BE[0:31]BGO_ABus[0:31]

BGO_busLockBGO_DBus[0:31]

BGO_requestBGO_RNWPLB_select

PLB_seqAddrPLB_wrDBus[0:63]

BGO_wrDAckBGO_wrCompBGO_wrBTermBGO_rdDBus[0:63]BGO_rdWdAddr[0:63]BGO_rdDackPLB_rdCompPLB_rdBTerm

PLB_ClkPLB_Rst

PLB_Trans_Abort

OPB_ClkOPB_Rst

Bus_Error_Det

PLB2OPB_rearb

OPB_DBus[0:31]OPB_errAck

OPB_MnGrantOPB_timeoutOPB_xferAck

OPBPLB

UG241_3-3_040606



PLB_V34 OverviewR

OPB_V20 OverviewThe OPB connects directly to the MicroBlaze microprocessor but not to the PPC405 processor. The OPB used in this manual is the OPB_V20. The PPC405 processor accesses slave peripherals on the OPB using the PLB2OPB bridge. Peripherals which are bus masters on the OPB access memory on the PLB using the OPB2PLB bridge. Lower performance peripherals attach to the OPB.

The OPB Arbiter connects to OPB masters using Mn_request and OPB_MnGrant signals. The OPB Arbiter also receives OPB_busLock, OPB_select, and OPB_xferAck signals. The Mn_request is asserted by the OPB master to request the bus. For single data transactions, Mn_request is de-asserted during the first cycle in which the bus is used. For continuous transfers, the OPB master asserts Mn_request until the last data transfer cycle. The OPB Arbiter asserts OPB_MnGrant to give control to the master requesting it.

Figure 3-5 provides a block diagram of the OPB_V20 arbiter. OPB_V20 contains the arbiter , bus OR logic, WDT timer, and reset circuitry.

Figure 3-4: OPB2PLB Bridge Pinout

OPB_selectOPB_ABus[0:31]OPB_RNWOPB_BE[0:31]OPB_DBus[0:31]OPB_seqAddr

BGI_DBus[0:31]BGI_retryBGI_toutSupBGI_xferAckBGI_errAckBGI_request

BGI_RequestBGI_ABus[0:31]

BGI_RNWBGI_BE[0:3]

BGI_sizeBGI_type

BGI_priorityBGI_rdBurstBGI_wrBurst

BGI_busLockBGI_abort

BGI_lockErrBGI_mSize

BGI_orderedBGI_compress

BGI_guardedBGI_wrDBus

PLB_RdWdAddrPLB_RdDBusPLB_AddrAckPLB_RdDAckPLB_WrDAck

PLB_RearbitratePLB_Busy

PLB_ErrPLB_RdBTerm

PLB_WRBTermPLB_SSize

PLB_pendReqPLB_pendPri

PLB_reqPri

OPB_ClkOPB_Rst

BGI_Trans_Abort

PLB_ClkPLB_Rst

Bus_Error_Det

OPB PLB

UG241_3-4_040606




The OPB Address Bus OPB_ABus(0:31) is used by OPB bus masters to select a unique OPB slave. The most significant bit is bit 0. The least significant bit is 31. The most significant byte of a halfword or fullword is the byte in the smallest binary address.

The OPB Data Bus (OPB_DBus) is used to transfer data between OPB masters and OPB slaves. In the 32-bit OPB_DBus(0:31), bit 0 is the most significant bit and bit 31 is the least significant bit. Bits 0-7 is the most significant byte.

The OPB_select / Mn_select is driven by the OPB master in the cycle following the assertion of the master’s OPB_MnGrant. The Mn_select signal qualifies all master control signals, and is driven until the master receives OPB_xferAck, OPB_retry, or OPB_timeout.

An OPB master for which MnGrant is asserted may abort a transfer cycle at any time by de-asserting Mn_select. If the select signal is de-activated, all slaves must terminate the transaction in progress. If the master de-asserts Mn_select and Mn_busLock is not asserted, the master must release the bus. If Mn_busLock is asserted, the master retains ownership of the bus.

The OPB_RNW indicates the direction of the data transfer. The signal is valid when OPB_select is active. A high on OPB_RNW is used to read slave data. A low is used by the master to write data to the slave.

The OPB Transfer Acknowledge (OPB_xferAck/Sln_xferAck) is asserted by the addressed slave to indicate that a data transaction between an OPB master and OPB slave is complete. OPB_xferAck is asserted for one clock cycle for each data transaction. OPB_xferAck is used for both read and write transactions.

The OPB Retry (OPB_retry/Sln_retry) is asserted by a OPB slave to indicate it is unable to complete the requested transaction. This is used to resolve deadlocks. Sln_retry is asserted instead of Sln_xferAck, and must remain asserted until OPB_select, Mn_request, and Mn_busLock are de-asserted. The OPB masters Mn_select, Mn_request, and Mn_busLock must remain de-asserted for one clock cycle, during which the OPB Arbiter rearbitrates for the bus.

The OPB_timeout is an OPB Arbiter output indicating to all OPB masters that a timeout error occurred. If there is no OPB_xferAck or OPB_retry response from the slave, OPB_timeout is asserted in the 16th clock cycle following the assertion of OPB_select. A

Figure 3-5: OPB_V20

Master 0 Master 1 Master 2 Master n

Slave 0 Slave 1 Slave 2 Slave m

OR of drivensignal (shared

OPB_V20

driven signals (individual)

OPB ArbiterOPB Bus Interconnect (bus ‘OR’ function)Power-on and WDT Reset

UG241_241_3-5_040606

OR of drivengnal (shared)

driven signals (individual)



PCI OverviewR

slave can assert OPB_ToutSup to suppress the OPB_timeout signal. When a master detects an OPB_timeout, the master which initiated the transaction terminates it by de-asserting Mn_select. Sln_ToutSup is used by the OPB Arbiter to disable the timeout counter and suppress the assertion of OPB_timeout.

The OPB does not directly support burst transactions. The OPB Sequential Address (OPB_seqAddr) signal is used to increase throughput. The Bus master asserts Mn_seqAddr to indicate that the current transaction is followed by a transaction to the next sequential address. The slave performs the same type of transaction (read or write) at the next sequential address. OPB_seqAddr is used with OPB_busLock so no other bus master uses the bus.

The Xilinx implementation of the OPB uses 32-bit address and data. Registers are aligned on dword boundaries.

Potential Deadlock

When a PLB master is requesting a read on the OPB and an OPB master is requesting a read on the PLB, there is potential for deadlock. The OPB2PLB bridge suppresses the OPB time-out while it waits for data from the PLB. The PLB is busy waiting for data from the OPB. Since the PLB doesn’t have a timeout mechanism during the data phase of a transaction, both buses are stalled. To prevent deadlock, the PLB2OPB Bridge waits C_BGI_TRANSABORT_CNT OPB clock cycles after asserting its OPB request for its grant to be asserted. If the grant is not asserted, the PLB2OPB Bridge asserts BGI_Trans_Abort to the OPB2PLB Bridge. This causes the OPB2PLB Bridge to retry the current OPB transaction which frees the OPB to the PLB2OPB Bridge’s transaction to occur.

PCI OverviewThe PCI bus consists of initiators and targets. The target is the device addressed by the initiator. Transactions are either single or bursts. In a burst transaction, the initiator arbitrates for the bus only once. Bursts on PCI are efficient because one dword can be transferred per clock cycle.

The 32-bit PCI bus is a time-multiplexed address data bus AD[31:0]. The Command/Byte Enable pins (CBE[3:0]) are multiplexed pins indicating the command (read/write) and the byte enables. Transactions start with an address phase, which is followed by the single or burst data phase. The initiator provides the start address on AD[31:0] and transaction type on CBE[3:0] during the address phase. The initiator provides the data on AD[31:0] and byte enables for data during the data phase.

Figure 3-6 is a basic PCI bus transaction. The initiator starts an address phase by asserting FRAME_N, providing the address on AD[31:0], and providing the command on CBE[3:0]. Central address decoding is not used on the PCI bus. Instead, all targets latch the address and transaction type to determine if it is addressed. Since the initiator provides only the start address in a burst, targets use internal counters to provide the address of DWORDs after the first in a burst.

The initiator indicates the length of the transaction (single or burst) by the duration FRAME_N is asserted. The initiator uses IRDY_N pin to signal to the target that it is ready to transmit or receive data. IRDY_N indicates the start of a data phase. For a write, data is valid on AD[31:0] when IRDY_N is asserted. Similarly, the target uses TRDY_N, along with DEVSEL_N and STOP_N, to signal to the target if it is ready to transmit or receive data. With the DEVSEL_N, TRDY_N, and STOP_N, the target indicates various normal and abnormal conditions. For a read, TRDY_N indicates that valid data is on AD[31:0]. The details are provided in the later chapters.




PCI ArbitrationThe PCI Bus generally has multiple initiators which may require bus access simultaneously. To execute a PCI transaction, an initiator requests and must be granted use of the bus. As shown in Figure 3-7, each initiator has REQ_N and GNT_N signals connected to the PCI Arbiter. When an initiator requires bus access, it asserts REQ_N. The PCI Arbiter asserts GNT_N, indicating that it is the next bus master. Only one GNT_N is active at once. The initiator with GNT_N asserted can begin a PCI transaction once the PCI bus is idle. The PCI bus is idle if FRAME_N and IRDY_N are de-asserted.

Bus arbitration on PCI is provided either by an external PCI arbiter or the PCI Arbiter core. The PCI specification does not specify an arbitration algorithm such as fixed or round robin. It only states that the algorithm must be fair.

The product specification for the Processor IP PCI Arbiter is DS495. Arbitration is done for two to eight PCI initiators. A rotating algorithm is used to provide PCI bus access to all initiators. Bus parking is used if no master requests the bus.

Figure 3-6: PCI Bus Transaction

0ns 20ns 40ns 60ns 80ns

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_NUG241_3-7_040606

Figure 3-7: PCI Bus Arbiter

D e vic e 1

D e vic e 3

REQ1#

UG241_3-8_040606

GNT1#

D e vic e 2

PCI Arbiter

REQ2#

GNT2#

REQ3#

GNT3#



PCI OverviewR

In Figure 3-7 and Figure 3-8, Devices 1-3 are initiators, with Device 1 and Device 2 requesting the PCI bus simultaneously. Device 1 asserts REQ1_N and the arbiter asserts GNT1_N. Device 2 asserts REQ2_N. Device1 detects GNT1_N asserted, and FRAME_N and IRDY_N de-asserted to indicate an idle bus, so it asserts FRAME_N to begin a transaction. Device 1 keeps REQ1_N asserted to execute a second transaction. The arbiter detects Device 2 REQ2_N asserted, and de-asserts GNT1_N and asserts GNT2_N.

Device 2 detects GNT2_N asserted, waits for the bus to become idle, and asserts FRAME_N to begin a transaction. Since it is a single transaction, Device 2 de-asserts REQ2_N.

The latency timer is included in every initiator on the PCI bus. The latency timer is used to prevent the PCI bus from being monopolized. The value in the latency timer, which is set in the latency timer field in the configuration header, is the maximum number of clock cycles an initiator owns the PCI bus when it initiates a transaction. The latency timer is loaded with the latency timer value when FRAME_N is asserted, and decrements on each clock cycle. If the counter reaches 0 before the transaction completes, the initiator’s GNT_N is de-asserted, and another initiator is requesting the bus, th ecurrent initiator must terminate its transaction. The current initiator usually immediately requests the bus so it can complete the transaction.

Using the Xilinx PCI Arbiter core rendors the latency timer ineffective.

Signaling Environments PCI signaling environments are both 3.3V and 5.0V.

For PCI mechanical information, read the PCI specification and refer to the PCI System Architecture text by Shanley/Anderson. Xilinx provides a number of development boards with 3.3V and 5.0V PCI slots, as well as PCI boards which can be inserted into the slots. Figure 3-9 shows the mechanical slots used for 3.3V and 5V PCI boards. This figure can be used to avoid inserting a PCI card into an incorrect slot.

Figure 3-8: PCI Arbitration

0ns 100ns

UG241_3-9_040606

200ns 300ns

PCI_CLK

REQ1_N

GNT1_N

REQ2_N

GNT2_N

FRAME_N

IRDY_N

TRDY_N

AD[31:0]




Using the OPB PCI Bridge in Processor Based FPGAsThis section discusses using the OPB PCI Bridge in FPGAs communicating over PLB, OPB, and PCI buses.

Figure 3-10 is a block diagram of the system which uses CoreConnect and PCI buses and the OPB PCI Bridge. The logic in the shaded block are typically done in an FPGA. The CPU is a PPC405. Memory for a system is usually a combination of external and on-chip memory. The Host/PCI Bridge is the OPB PCI Bridge. This is commonly called the North Bridge.

The figure shows a primary and secondary bus. Each bus has a bus number, and each function on the bus (e.g., the sound card) has a device number and a function number. The bus number, device number, and function number are discussed in detail in Chapter 5 Configuration.

The Xilinx Virtex PCI ML410 Development Board design provides the Virtex-4 access to two 33 MHz/32-bit PCI buses: a primary 3.3V PCI bus and a secondary 5.0V PCI bus. The FPGA is directly connected to the primary 3.3V bus. The 5.0V PCI bus is connected to the Primary PCI bus via a PCI-to-PCI bridge. The PCI-to-ISA bridge, or South Bridge, is often a stand-alone integrated circuit for communicating to the parallel port, PS2 keyboard, GPIO devices.

There are four PCI add-in card slots, two for 3.3V cards and two for 5.0V cards.

Figure 3-9: Keying for PCI Slots for Different Signaling Environments

5.0 V board

Universl dual-voltage board

3.3 V board

5.0 V connector 3.3 V connector

UG241_3-10_040606



Using the OPB PCI Bridge in Processor Based FPGAsR

Figure 3-11 shows the PPC405 and commonly used processor IP cores in the FPGA which contains the OPB PCI Bridge. The PLB2OPB Bridge and OPB2PLB Bridges are omitted to simplify the figure. These components are defined in the system.mhs using the Xilinx XPS design tool. This is typical for an OPB PCI Bridge providing a North Bridge function used to communicate to the sound card, video card, and Ethernet controller on the primary bus.

A second common application is to insert a PCI card in one of the four add in slots. This may be a Spartan based FPGA which uses MicroBlaze as the microprocessor. This FPGA contains the OPB PCI Bridge also. Because MicroBlaze interfaces to the OPB but not the PLB, the PLB2OPB Bridge and OPB2PLB Bridge are not included in the mhs file in this system.

Figure 3-11: Components in the FPGA containing the OPB PCI Bridge

Figure 3-12 shows the PCI Bus Devices on Xilinx development boards. The FPGA (U37) contains the IP cores specified in Figure 3-11. The TI2250 device (U32) is a PCI-to-PCI bridge to the two 5V PCI slots. The Intel GD82559 10/100 Ethernet NIC is used to connect to an Ethernet port. The ALi M1535D+ South Bridge interface to legacy devices, including the audio, modem, USB, and IDE ports.

Figure 3-10: OPB PCI Bridge in a System

Downstream

Primary PCI

Secondary PCI

DS241_3-11_040606

PCI/PCIBridge

SoundCard

VideoCard

EthernetController

SCSIController

CPU

PLB

Memory

PLB2OPBOPB2PLB

Bridges

Host/PCIBridge

Upstream

DS241_ch3-12_031006

PLBDCR

OPBGPIO

OPBINTC

PPC405

OPB

PLB

OPB UART 16550

OPBPCI

OPBSYSACE

PLBBRAM




Each device has a device ID and a vendor ID.

Figure 3-13 shows the connections of the South Bridge to the legacy devices.

Figure 3-12: PCI Bus Devices

PCI_P_AD31PCI_P_AD27PCI_P_AD26PCI_P_AD19PCI_P_AD18PCI_P_AD17

ALiSouth Bridge

U15

PCI_BUS

UG_241_3-13_040606

Device ID 0x54510x15330x54570x52370x52290x5237

Vendor ID10B910B910B910B910B910B9

IDSEL

USB#1IDE BusUSB#2Modem

S. BridgeAudio

PCI-to-PCIBridge TI2250

Intel 10/100Ethernet NIC

5.0V PCI Slot 6

Memec 2S200

5.0V PCI Slot 4

Virtex-II ProFPGA

XC2VP30

IDSELIDSEL

0xAC23 104C

0x1229 8086

PCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

IDSELPCI_BUS

PCI Bus

PCI_S_AD18PCI_S_CLK0

PCI_S_AD19PCI_P_AD25

3.3V

PCI_S_CLK1

3.3V PCI Slot 5

3.3V PCI Slot 3

PCI_P_AD21

PCI_P_AD22

PCI_P_AD23

5.0V

U32

U37

U11

PCI_P_AD24

PCI_P_CLK5

PCI_P_CLK4

PCI_P_CLK0

PCI_P_CLK1PCI_P_CLK2PCI_P_CLK3



Spartan PCI Development BoardR

Spartan PCI Development BoardThe OPB PCI in the Xilinx PCI motherboards can interface to a OPB PCI Bridge in the Spartan based PCI boards. The Spartan-II and Spartan-3 development boards are useful in testing PCI systems since they can act as target/initiators comminicating to the host bridge.

Figure 3-14 shows the Spartan-II Development board. The board includes two clock sources, a 32-bit PCI edge connector, 8 MB SDRAM memory, RS232C port, LED displays, ISP PROM, and a JTAG port. The MicroBlaze microprocessor is used in this design.

Figure 3-13: ALI Bus - PCI to Legacy Devices

PCI_P_AD31

PCI_P_AD27 PCI_P_AD26 PCI_P_AD19 PCI_P_AD18 PCI_P_AD17

ALi South B r idg e

X4

FPGA

PCI_P_AD24 OSC

32.768 MHz

PCI_P_CLK3

PCI_ B U S

IDSEL

U37

ISA

U15

PCI_ B U S

UG_241_3-14_040606

USB 1

USB 2

J3

PS/2 KBD

P2

GPIO

J5

FLASH

U4

SERIAL 1

SERIAL 2

P a r alle l P o r t

P1

PRIMA R Y ID E SECON D A R Y ID E

J16/J15

X2

OSC 48

MHz

X3

OSC 14.318 MHz

U1

A C9 7

X1

OSC 24.576 MHz

D e vice ID 0x5451 0x1533 0x5457 0x5237 0x5229 0x5237

V endor I D 0x10B9 0x10B9 0x10B9 0x10B9 0x10B9 0x10B9

IDSEL

USB#1 IDE Bus USB#2 Modem

S . B r idg e A udi o




Figure 3-15 shows the interface of multiple PCI boards, each using FPGAs with OPB PCI Bridge cores. Chapter 6 discusses OPB to PCI write and read transactions. These transactions are done if the PPC405 in the PCI Board on the motherboard writes/reads the SDRAM on the PCI board on the daughter board. Chapter 7 discusses PCI to OPB read and write transactions. These transactions are used if the MicroBlaze microprocessor in the PCI board on the daughterboard writes/reads the DDR on the PCI board on the motherboard.

Figure 3-14: Memec Design Spartan-II Development Board

Figure 3-15: Interfacing OPB PCI Bridges on Different Boards

UG241_15_0

UG241_3-16_040606

DDR

Motherboard

PCI

BRAM

OPB PCI PPC

OPB PCI

SDRAM

BRAM

MB

Daughterboard



Recommended Parameter Settings for Other IP in an OPB PCI SystemR

Recommended Parameter Settings for Other IP in an OPB PCI System

This section includes recommendations for generic settings to increase data throughput. Xilinx offers a PLB PCI Full Bridge in addition to the OPB PCI Bridge. If the source/destination of data is on the PLB, the PLB PCI Full Bridge provides advantages over the OPB PCI Full Bridge.

Memory ControllersTable 3-1 provides the settings for the memory controller to allow the memory controller to process burst/cacheline transactions.

OPB2PLB BridgeIf using PLB memory, configure the OPB2PLB Bridge to generate bursts on the PLB for writes, and configure it to pre-fetch data for reads. This is done by setting C_RNGn_BURST = 1 and C_RNGn_PREFETCH = 1, with n = address range.. The C_RNGn_LINE parameters have no effect when C_RNGn_BURST and C_RNGn_PREFETCH = 1.

If the OPB2PLB Bridge is not getting access to the PLB, increase the priority on the PLB by setting C_PLB_PRIORITY = 2. This should be done only after confirming via ChipScope that the OPB2PLB Bridge is not getting access on the PLB.

OPB V20Insure that the arbitration scheme on the OPB V20 is a dynamic priority arbitration scheme so that the OPB PCI Bridge gets fair access to the OPB. Setting this parameter to 1 sets the OPB V20 arbitration scheme to a Least Recently Used (LRU) algorithm.

Table 3-1: Memory Controller Settings

Memory Controller Parameters Value

OPB DDR C_INCLUDE_BURSTS 1

MCH OPB DDR C_INCLUDE_OPB_IPIF

C_INCLUDE_OPB_BURST_SUPPORT

1

MCH OPB DDR2 C_INCLUDE_OPB_IPIF

C_INCLUDE_OPB_BURST_SUPPORT

1

PLB DDR C_INCLUDE_BURST_CACHELN_SUPPORT 1

PLB DDR2 C_INCLUDE_BURST_CACHELN_SUPPORT 1



R

Chapter 4

OPB PCI Bridge Functionality

This chapter provides information on the OPB PCI core. Functional diagrams provide the blocks which comprise the OPB PCI Bridge. Signal names and descriptions are given. First time readers may concentrate on learning the primary I/O signals of the OPB PCI core. Internal signals of the major functional blocks are given to allow detailed understanding of the OPB PCI Bridge. Registers in the OPB PCI Bridge are defined. The generics for customizing the OPB PCI Bridge are discussed. PCI commands are discussed.

Block DiagramsFigure 4-1 provides a functional diagram of the OPB PCI Full Bridge core. The three functions of the core are the OPB IPIF, v3.0 PCI LogiCORE, and IPIF-v3 Bridge.

Figure 4-2 provides a detailed diagram of the OPB PCI Bridge, including the IPIF, IPIF-V3 Bridge, and v3 core. There are two shaded areas in the figure. The logic in the upper shaded area is used for OPB to PCI write/read transactions discussed in Chapter 6. The OPB PCI Bridge is parameterizable using generics which use C_* nomenclature. The generics allow logic to be included/excluded. The logic is included in the OPB PCI Bridge if the C_INCLUDE_OPB_MST2PCI_TRG = 1. The lower shaded area is logic used for PCI to OPB write/read transactions. This logic is included if C_INCLUDE_PCI2OPB_SLV = 1.

Figure 4-1: Simple Diagram of OPB PCI Blocks

OPBIPIF

PCIV3/IPIFBridge

V3

UG241_4-1_040606



Chapter 4: OPB PCI Bridge FunctionalityR

Figure 4-3 provides the I/Os for the OPB PCI core.

Figure 4-2: Detailed Diagram of OPB PCI Blocks

Figure 4-3: OPB PCI Bridge I/Os

EndianessTranslation

AddressTranslation

IPMaster SM

InterruptModule

OptionalDMA

MasterAttach

SlaveAttach

ResetModule

PCI2IPIFFIFO

IPIF2PCIFIFO

EndianessTranslation

TargetSM

PCIInitiator SM

AddressTranslation

IPIFSlave SM

IPIF/V3 BridgeIPIF

UG241_4-2_040606

C_INCLUDE_PCI2OPB_SLV

C_INCLUDE_OPB2PCI_TARG

OP

B B

us

v3.0Core

PC

I Bus

OPB_CLKOPB_RSTIP2INTC_IRPT

PCI_DBUS[0:31]PCI_XFERACKPCI_RETRYPCI_TOUTSUPPCI_ERRACK

OPB_ABUS[0:31]OPB_BE[0:3]OPB_DBUS[0:31]OPB_RNWOPB_selectOPB_ERRACKOPB_MGRANTOPB_RETRYOPB_TIMEOUTOPB_XFERACK

PCI_REQUESTPCI_BUSLOCKPCI_SELECTPCI_RNWPCI_BE[0:3]PCI_SEQADDRPCI_ABUS[0:31]

OPB PCI

AD[31:0]CBE[3:0]

PAR

FRAME_NDEVSEL_N

TRDY_NIRDY_N

STOP_NIDSEL

INTR_A

PERR_NSERR_N

REQ_NGNT_N

RST_NPCLK

INTR_A_INTREQ_N_TOARB

FRAME_IIRDY_I

BUS2PCI_INTRRCLK

UG241_4-3_040606



Block DiagramsR

Figure 4-4 provides V3 signals. The signals on the left interface to the PCI bus, defined in Table 4-1. The signals on the right interface to the IPIF-v3 bridge, which are defined in Table 4-4.

Figure 4-4: V3 Signals

AD_IO[63:0]CBE_IO[7:0]PAR_IOPAR64_IO

FRAME_IOREQ64_IOTRDY_IOIRDY_IOSTOP_IODEVSEL_IOACK64_IOIDSEL_IO

INTA_O

PERR_IOSERR_IO

REQ_0GNT_I

V3

CFG[255:0]FRAMEQ_NREQ64Q_N

TRDYQ_NIRDQ_N

STOPQ_NDEVSELQ_N

ACK64Q_NADDR[31:0]ADIO[63:0]CFG_VLDCFG_HITC_TERM

C_READYADDR_VLD

BASE_HIT[7:0]S_CYCLE64

S_TERMS_READYS_ABORTS_WRDN

S_SRC_ENS_DATA_VLD

S_CBE[7:0]PCI_CMD[15:0]

REQUESTREQUESTHOLD

COMPLETEM_WRDN

M_READYM_SRC_EN

M_DATA_VLDM_CBE[7:0]TIME_OUTM_FAIL64

CFG_SELFM_DATADR_BUS

I_IDLEM_ADDR_N

IDLEB_BUSYS_DATA

BACKOFFSLOT64INTR_N

PERRO_NSERRO_NKEEPOUTCSR[39:0]

SUB_DATA[31:0]CLKRST

UG241_4-4_040606




Pinout DescriptionSignal descriptions are provided in Table 1, Table 2, Table 3, and Table 4.

Table 4-1: PCI Bus Signals

Signal Name

I/O Functional Description

AD[31:0] STS AD[31:0] is a time-multiplexed address and data bus. Each bus transaction consists of an address phase followed by one or more data phases.

CBE[3:0] STS CBE[3:0] is a time-multiplexed bus command and byte enable bus. Bus commands are asserted during an address phase on the bus. Byte enables are asserted during data phases.

PAR STS PAR generates and checks even parity across AD[31:0] and CBE[3:0].

When the PCI interface is the source of an address or data, the interface generates even parity across AD[31:0] and CBE[3:0] and presents the result on PAR one cycle after the values were presented on AD[31:0] and CBE[3:0].

When the interface receives an address or data, the interface checks for even parity across AD[31:0] and CBE[3:0] and compares it to PAR one cycle later. Parity errors are reported via PERR.



Pinout DescriptionR

Transaction Control

FRAME_N STS FRAME_N is driven by an initiator to indicate a bus transaction. FRAME_N is asserted for the duration of the operation and is deasserted during the last data phase to identify the end of the transaction.

When operating as an initiator, the core interface asserts FRAME_N when all of the following conditions are met:

• GNT_N has been asserted for more than one cycle

• IRDY_N and FRAME_N are de-asserted, meaning the bus is idle

• The bus master enable bit (CSR2) is set in the command register

• The IPIF-v3 Bridge application has asserted REQUEST or REQUEST64

FRAME_N is de-asserted upon any of the following conditions:

• The IPIF-v3 Bridge asserts COMPLETE

• The interface receives a termination from the addressed target (retry, disconnect, or abort)

• Not receiving a DEVSEL assertion from the addressed target (master abort)

• The internal latency timer has expired, if enabled, and the system arbiter is no longer asserting GNT_I

• A 32-bit target responds to a 64-bit transfer request

DEVSEL_N STS DEVSEL_N indicates that a target has decoded the address presented during the address phase and is claiming the transaction. This occurs when the address matches one of the Base Address Registers in the target.

TRDY_N STS TRDY_N indicates that the target is ready to complete the current data phase. When TRDY_N is asserted, the target is ready to transfer data.

Data transfer occurs when both TRDY_N and IRDY_N are asserted on the bus.

IRDY_N STS IRDY_N indicates that the initiator is ready to complete the current data phase. When IRDY_N is asserted, the initiator is ready to transfer data.

Data transfer occurs when both TRDY_N and IRDY_N are asserted on the bus.

Table 4-1: PCI Bus Signals (Continued)

Signal Name





STOP_N STS STOP_N indicates that the target has requested to stop the current transaction. The target uses STOP_N to signal a disconnect, retry, or target abort.

STOP_N is automatically asserted during non-linear memory transactions, performing disconnect with data.

IDSEL_I I IDSEL_I indicates that the OPB PCI Bridge is the target of a configuration cycle.

Interrupts

INTA_N OD INTA_N requests an interrupt. This may be disabled by setting the interrupt disable bit in the command register.

Error Signals

PERR_N STS PERR_N indicates that a parity error was detected while the v3 was the target of a write transfer or the initiator of a read transfer.

Parity errors are reported two clock cycles after the data transaction appeared on the AD and CBE lines. Parity error reporting on PERR is enabled by setting the report parity errors bit (CSR6) in the command register.

Parity errors, except those during special cycles, are reported in the status register (CSR31). Additionally, the initiator reports parity errors during a transaction when it is the bus master. The error is reported via the data parity error detected bit (CSR24) in the status register if the report parity errors bit (CSR6) is set in the command register.

SERR_N OD SERR_N indicates that a parity error was detected during an address cycle, except during special cycles.

SERR_N is asserted on the third clock after FRAME_N is first asserted. System errors are reported on the signaled system error bit (CSR30) in the status register if the SERR_N enable bit (CSR8) and the report parity errors bit (CSR6) are set in the command register.

SERR_N is an open-drain output. Per the PCI Local Bus Specification, SERR is not actively driven high after assertion.

Arbitration

REQ_N STS REQ_N indicates to the arbiter that the PCI initiator requests access to the bus. The initiator may only request the bus when it has been enabled by setting the bus master enable bit (CSR2) in the command register.

GNT_N STS GNT_N indicates that the arbiter has granted the bus to the PCI initiator.

If GNT_N is asserted and there is not a pending request, or the bus master enable bit is not set, the v3 performs bus parking.


Signal Name




Pinout DescriptionR

System Signals

RST_N I RST_N is the PCI Bus reset signal. This signal is used to bring PCI-specific registers, sequencers, and signals to a consistent state. When RST_N is asserted, PCI output signals are three-stated.

PCLK I PCLK is the PCI Bus clock signal. This signal provides timing for all transactions on the PCI Bus and is an input to every PCI device. The frequency of PCLK may vary as allowed in the PCI Local Bus Specification.

RCLK I RCLK is a reference clock input present only in specific Virtex-4 implementations. It is a reference clock used to calibrate input delay lines. See the PCI Getting Started Guide for additional information.

64-bit Extension (not supported in standard OPB PCI Bridge)

AD[63:32] STS AD[63:32] is a time-multiplexed address and data bus. Each bus transaction consists of an address phase followed by one or more data phases. During address phases presented by 64-bit initiators, AD[31:0] is driven with valid (reserved) values.

CBE[7:4] STS CBE[7:4] is a time-multiplexed bus command and byte enable bus. During address phases presented by 64-bit initiators, CBE[7:4] is driven with valid (reserved) values. Byte enables for the 64-bit extension are asserted during data phases.

PAR64 STS PAR64 generates and checks even parity across AD[63:32] and CBE[7:4].

When the PCI interface is the source of an address or data, the interface generates even parity across AD[63:32] and CBE[7:4] and presents the result on PAR64 one cycle after the values were presented on AD[63:32] and CBE[7:4].

When the interface receives an address or data, the interface checks for even parity across AD[63:32] and CBE[7:4] and compares it to PAR64 one cycle later. Parity errors are reported via PERR.

ACK64 STSactivelow

ACK64 indicates that a target has decoded the address presented during the address phase and is claiming the transaction as a 64-bit target. This occurs when the initiator makes a 64-bit transfer request using REQ64, the address matches one of the Base Address Registers in the target, and the target is 64-bit enabled.

Not used.


Signal Name





The signals for the OPB IPIF are given in the Table 4-2 which provides the signal descriptions for the OPB signals.

REQ64_N STS REQ64_N is driven by the initiator to indicate a 64-bit bus transaction. REQ64 is asserted for the duration of the operation and is deasserted during the last data phase to identify the end of the transaction. Its behavior is similar to FRAME.

When operating as an initiator, the v3 asserts REQ64 when all of the following conditions are met:

• GNT_I has been asserted for more than one cycle

• IRDY and FRAME are deasserted, meaning the bus is idle

• The bus master enable bit (CSR2) is set in the command register

• The IPIF-v3 Bridge has asserted REQUEST64

The core interface deasserts REQ64 upon any of the following conditions:

• The IPIF-v3 Bridge asserts COMPLETE

• The interface receives a termination from the addressed target (retry, disconnect, or abort)

• Not receiving a DEVSEL assertion from the addressed target (master abort)

• The internal latency timer has expired, if enabled, and the system arbiter is no longer asserting GNT_I

• A 32-bit target responds to a 64-bit transfer request

Notes: 1. The OPB PCI Bridge standard configuration does not support 64-bit operation.2. In the I/O description, STS is sustained tri-state, and OD is open drain.

Table 4-2: OPB IPIF Signals

Signal Name I/O Functional Description

OPB_clk I OPB bus clock.

Reset I OPB bus reset.

Freeze I Debug freeze signal.

OPB_ABus(0:C_OPB_AWIDTH-1)

I OPB Address Bus

OPB_DBus(0:C_OPB_DWIDTH-1)

I OPB Data Bus

OPB_BE(0:[C_OPB_DWIDTH/8]-1)

I OPB Byte Enable


Signal Name




Pinout DescriptionR

The signals in Table 4-3 are internal IPIC signals. The IPIC is the interface between the IPIF and the IPIF-v3 Bridge. The entries under the I/O column are relative to the IPIF interface.

OPB_Select I OPB Select

OPB_RNW I OPB Read/Write Enable

OPB_seqAddr I OPB Sequential Address

Sln_DBus(0:C_OPB_DWIDTH-1)

O Slave Data Bus

Sln_xferAck O Slave Transfer Acknowledge

Sln_errAck O Slave Error Acknowledge

Sln_retry O Slave Retry

Sln_toutSup O Slave Timeout Suppress

Mn_request O Master Request

Mn_busLock O Master Bus Lock

Mn_ABus(0:C_OPB_AWIDTH-1)

O Master Address Bus

Mn_BE(0:C_OPB_DWIDTH/8-1)

O Master Byte Enable

Mn_select O Master Select

Mn_RNW O Master Read/Write Enable

Mn_seqAddr O Master Sequential Address

OPB_MnGrant I Master Grant

OPB_xferAck I OPB Transfer Acknowledge

OPB_errAck I OPB Error Acknowledge

OPB_retry I OPB Retry

OPB_timeout I OPB Timeout

Table 4-3: IPIC Signals


IP2INTC_Irpt O Device interrupt output to microprocessor interrupt input or system interrupt controller. Registered level type, asserted active high.

Bus2IP_Clk O IPIC clock pass-through from OPB_Clk.

Bus2IP_Reset O Active high reset for use by the IPIF-v3 Bridge.

Bus2IP_Freeze O Active high signal requesting an operational freeze of the IPIF-v3 Bridge.

Table 4-2: OPB IPIF Signals





IP2Bus_IntrEvent(0:C_IP_INTR_MODE_ARRAYlength -1)

I IPIF-v3 Bridge interrupt signals to be captured in the IPIF IP ISC. The number and capture properties are set by C_IP_INTR_MODE_ARRAY VHDL.

Bus2IP_Data(0:31) O Write data bus to the IPIF-v3 Bridge. Write data is accepted by the IP during a write operation by assertion of the IP2Bus_WrAck signal and the rising edge of the Bus2IP_Clk.

Bus2IP_Addr(0:31) O Address bus indicating the address of the requested read or write operation.

Bus2IP_RNW O This signal indicates the direction of a requested operation with the IPIF-v3. High is a read, low is a write.

Bus2IP_BE(0:3) O Byte enable qualifiers for the requested read or write operation with the IPIF-v3 Bridge. Bit 0 corresponds to Byte lane 0, Bit 1 to Byte lane 1, and so on.

Bus2IP_Burst O Active high signal indicating that the active read or write operation with the IPIF-v3 Bridge is utilizing bursting protocol. This signal is asserted for each data beat of the burst transfer.

Bus2IP_WrReq O Active high signal indicating the initiation of a write operation with the IP. It is asserted for one Bus2IP_Clk during single data beat transactions and remains high to completion on burst write operations.

Bus2IP_RdReq O Active high signal indicating the initiation of a read operation with the IP. It is asserted for one Bus2IP_Clk during single data beat transactions and remains high to completion on burst write operations.

Bus2IP_CS(0:C_ARD_ID_ARRAY length - 1)

O Active High chip select bus. Each bit of the bus corresponds to an entry in the C_ARD_ID_ARRAY. Assertion of a chip select indicates a active transaction request to the chip selects target address space.

Bus2IP_CE O Active high chip enable bus. Chip enables are assigned per the Users entries in the C_ARD_NUM_CE_ARRAY. Chip enables are asserted during active transaction requests with the target address space and in conjunction with the corresponding sub-address within the space.

Bus2IP_RdCE O Active high chip enable bus. Chip enables are assigned per the Users entries in the C_ARD_NUM_CE_ARRAY. These chip enables are asserted only during active read transaction requests with the target address space and in conjunction with the corresponding sub-address within the space.





Pinout DescriptionR

Bus2IP_WrCE O Active high chip enable bus. Chip enables are assigned per the Users entries in the C_ARD_NUM_CE_ARRAY. These chip enables are asserted only during active write transaction requests with the target address space and in conjunction with the corresponding sub-address within the space.

IP2Bus_Data(0:C_IPIF_DWIDTH -1)

I Input Read Data bus from the IPIF-v3 Bridge. Data is qualified with the assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk.

IP2Bus_WrAck I Active high Write Data qualifier. Write data on the Bus2IP_Data Bus is accepted by the IPIF-v3 Bridge at the rising edge of the Bus2IP_Clk and IP2Bus_WrAck asserted high by the IPIF-v3 Bridge.

IP2Bus_RdAck I Active high read data qualifier. Read data on the IP2Bus_Data Bus is deemed valid at the rising edge of Bus2IP_Clk and the assertion of the IP2Bus_RdAck signal by the IPIF-v3.

IP2Bus_Retry I Active high signal indicating the IPIF-v3 Bridge is requesting a retry of an active operation.

IP2Bus_Error I Active high signal indicating the IPIF-v3 Bridge has encountered an error with the requested operation. This signal is asserted in conjunction with IP2Bus_RdAck or the IP2Bus_WrAck.

IP2Bus_ToutSup I Active high signal requesting suppression of the transaction time-out function in the IPIF for the active read or write operation.

IP2Bus_PostedWrInh I Active high signal requesting full handshake transfer protocol for all write transactions to the IPIF-v3 Bridge. This is generally used to slow down writes into a IPIF-v3 FIFO if it is nearing a possible overrun condition.

IP2Bus_Addr(0:C_OPB_AWIDTH-1)

I Address bus from the IPIF-v3 Bridge used to convey the desired address to be output on the OPB Bus during IP Master read or write operations. The address value must be valid during the assertion of the IP2Bus_MstWrReq or IP2Bus_MstRdReq signal.

IP2Bus_MstBE(0:(C_IPIF_DWIDTH/8) -1)

I Byte Enable bus from the IPIF-v3 Bridge used to convey the desired Byte Enables to be output on the OPB Bus during IP Master single data beat read or write operations. The byte-enable value must be valid during the assertion of the IP2Bus_MstWrReq or IP2Bus_MstRdReq signal.






IP2IP_Addr(0:C_OPB_AWIDTH-1)

I Address bus from the IPIF-v3 Bridge output on the IPIF Local Bus during IP Master read or write operations. The address value must be valid during the assertion of the IP2Bus_MstWrReq or IP2Bus_MstRdReq signal.

IP2Bus_MstWrReq I Active high signal initiating a Master write transaction.

IP2Bus_MstRdReq I Active high signal initiating a Master read transaction.

IP2Bus_MstBurst I Active high signal indicating that the corresponding Master transaction uses burst protocol. IP Master bursts are only of fixed-size eight.

IP2Bus_MstBusLock I Active high signal requesting a OPB Bus Lock assertion during the corresponding Master transaction request.

Bus2IP_MstWrAck O Active high signal indicating that a write data beat of the requested write transaction is completed at the next rising edge of the Bus2IP_Clk.

Bus2IP_MstRdAck O Active high signal indicating that a read data beat of the requested read transaction is completed at the next rising edge of the Bus2IP_Clk.

Bus2IP_MstRetry O Active high signal indicating that the Master is requesting a retry on the active Master transaction request.

Bus2IP_MstError O Active high signal indicating that the Master has encountered an error on the active Master transaction request.

Bus2IP_MstTimeout O Active high signal indicating that the Master has encountered a bus time-out on the active Master transaction request.

Bus2IP_MstLastAck O Active high signal. When concurrent with MstWrAck or MstRdAck, Bus2IP_MstLastAck indicates that the last data beat (either read or write) of the requested transaction is completed at the next rising edge of the Bus2IP_Clk. When concurrent with Bus2IP_MstRetry, Bus2IP_MstLastAck indicates that there is no data buffered in the IPIF that could not be stored before the retry is reported. When concurrent with Bus2IP_MstError, Bus2IP_MstLastAck indicates an error completion of the master transaction.

Bus2IP_IPMstTrans O Active high signal indicating that the current read or write operation on the slave port (with the IPIF) is initiated by the Master transaction request interface.





Pinout DescriptionR

Table 4-4 provides the signals of the v3 which interface with the IPIF-V3 Bridge.

DMA2IP_Wr_ Imminent_n

Active-low indication that data is read from the OPB by the local DMA controller and presented in an IPIC write transaction. The earliest that the data is presented is one clock after the first clock edge for which this signal is asserted low.

RmtOPBmst2IP_Wr Burst_Imminent

Active-high indication that burst data from a OPB master is to be presented in an IPIC write transaction. The earliest that the data is presented is one clock after the first clock edge for which this signal is asserted.

Table 4-4: V3 Signals


Configuration

CFG[255:0] I CFG[255:0], driven by a cfg module, configures the PCI interface.

Cycle Control

FRAMEQ_N O FRAMEQ_N is a registered version of the PCI Bus FRAME_IO signal.

DEVSELQ_N O DEVSELQ_N is a registered version of the PCI Bus DEVSEL_IO signal.

IRDYQ_N O IRDYQ_N is a registered version of the PCI Bus IRDY_IO signal.

TRDYQ_N O TRDYQ_N is a registered version of the PCI Bus TRDY_IO signal.

STOPQ_N O STOPQ_N is a registered version of the PCI Bus STOP_IO signal.

Address and Data Path

ADDR[31:0] O ADDR[31:0] holds PCI Bus addresses latched during address phases. The address is available in the cycle following the assertion of ADDR_VLD and remains stable until ADDR_VLD is asserted again.

ADIO[31:0] TS ADIO[31:0] is a time-multiplexed address and data bus.






Target Control

ADDR_VLD O ADDR_VLD indicates the beginning of a potential address phase on the PCI Bus and that the address is on the ADIO[31:0] internal bus. The latched address is presented on ADDR[31:0] one cycle later. The PCI Bus command on S_CBE[3:0] is latched, decoded, and presented on PCI_CMD[15:0].

ADDR_VLD is active only during potential target operations. It is not asserted during address phases that result from core initiator activity.

CFG_VLD O CFG_VLD indicates the beginning of a potential configuration cycle. This signal is similar to ADDR_VLD but is further qualified by IDSEL_I.

S_DATA_VLD O S_DATA_VLD indicates that a data transaction has occurred on the PCI Bus while the v3 is a target. S_DATA_VLD is asserted on the clock cycle after data transfer occurs on the PCI Bus and the target state machine is in the S_DATA state.

When receiving data, S_DATA_VLD also indicates that the data is available on the ADIO bus. When sourcing data, S_DATA_VLD indicates successful data transfer.

S_SRC_EN O S_SRC_EN is an enable signal used to increment a data pointer when the interface is the source of data in a target burst read.

S_WRDN O S_WRDN indicates the data transfer direction during target transactions. During target writes, S_WRDN is asserted. During target reads, S_WRDN is deasserted.

PCI_CMD [15:0]

O PCI_CMD[15:0] indicates the current decoded and latched PCI Bus operation. This bus is a fully decoded (one-hot) version of the current PCI Bus command. The command is captured during the address phase and remains stable until the next address phase.

S_CBE[3:0] O S_CBE[3:0] indicates the current PCI Bus command or byte enables for a target access. Byte enables are active low.





Pinout DescriptionR

BASE_HIT [7:0]

O BASE_HIT[7:0] indicates that one of the Base Address Registers has decoded and matched an address. The bus is one-hot encoded. The BASE_HIT signals are active for one clock cycle, the cycle preceding the S_DATA state.

CFG_HIT O CFG_HIT indicates the start of a valid configuration cycle. The CFG_HIT signal is active for one clock cycle, the cycle preceding the S_DATA state. This signal is similar in nature to the BASE_HIT signals.

C_READY O C_READY signals that the IPIF-v3 Bridge is ready to transfer configuration data. This is one of the signals which controls TRDY_IO.

For most applications, C_READY should always be asserted. The exceptions are applications that require access to user configuration space. In the OPB PCI Bridge, C_READY is always asserted.

C_TERM I C_TERM signals that the IPIF-v3 Bridge is terminating the transfer of configuration data. This is one of the signals which controls STOP_IO.

For most applications C_TERM should always be asserted. The exceptions are applications that require wait states when accessing user configuration space.

In the OPB PCI Bridge, C_TERM is always asserted.

S_READY I S_READY signals that the IPIF-v3 Bridge is ready to transfer data. This is one of the signals which controls TRDY_IO.

If the IPIF-v3 Bridge is not ready to transfer data, S_READY is delayed until the application is ready to support a sustained burst transfer.

S_TERM I S_TERM signals that the IPIF-v3 Bridge is terminating the transfer of data. This is one of the signals which controls STOP_IO.

S_ABORT I S_ABORT is used to signal a serious error condition which requires the current transaction to stop.

S_ABORT is used to signal an address overrun during a burst transfer or an unaligned 64-bit access.






Initiator Control

REQUEST I REQUEST is used to request a PCI initiator transaction. Assertion of REQUEST causes the PCI interface to assert REQ_O if the bus master enable bit (CSR2) is set in the command register. REQUEST is cleared at reset.

REQUESTHOLD I REQUESTHOLD is used to force an extended bus request. Assertion of REQUESTHOLD causes the v3 to assert REQ_O if the bus master enable bit (CSR2) is set in the command register.

Unlike the REQUEST signal, REQUESTHOLD is not an input to the core initiator state machine. REQUESTHOLD is intended to allow applications with very demanding bandwidth requirements to keep REQ_O asserted as long as possible.

M_CBE[3:0] I M_CBE[3:0] is used by the IPIF-v3 Bridge to drive command and byte enables during initiator transactions. Bus commands are presented during the assertion of M_ADDR_N, and byte enables are presented during the M_DATA state. Byte enables are active low.

M_WRDN I M_WRDN indicates the data transfer direction during initiator transactions. During initiator writes, M_WRDN is asserted. During initiator reads, M_WRDN is de-asserted.

COMPLETE I COMPLETE signals the initiator state machine to finish the current transaction. Once asserted, COMPLETE remains asserted until the state machine leaves the M_DATA state. COMPLETE is one of the signals which controls FRAME_IO and IRDY_IO.

M_READY I M_READY signals that the IPIF-v3 Bridge is ready to transfer data. If deasserted, wait states are inserted. This is one of the signals which controls IRDY_IO.

If the IPIF-v3 Bridge is not ready to transfer data, M_READY is delayed until it is ready to support a sustained burst transfer.

M_DATA_VLD O M_DATA_VLD indicates that a data transaction has occurred on the PCI Bus while the v3 is an initiator. M_DATA_VLD is asserted on the clock cycle after data transfer occurs on the PCI Bus and the initiator state machine is in the M_DATA state.

When receiving data, M_DATA_VLD indicates that the data is available on the ADIO bus. When sourcing data, M_DATA_VLD indicates successful data transfer.

M_SRC_EN O M_SRC_EN is an enable signal used to increment a data pointer when the v3 is the source of data in an initiator burst write.





Pinout DescriptionR

CFG_SELF I CFG_SELF indicates to the v3 that it is allowed to issue a configuration cycle to itself. The assertion of CFG_SELF overrides the bus master enable bit (CSR2) and modifies the internal data path. It is used only in host bridge applications.

TIME_OUT O TIME_OUT indicates that the internal latency timer has expired and that the initiator has exceeded the maximum number of clock cycles allowed by the system configuration software.

If the latency timer expires while the system arbiter is still asserting GNT_I, the operation continues until either the operation completes, or the arbiter de-asserts GNT_I. If the latency timer expires and the system arbiter has already deasserted GNT_I, the operation terminates. This termination is handled like any other target termination.

Note: The default latency timer value is 0, indicating immediate time-out. Ensure that the system configuration software writes a sufficiently large value in the latency timer register to allow the desired transfer size.

State Machine - Initiator

M_DATA O M_DATA indicates that the initiator is in the data transfer state. The M_DATA state occurs after the assertion of M_ADDR_N unless a single cycle assertion of GNT_I occurs.

DR_BUS O DR_BUS indicates that the bus is parked on the OPB PCI Bridge. The initiator is responsible for driving the AD_IO[31:0] bus, CBE_IO[3:0] bus, and the PAR_IO signal to prevent these three-state bus signals from floating. The actual values driven on these lines are not important.

M_ADDR_N O M_ADDR_N indicates that the initiator is in the address state. During this time, a valid address is provided on ADIO and a valid bus command on M_CBE.

M_ADDR_N is asserted with a one clock cycle overlap with either the I_IDLE or DR_BUS states.

I_IDLE O I_IDLE indicates that the initiator is in the idle state. The initiator is either not enabled, does not have an active request pending, or has not received GNT_I from the system arbiter.

The state machine is in either the I_IDLE or DR_BUS state when the bus master enable bit (CSR2) in the command register is reset.

State Machine - Target

IDLE O IDLE indicates that the target is in the idle state.






B_BUSY O B_BUSY indicates that the PCI Bus is busy. An agent has started a transaction (FRAME_IO has been asserted) but the target state machine either has not yet finished decoding the address or has determined that it is not the target of the current operation.

S_DATA O S_DATA indicates that the target is in the data transfer state. The target has decoded the address and matched it to one of its Base Address Registers or a configuration operation is in progress.

BACKOFF O BACKOFF indicates that either S_TERM or C_TERM are asserted, and the target state machine is waiting for the transaction to complete.

Miscellaneous Signals

PERRQ_N O PERRQ_N is a registered version of the PCI Bus PERR_IO signal.

SERRQ_N O SERRQ_N is a registered version of the PCI Bus SERR_IO signal.

INTR_N I INTR_N signals an interrupt request. The assertion of this signal generates an interrupt request on the PCI Bus unless the interrupt disable bit of the command register is set. Once the INTR_N signal is asserted, it must remain asserted until the device driver clears the interrupt.

KEEPOUT I KEEPOUT isolates the internal ADIO bus from the PCI core interface. This allows data transfer over ADIO without interference.

CSR[15:0] O CSR[15:0] provides access to the command register state bits. These bits are directly set or reset through the system configuration software. All values in the command register are either registered or read-only.

Note: The bus master enable bit must be set in the command register before the initiator can access the PCI Bus. The I/O access enable bit and/or the memory access enable bit must be set in the command register before the target will respond.





Pinout DescriptionR

CSR[31:16] O CSR[31:16] provides access to the status register state bits. Individual status bits are reset by the system software by writing a 1 to the bit location to be reset. All values in the status register are either registered or read-only. Fast back to back transactions are not supported.

CSR[39:32] O CSR[39:32] provides access to the transaction status signals. These are an extension of the standard command and status register bits and reflect the status of a PCI transaction.

With the exception of “master abort”, these status bits reflect any bus activity, as they are derived from registered copies of PCI Bus signals. CSR[38:32] are combinational outputs generated by the equations shown below.

SUB_DATA [31:0]

I SUB_DATA[31:0] performs one of two functions depending on the v3 configuration. If the v3 is not configured to use external Subsystem ID, SUB_DATA provides the CardBus CIS Pointer data. If the v3 is configured to use external Subsystem ID, SUB_DATA provides the Subsystem ID data.

System Signals

CLK O CLK is the PCI Bus clock driven by a global clock buffer.

RST O RST is an inverted signal of the PCI Bus reset signal.

64-bit Extension (not supported in standard OPB PCI Bridge)

REQ64Q_N Oactivelow

REQ64Q_N is a registered version of the PCI Bus REQ64_IO signal. Not used.






RegistersThis section contains register descriptions. The OPB PCI Bridge contains two sets of registers. One set is accessible from the OPB. The second set is the registers in the Configuration Header, which are accessible from either the OPB or PCI bus

Table 4-5 provides the registers used when the OPB PCI Bridge is a host bridge. The OPB addresses are given.

ACK64Q_N Oactivelow

ACK64Q_N s a registered version of the PCI Bus ACK64_IO signal. Not used.

ADIO[63:32] TS ADIO[63:32] is a time multiplexed address and data bus. Not used.

S_CYCLE64 O S_CYCLE64 indicates that the v3 is engaged in a 64-bit target transaction. This signal is asserted at the same time as BASE_HIT and remains asserted until the transaction is complete.

S_CBE[7:4] O S_CBE[7:4] indicates the current PCI Bus command or byte enables for a target access. Byte enables are active low.

REQUEST64 I REQUEST64 is used to request a 64-bit PCI initiator transaction. Assertion of REQUEST64 causes the v3 to assert REQ_O if the bus master enable bit (CSR2) is set in the command register. This bit is cleared at reset.

M_FAIL64 O M_FAIL64 indicates that a 64-bit initiator transfer attempt has encountered a 32-bit target. In such situations, the initiator transfers at most two 32-bit words before terminating the transfer.

The M_FAIL64 signal should be used to adjust the increment value (step size) of initiator address pointers.

SLOT64 I SLOT64 is used to enable the 64-bit extension. Refer to the appropriate implementation guide for details.

M_CBE[7:4] I M_CBE[7:4] is used by the initiator to drive byte enables during initiator transactions. Byte enables are active low.





RegistersR

OPB PCI Bus Interface Register

1. TOW - Toggle on Write

Configuration Header RegistersA configuration header is provided for each function. The header is 256 bytes. The first 64 bytes are defined as shown in Figure 4-5. There are three types of configuration headers. Type 0 is used for most devices. Type 1 is used for a bridge device. Type 2 is used for a PC card device. The Header type field at offset 0CH defines whether the header is Type 0, 1, or 2.

The vendor ID identifies the silicon vendor (0x00). The device ID and revision ID identify the device and revision level of the device. Valid identifiers are assigned by the PCI Special Interest Group to guarantee that each identifier is unique. The value 10EEh, provided in the default configuration, is the Vendor ID for Xilinx. The value FFFFh is reserved.

Table 4-5: OPB PCI Bus Interface Registers

Register Name OPB Address Access

Device Interrupt Status Register (ISR) C_BASEADDR + 0x00 Read/TOW

Device Interrupt Pending Register (IPR) C_BASEADDR + 0x04 Read/Write

Device Interrupt Enable Register (IER) C_BASEADDR + 0x08 Read/Write

Device Interrupt ID (IID) C_BASEADDR + 0x18 Read

Global Interrupt Enable Register (GIE) C_BASEADDR + 0x1C Read/Write

Bridge Interrupt Register C_BASEADDR + 0x20 Read/TOW

Bridge Interrupt Enable Register C_BASEADDR + 0x28 Read/TOW

Reset Module C_BASEADDR + 0x80 Read/Write

Configuration Address Port C_BASEADDR + 0x10C Read/Write

Configuration Data Port C_BASEADDR + 0x110 Read/Write

Bus Number/Subordinate Bus Number C_BASEADDR + 0x114 Read/Write

Inhibit Transfers on Errors C_BASEADDR + 0x120 Read/Write

OPB Master Error Definition C_BASEADDR + 0x124 Read/TOW

OPB Master Read Address C_BASEADDR + 0x128 Read

OPB Master Write Address C_BASEADDR + 0x12C Read

IPIFBAR2PCIBAR_0 High-Order Bits C_BASEADDR + 0x180 Read/Write



IPIFBAR2PCIBAR_3 High-Order Bits C_BASEADDR + 0x18C Read/Write



Host Bridge Device Number C_BASEADDR + 0x198 Read/Write




The subsystem vendor ID and subsystem device ID allow suppliers of PCI plug in adaptors to identify their devices (0x2C). The Subsystem Vendor ID further qualifies the manufacturer of the device or application. Typically, C_SUBSYSTEM_VENDOR_ID is the same as the Vendor ID. Setting it to 0000h may cause issues with compliance testing. The C_SUBSYSTEM_ID identifies the device, revision, or other manufacturing data.

By default, the Subsystem Vendor ID and Subsystem ID are set at design time and part of the resulting interface netlist.

Enabling the External Subsystem ID allows these fields to be dynamic and supplied through the SUB_DATA bus (0x2C). This may be used to load unique values which are determined by the IPIF-v3 Bridge at run-time. When this feature is enabled, the CardBus CIS Pointer is disabled and set to zero (0x28). This is not supported in the OPB PCI Bridge.

The class code identifies the device’s function. The default C_CLASS_CODE and C_REV_ID values identify the device as a generic co-processor function. The Class Code is divided into three byte-size fields as described in the PCI Local Bus Specification. The upper byte broadly identifies the type of function performed by the device. The middle byte defines a sub-class that more specifically identifies the device’s function. The sub-classes are defined in Appendix D of the PCI Local Bus Specification. The lower byte defines a specific register-level programming interface (if any). This allows device-independent software to interact with the device.

The latency timer is required and must be read/writable for any master capable of bursting more than two clock phases (0x2C). The function of the latency timer is to prevent a bus master from monopolizing the bus if other masters require access. The latency timer field is the minimum number of clock cycles, from the assertion of FRAME_N, that a master can retain ownership of the bus when it initiates a transaction. A 0xFF value in the Latency timer provides a minimum of 255 clock cycles.

The Maximum Latency (Max_Lat) field defines how quickly the device needs to access the PCI bus, in increments of 250 ns (0x3C). This allows the configuration software to determine the masters priority. A low value is a requirement for low latency, requiring a high priority.

The Minimum Grant (Min_Gnt) register specifies the time the master retains ownership of the bus when a transaction is initiated, again in increments of 250 ns (0x3C). Configuration software uses the value of Min_Gnt to set the Latency Timer of devices.

The Base Address Registers (BARs) are used by configuration software to determine the memory and I/O resources needed by a device. The configuration software determines the system topology, and then writes the starting address into the BARs.

There two formats for BARs are defined later in this chapter.

The CardBus CIS Pointer is used in CardBus applications (0x28). By default, this field is supplied through the SUB_DATA bus. If the CardBus CIS Pointer is not used, the SUB_DATA bus is set to zero. If the interface is configured to use an external Subsystem Vendor ID and Subsystem ID via SUB_DATA, the CardBus CIS Pointer is disabled and always set to zero.

The v3 has the ability to implement a Capabilities List in configuration space. The OPB PCI Bridge does not support a Capabilities List. If the design requires a Capabilities List, enable this option and set the pointer to the desired address in configuration space. Otherwise it is set to zero. Enable the User Config Space option. This requires custom design support.



RegistersR

Figure 4-6 shows the content of the Command register. The Command register is located in the Configuration Header at offset 0x04. For the OPB PCI Bridge, the fields of principle interest are IO Space, Memory Space, Bus master Parity Error Response, and SERR_N Enable.

Figure 4-7 shows the content of the Status register. The Status register is located in the Configuration Header at offset 0x04.

Figure 4-5: Configuration Header

Figure 4-6: Command Register

Base Address Register 0 BIST

Base Address Register 1 Base Address Register 2 Base Address Register 3 Base Address Register 4 Base Address Register 5 CardBus CIS Pointer

Class Code Status Device ID Vendor ID

Revision ID Command

Header Type Cache Line Size

Subsystem Vendor ID

Capabilities Pointer

Subsystem ID

Min_Gnt Interrupt Pin Interrupt Line Reserved

Reserved

Max_Lat

Expansion ROM Base Address

0x0031 bits 16 bits 15 bits 0 bits

0x040x080x0C0x100x140x180x1C0x200x240x280x2C0x30

0x34

0x380x3C

UG241_4-5_041706

Fast Back-to-Back Enable SERR# Enable

Stepping Control Parity Error Response

VGA Palette Snoop Enable Memory Write/Invalidate

Special Cycles Bus Master

Memory Space IO Space

0

UG241_4-6_071706

1234567891015 Reserved




Figure 4-8 provides the two formats of the Base Address Registers (BARs). The BARS allow configuration software to determine the memory and I/O resources needed by a device. After scanning the PCI bus, the configuration software maps all devices into the BARs. The Type 0 configuration header supports up to six BARS. Bit 0 specifies that the BAR is for memory or I/O. If the BAR is for memory, bits 1-2 specify how the memory is mapped and the size of the BAR. If the BAR is for I/O space, bit 1 = 0, and the remaining bits map the device.

For PCI to OPB transactions, the OPB PCI Bridge supports up to three BARs, with the number defined by C_PCIBAR_NUM. Each BAR has several attributes. These attributes define:

• Whether the BAR is enabled. Disabling the BAR allows the optimization tools to delete the entire circuit.

• The size of the address space required. The address space ranges from 16 bytes to two gigabytes. For 80x86 systems, the maximum allowed I/O space is 256 bytes. This is defined by C_PCIBAR_LEN_N.

• The ability of memory space to be prefetched is defined by C_PCI_PREFETCH_N. The PCI Local Bus Specification defines memory as prefetchable if:

♦ there are no side-effects on reads (i.e. data is not destroyed by reading, as from a RAM).

♦ byte write operations can be merged into a single double-word write, when applicable.

• Whether the address space is defined as memory or I/O by C_PCI_SPACE_TYPE_N. The BAR only responds to commands that access the specified address space.

• Endian translation is enabled by C_PCIBAR_ENDIAN_TRANSLATE_EN_N.

• The address space location “preference” of the device. The v3 supports 32-bit address spaces for both memory and I/O.

• Whether the BAR address space is 64-bit capable. This only applies to memory spaces, and is not available in the standard release.

Memory spaces less than 4K in size should use a 4K block size, as recommended in the PCI Local Bus Specification. The maximum I/O space allowed is 256 bytes. Some machines may disable a card if it requests more than 256 bytes of contiguous I/O space.

Figure 4-7: Status Register

Capabilities List66 MHz CapableReservedFast Back-to-Back CapableData Parity Error DetectedDEVSEL Timing 00 - Fast 01 - Medium 10 - SlowSignal Target AbortReceived Target AbortReceived Master AbortSignaled System ErrorDetected Parity Error

UG241_4-7_071706

034567891015 14 13 12 11



PCI Bus CommandsR

PCI Bus CommandsThe PCI bus command for a transaction is output on the CBE pins during the address phase. The command data in CBE is active high. The byte enables, which are active during the data phase, are active low.

The PCI bus uses three address spaces for the read/write commands: memory, I/O, and configuration. A distinction between memory and I/O space is that memory can be prefetchable, in which case reads from memory bus have no side effects. Configuration space is normally used only at boot time to configure all the PCI cards in the system.

Figure 4-8: Base Address Register

Prefetchable Type

Memory Space Indicator

00 - Locate Anywhere in 32-Bit Space 01 - Reserved 10 - Locate Anywhere in 64-Bit Space 11 - Reserved

UG241_4-8_040606

Reserved Memory Space Indicator

01

01

23

Table 4-6: PCI Commands

CBE3 CBE2 CBE1 CBE0 Hex Command Target Initiator

0 0 0 0 0 Interrupt Acknowledge No Yes

0 0 0 1 1 Special Cycle No No

0 0 1 0 2 I/O Read No Yes

0 0 1 1 3 I/O Write No Yes

0 1 0 0 4 Reserved Ignore Ignore


0 1 1 0 6 Memory Read Yes Yes

0 1 1 1 7 Memory Write Yes Yes



1 0 1 0 A Configuration Read Yes Optional

1 0 1 1 B Configuration Write Yes Optional

1 1 0 0 C Memory Read Multiple Yes Yes




The basic memory commands are Memory Read and Memory Write. The Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate are used to increase performance. The support of these commands by the OPB PCI Bridge is given in Table 4-6. The Memory Read Line and Memory Read Multiple commands require that target memory be prefetchable.

The Memory Read Line command indicates to the target that the master is to read the full cache line, allowing the target to set up to supply the full line. A master uses the Memory Read Multiple command to indicate it will read more than one cache line before disconnecting, so the target can prefetch the next cache line.

The Memory Write and Invalidate command is similar to the Memory Write command, with the master writing a full cache line in a single PCI transaction. This is useful when a transaction hits a dirty line in a writeback cache. Since the master is updating the entire line, the cache can invalidate the line without writing it back.

The Cache Line Size configuration register in the Configuration Space Header must be implemented by bus masters which use Memory Write. It should be used for bus masters that use Memory Read Line and Memory Read Multiple commands.

Targets must not assert DEVSEL_N to reserved bus commands. Using a reserved bus command causes the initiator to generate a Master Abort.

The initiator uses the Dual-Address Cycle (DAC) command to indicate it is using 64-bit memory addressing to address a memory target beyond the 4 GB boundary.

The Special Cycle command is used by the master to broadcast a message to one or more targets on the PCI bus. The command register in the Configuration Space Header has a Special Cycle bit which indicates whether it should detect a Special Cycle command.

Using OPB PCI GenericsThis section describes how to modify the OPB PCI Bridge. Generics are used to reduce resources required, generally at the expense of functionality or performance. Many of these generics are related to the specifications in the v3 cfg.vhd file. Table 3 OPB PCI Bridge Parameters-Port Dependencies in the OPB PCI Full Bridge product specification (DS437) define which of these generics are legal/used as a function of the settings of the other generics. Table 6 Register and Parameter Dependencies in DS437 provides the effects of generics on the registers included in the OPB PCI Bridge.

The size of the OPB PCI Bridge ranges from approximately 700 LUTs to 4150 LUTs, if all functionality is included. The generics used to set up OPB PCI Bridge functionality are C_INCLUDE_PCI_CONFIG, C_INCLUDE_OPB_MST2PCI_TRG, and C_INCLUDE_PCI_INT2OPB_SLV. Generics which affect both functionality and performance are C_DMA _CHAN_TYPE, C_IPIF2PCI_FIFO_ABUS_WIDTH, and C_PCI2IPIF_FIFO_ABUS_WIDTH.

1 1 0 1 D Dual-Address Cycle Ignore No

1 1 1 0 E Memory Read Line Yes No

1 1 1 1 F Memory Write and Invalidate

Yes No

Table 4-6: PCI Commands (Continued)

CBE3 CBE2 CBE1 CBE0 Hex Command Target Initiator



Using OPB PCI GenericsR

The OPB PCI bridge consists of two half bridges, allowing reduced device utilization if only a target or initiator is needed. Removing a target or initiator saves as much as 1000 LUTs. Setting C_DMA_CHAN_TYPE = 9 removes DMA, which save LUTs, but it impacts performance.

Most applications set C_INCLUDE_RESET_MODULE = 0 to save area. The interrupt functionality when C_INCLUDE_INTR_MODULE = 1 provides almost the same information the error registers, so many applications set C_INCLUDE_ERR_REG_MODULE = 0.

The configuration generics depend on whether the bridge is configured from the OPB or PCI side. Set C_INCLUDE_PCI_CONFIG = 1 to configure from the OPB side. The C_INCLUDE_PCI_CONFIG generic requires that C_INCLUDE_OPB_MST2PCI_TARG is set to 1. The C_INCLUDE_DEVNUM_REG generic determines if a register or generic determines the device number. If C_INCLUDE_DEVNUM_REG = 0, the C_BRIDGE_IDSEL_ADDR_BIT generic defines the address bit on the address bus used to select configuration cycles. The value of C_BRIDGE_IDSEL_ADDR_BIT must be consistent with the C_NUM_IDSEL value.

If C_INCLUDE_OPB_MST2PCI_TARG = 0, C_INCLUDE_PCI_CONFIG is not used. When C_INCLUDE_PCI_CONFIG = 1, the IDSEL pin is not used.

The interrupt module registers can only be included if FIFOs are included.

The value of C_INCLUDE_DEVNUM_REG is limited by the value in C_NUM_IDSEL.

The number of registers set when C_INCLUDE_BAROFFSET_REG is set by C_IPIFBAR_NUM.

DMA requires C_INCLUDE_OPB_MST2PCI_TARG = 1 and C_DMA_CHAN_TYPE = 0.

OPB PCI Bridge PerformanceThe OPB can be clocked at any frequency up to 100 MHz or more. The PCI bus can be clocked up to 33 MHz. Figure 4-9 shows the absolute maximum PCI bus performance of a PCI initator transferring data to a PCI target in which the bus clock is 33 MHz.

Figure 4-9: PCI Throughput vs Burst Size

0 50 100 150 2000

50

100

150

Number of Words per Burst

MB

ytes

/s




As shown, the data throughput is dependent on the burst size. Bursts must start on dword boundaries. The plot shows ideal conditions in which neither the initiator or slave throttles data. Once data transfer occurs, data is transferred every clock cycle after the first. Both read and write cycles are approximately the same, and at large burst sizes, they approach the maximum rate of 132 MB/s. At smaller burst sizes, the data throughput can be significantly less than 132 MB/s

In a real system, several factors reduce data throughput, including bus arbitration time, how fast the target responds, and data throttling by both the initiator and target. There are setup/overhead operations in the OPB PCB Bridge, including two arbitration operations, which limit data throughput. This performance analysis indicates that under an ideal system that the 132 MB/s PCI performance is possible. In most systems, the maximum perfromance is in the 40 MB/s range.

In the following section, the theoretical performance of the OPB PCI Bridge is given for the four basic transactions supported.

PCI Initiator Write to OPB Slave

In an analysis of a PCI initiator write to an OPB slave, it is assumed that the PCI arbiter provides a grant in the first clock cycle after the initiator requests the bus. It is also assumed the OPB PCI Bridge is not busy with another transaction and can respond to the PCI initator request. The data is buffered in a FIFO. The bridge accepts the data as fast as the PCI initiator sources the data, i.e., since single clock cycle data tranfers are supported. The IPIF is the master on the OPB. As the master, the IPIF can generate a single word transfer or a burst of 8 words per request. The OPB PCI Bridge requests the OPB, transfers 8 words as fast as the target slave accepts the data, and then gets off the bus. To transfer more data, the OPB PCI Bridge repeats this process. The OPB PCI Bridge can only burst write 8 words at a time. This can result in significant overhead for large bursts since the setup penalty occurs every 8 words. This is not a problem if the OPB clock runs much faster than the PCI clock.

If the OPB clock is 2.75 times faster than the PCI clock, the 8 word OPB burst write limit does not significantly affect throughput. If burst writes are 35 words or more, the data throughput is greater than 100 MB/s. If the burst size is 90-100 words, the data throughput approaches the maximum supported by the PCI bus, 132MB/s. The dependence on the OPB clock frequency when it is less than 2.75 times the PCI clock frequency is significant. At an OPB clock frequency of 75 MHz, the maximum throughput is 100 MB/s. At an OPB clock frequency of 50 MHz, the maximum data throughput is 68 MB/s.

Data throughput is affected by PCI initiator throttling and arbitration on both the PCI and OPB. It is especially sensitive to OPB bus arbitration because the IPIF performs so many requests for bus access since a request is made every 8 words. Data throughput is also reduced by throttling of data flow by the destination OPB slave.

If the slave requires more than one OPB clock cycles to accept a word, data throughput is reduced. If 4 OPB clock cycles per word are required, and OPB clock is 50 MHz, the data throughput maximum is 50 MB/s.

PCI Initiator Read of an OPB Slave

Assuming the OPB PCI Bridge is not busy with another transaction and responds to the PCI initiator request, and the grant is given on the clock cycle following a request, the OPB PCI Bridge can provide data as fast as the PCI initiator can accept the data. Single clock



Using OPB PCI GenericsR

data transfers are supported. This requires data to be available in the FIFO. The IPIF is the OPB master, and does either a single word read or a burst read of 8 words per bus request. As with a write, there is significant overhead for burst read operations since the setup is required every 8 clock cycles. This is not a problem if the OPB clock is 1.65 times the PCI clock. The ratio is less on the read cycle because the IPIF requires more time to write to than to read from an OPB slave. The setup time is larger for a read than a write, so that a larger read burst size is needed to approach the maximum 132 MB/s data throughput.

If prefetching is done, and the PCI initiator reads data in bursts of 70 or more, data throughput exceeds 100 MHz. Data throughput approaches 132MB/s at several hundred words per burst. As with the PCI write transaction, data throughput is affected by PCI initiator throttling, by arbitration on both the PCI and OPB bus, and by throttling of data flow by the OPB slave. OPB bus arbitration has the strongest impact on data throughput. If the OPB slave requires 5 OPB clock cycles to transfer a word, the data throughput is limited to 20 MB/s.

OPB Master Write to a PCI Target

If the OPB PCI Bridge is not busy with another transaction and the arbiter grants the bus on the clock cycle following the request, the OPB master write to a PCI target can approach 132 MB/s. The OPB PCI bridge supports any burst size of the OPB write transaction. The burst size is limited by the OPB master device writing the data to the OPB PCI Bridge. The bridge can accept any size up to the FIFO depth at 1 word per clock cycle. According to the OPB specification, the OPB master cannot throttle the data. Since the OPB PCI Bridge does not throttle data, data is transferred with single clock cycles per data transfer during burst writes. There is an initial delay before the IPIF accepts the first word.

At the defined occupancy level in the FIFO, a request is made for PCI bus access. When the data phase is entered, the bridge provides the data on the PCI bus as fast as the PCI target can accept it. This continues until the FIFO is empty.

If the OPB clock is slower than the PCI clock, PCI transfers can empty the FIFO before all the data is transferred to the FIFO by the OPB master. In this case, the OPB PCI Bridge must end the PCI transfer because the v3.0 does not permit throttling of the data. When the FIFO is emptied by faster PCI transfer, the bridge starts another transaction, or as many as needed to complete the transfer. Repeated requests lower throughput.

OPB Master Read from a PCI Target

In this transaction, the read request to the IPIF crosses time domains in the IPIF-v3.0 bridge and is presented to the v3.0 core. The v3.0 core request access to the PCI bus and reads data from the PCI target. The data is buffered in the FIFO. The OPB PCI bridge provides the data as fast as the data is read from the PCI target source. The data can be transferred in one clock cycle if data is available in the FIFO. The OPB PCI Bridge accepts any burst size up to the FIFO depth at 1 word per clock cycle. The OPB specification does not allow the OPB master to throttle the data. The OPB PCI Bridge only throttles data if the PCI target throttles data on the PCI bus. There is an initial delay before the first word is fetched from the PCI target.

When the FIFO is empty, the OPB PCI Bridge throttles data on the OPB while waiting for data from the PCI target. If the OPB clock is slower than the PCI clock, the FIFO can be filled. If filled, the OPB PCI Bridge must end the PCI transfer since the v3.0 core does not allow data throttling. If the OPB master continues requesting data, at the defined FIFO




occupancy level, the OPB PCI Bridge starts another transaction, or as many as needed to complete the transfer. Repeated requests lowers the data throughput.

Analyzing Performance

If a design has performance issues, Xilinx recommends that a ChipScope trace be captured as define in the chapter titled ChipScope. Determine if the OPB and PCI bus are granted access quickly. Determine the number of clock cycles a target/slave requires to respond. On the PCI side, TRDY_N is de-activated to insert wait states. Determine if there are a large number of OPB or PCI retries.



R

Chapter 5

Configuration

This chapter discusses the configuration of the OPB PCI Bridge. In this chapter, configuration refers to the configuration of the PCI Configuration Header. The v3.0 module in the OPB PCI Bridge has a Configuration Header, as do all agents on a PCI bus. The configuration generics and registers are defined. Following an overview of bus hierarchy, Type 0 and Type 1 configuration are defined in the context of bus hierarchy. A method to generate the configuration chip select signal, IDSEL, is provided. The self configuration of the v3.0 in the Host/PCI bridge and the configuration of external agents are discussed. The steps used to verify that the OPB PCI Bridge is configured correctly are provided.

The OPB PCI Bridge can also be configured from the PCI bus. An example is given.

OverviewAn advantage of PCI is support for Plug n Play. Configuration of devices/add in cards is done without setting jumpers. Configuration software scans the system at power-up to determine resource requirements, and assigns memory, I/O, and interrupts to PCI functions on individual cards. The configuration software also determines which devices require bus master capability and sets their arbitration priority. The PCI bus scanning is initially done by BIOS, and subsequently by the operating system. If a system has PCI expansion connectors, cards which have PCI-PCI bridges can be installed at any time. The Host/PCI bridge must be able to configure all PCI functions on all PCI buses.

In a typical PCI Bus system, reading and writing of configuration registers is done by a software writing to a host bridge. The OPB PCI Bridge is capable of acting as a host bridge. A host bridge is a subset of a central resource as defined in Section 2.4 of the PCI Local Bus Specification. A central resource, and a host bridge as part of a central resource, require additional design considerations beyond those for a generic PCI agent.

The v3.0 in the OPB PCI can be configured from the OPB or PCI bus. When the OPB PCI Bridge is configured with host bridge capability, the v3.0 in the host OPB PCI Bridge is configured first, followed by the configuration of external agents.

Configuration Register DescriptionsThe Configuration Address Port (CAP), Configuration Data Port (CDP), and Bus Number/Subordinate Bus Number (BNSBN) registers are used if the OPB PCI bridge is configured with host bridge configuration functionality. The Host Bridge Device Number (HBDN) register is optionally used in configuration.



Chapter 5: ConfigurationR

The Configuration Address Port, Configuration Data Port, and Bus Number/Subordinate Bus Number registers are on the OPB-side of the bridge and are not accessible from the PCI-side via I/O transactions on the PCI bus.

Table 5-1 defines the content of the Configuration Address Port.

The Configuration Data Port register is defined in Table 5-2. In the Configuration Address Port and Configuration Data Port registers, the format of the bytes defined in the PCI specification are swapped. The PCI Bus uses little endian word format while the OPB uses big endian format.

The Bus Number/Subordinate Bus Number (BNSBN) register contains the bus number, an 8-bit value defining the primary bus number, and the highest subordinate bus number, also an 8-bit value. The BNSBN register fields are defined in Table 5-3.

Table 5-2: Configuration Data Port Register

Bit(s) Access Reset Value Description

0-31 Read/Write 0x00000000 Data in Configuration Read or Configuration Write

Table 5-1: Configuration Address Port Register

Bit(s) AccessReset Value

Description

0-5 Read/Write 0x00Identifies the target word address within the function’s configuration space (1-64)

6-7 Read 0b00 Hard-wired to 0. Read-only

8-12 Read/Write 0x00 Identifies the target PCI Device (0-31)

13-15 Read/Write 0x00 Identifies the target function (1-8)

16-23 Read/Write 0x00 Identifies the target PCI Bus (1-256)

24 Read/Write 0b0 Active high enable bit

25-31 Read 0x00 Reserved and hardwired to 0. Read only.

Table 5-3: Bus Number/Subordinate Bus Number Register

Bit(s) AccessReset Value

Description

0-7 Read 0x00 Reserved

8-15 Read/Write 0x00 Bus number

16-23 Read 0x00 Reserved

24-31 Read/Write 0x00 Maximum subordinate bus number



Configuration Register DescriptionsR

The Host Bridge Device Number (HBDN) register defines the device number. The HBDN register is used to select the address bit that is internally connected to the IDSEL signal. The maximum value in the HBDN register is C_NUM_IDSEL-1.

The OPB PCI Bridge, by default, implements the first 64 bytes of a Type 0 Configuration Header, shown in Figure 5-1. Additional configuration registers are available if the User Config option is enabled in the v3.0 configuration file, beginning at offset 40H This file is not accessible in the standard OPB PCI Bridge..

Unimplemented configuration registers, shown in gray in Figure 5-1, return a value of zero during configuration read cycles. No operation occurs if a configuration write is attempted to an unimplemented field. BIST, Line Size and Expansion ROM Base Address are not implemented.

Fields of the Configuration Header are Device ID, Vendor ID, Class Code, Rev ID, Subsystem ID, Subsystem Vendor ID, Maximum Latency and Minimum Grant. The parameters in the OPB PCI Bridge for these fields are C_DEVICE_ID, C_VENDOR_ID, C_CLASS_CODE, C_REV_ID, C_SUBSYSTEM_ID, C_SUBSYSTEM_VENDOR_ID, C_MAX_LAT, C_MIN_GNT, respectively.

Table 5-4: Host Bridge Device Number Register

Bits Access Reset Value Description

0-27 Read Only 0x0000000 Set to zero.

28-31 Read/Write 0x0 Defines the device number of the OPB PCI Bridge when configured as Host Bridge

Figure 5-1: PCI Configuration Header

Base Address Register 0BIST

Base Address Register 1Base Address Register 2Base Address Register 3Base Address Register 4Base Address Register 5CardBus CIS Pointer

Class CodeStatusDevice ID Vendor ID

Revision IDCommand

Header Type Line SizeLat. Timer

Subsystem Vendor ID

User Configuration Begins

Capabilities Pointer

Subsystem ID

Min_Gnt Interrupt Pin Interrupt LineReserved

Reserved

Max_Lat

Expansion ROM Base Address

00h31 16 15 0

04h08h0Ch10h14h18h1Ch20h24h28h2Ch30h

40h

34h

38h3Ch

UG241_5-1_041806




The Header Type is a fixed byte of all zeros. Cardbus CIS Pointer is all zeros. The Capabilities Pointer is not enabled. The Interrupt Pin register is 0x01. BAR3, BAR4 and BAR5 are not supported.

Command/Status, Latency Timer, and at least one BAR register must be set by the host bridge. The number of BARs (0-2) is set by the OPB PCI Bridge parameter C_PCIBAR_NUM. Unused BARs do not need to be set.

Table 5-5 defines the content of the Command Status Register.

Table 5-5: Command Status Register (CSR)

Function Bit Position Reset Value

I/O Access Enable 0

Memory Access Enable 1

Bus Master Enable 2

Special Cycles 3 0

Memory Write/Invalidate Supported 4 0

VGA Palette Snoop Enable 5 0

Report Parity Errors 6

Reserved 7 0

SERR Enable 8

Fast Back to Back Enable 9 0

Interrupt Disable 10

Reserved 11-15 00000

Reserved 16-18 000

Interrupt Status 19

Capabilities List 20

66 MHz Capable 21

Reserved 22 0

Fast Back to Back Capable 23 0

Data Parity Error Detected 24

Device Select Timing 25-26

Signaled Target Abort 27

Received Target Abort 28

Received Master Abort 29

Signaled System Error 30

Detected Parity Error 31



OPB PCI Bridge Configuration GenericsR

OPB PCI Bridge Configuration GenericsThe OPB PCI Bridge is configured with host bridge configuration functionality by setting C_INCLUDE_PCI_CONFIG and C_INCLUDE_OPB_MST2PCI_TARG to 1.

The C_INCLUDE_DEVNUM_REG is used to include the Host Bridge Device Number register. When the HBDN register is not used, the C_BRIDGE_IDSEL_ADDRESS_BIT is used in the generation of IDSEL.

SignalsThe following signals are used in the configuration interface between the IPIF-v3 Bridge and the v3.0 core. These signals are used in conjunction with other signals used for target data transfer.

• CFG_HIT indicates that the v3.0 recognizes that it is the target of a current PCI configuration transaction.

• CFG_VLD indicates that a valid PCI configuration address is on the ADIO bus. Since the v3.0 does not support configuration burst transactions, the latched address present on the ADDR[31:0] bus can be used. The CFG_VLD signal is asserted for a single cycle, coincident with ADDR_VLD.

• C_READY indicates that it is ready to transfer data, and can be used to insert wait states during the first data phase of a transaction. With C_TERM, C_READY is also used to signal different types of target termination for configuration accesses. C_READY is tied high.

• C_TERM indicates that data transfer should cease. It is also used with C_READY to signal different types of target termination for configuration accesses. C_TERM is tied high.

Bus HierarchyThe host bridge, or North Bridge, bridges a host processor bus and the PCI Bus. The CPU for the Host/PCI bridge is either the PPC405 or the MicroBlaze. The PPC405 connects to the OPB PCI Bridge through its interface to the Processor Local Bus (PLB), which connects to the OPB using the PLB2OPB and OPB2PLB Bridges. MicroBlaze connects directly to the OPB.

The PCI specification defines memory, I/O, and configuration space. The PPC405 and MicroBlaze CPUs do not have configuration space. The PPC405 and MicroBlaze use memory mapped I/O transactions. In host bridge configuration, the PPC405 uses memory mapped writes/reads to the Configuration Address Port in the OPB PCI Bridge, and these writes/reads are translated into transactions in the configuration space on the PCI bus.

The host bridge configuration process consists of two steps. The CPU writes the Configuration Address Port. The CPU next writes the Configuration Data Port register. These transactions occur on the OPB, and get translated to the PCI bus if an external PCI agent is configured. These two steps are repeated to write the fields in the Configuration Header. In addition to configuring the host bridge, these two steps are used to configure the Configuration Header(s) of external PCI agents.

The PCI bus hierarchy consists of buses, devices, and functions. A PCI device with one function is a single function device. A PCI device with more than one function is a multi-function device. A bit adjacent to the Header Type field in the Configuration Header defines whether a function is a single function or multi-function device. Single function devices are required to respond as function 0 when addressed in a Type 0 configuration




transaction. Every function is allocated 256 bytes in configuration space, the Configuration Header. A function is selected by the devices IDSEL and the Configuration Read or Configuration Write command indicated on CBE[3:0].

In Figure 5-2, the bus on the other side of the OPB PCI Bridge is PCI Bus 0. PCI-PCI Bridges are used to allow other functions in the PCI bus hierarchy. When two PCI buses are used, the one closest to the OPB PCI Bridge is referred to as the primary bus, and bus accessed through the PCI-PCI Bridge is referrred to as the secondary bus. A subordinate bus is the highest numbered PCI bus on the downstream side of either a host or PCI-PCI bridge. A PCI to ISA bridge is a South Bridge.

Figure 5-3 shows the implementation of the PCI bus hierarchy defined in Figure 5-2. This is based on the XAPP911 OPB PCI Reference Design. The design is used in the Xilinx ML310

Figure 5-2: Bus Hierarchy

CPU

PLB

OPB

PLB2OPBOPB2PLB

Bridges

Host/PCIBridge

UG241_5-2_040606

PCI/PCIBridgeUpstream

Dev 0 Dev NDownstream

Primary PCI

Secondary PCI

Dev 0 Dev N




and ML410 boards. The PLB2OPB and OPB2PLB Bridges, and the OPB PCI Bridge are in the Virtex-2P/Virtex-4 FPGA, along with other IP.

Type 0 and Type 1 Configuration TransactionsType 0 configuration transactions access the primary bus, and Type 1 configuration transactions access subordinate buses. The Bus Number/Subordinate Bus Number Register is used by the Host/PCI Bridge to determine the target bus number. If the target is a device on either Bus 0 or a subordinate bus, a configuration transaction is generated. If the target bus is Bus 0, the bridge indicates to devices on Bus 0 that the transaction is a Type 0 configuration transaction by setting AD[1:0] = 00 in the address phase. If the target bus is a subordinate bus, Bus 0 is still accessed since it is physically connected to the Host/PCI bridge. Since devices on Bus 0 are not targeted, a Type 1 configuration transaction is generated, with AD[1:0] set to 01.

If the target device is not on the primary bus, the Host/PCI Bridge converts the Configuration Data Port transaction on the OPB to a Type 1 configuration transaction on the PCI bus. Only devices on the downstream side of PCI-PCI bridges recognize Type 1 configuration transactions. These devices determine if the target bus is within its range of PCI buses. If the bus number is not within its range, the transaction is ignored. If the bus number is equal to its Bus Number, the transaction is re-transmitted as a Type 0 transaction. If the bus number is not equal to its bus number but less than or equal to the Subordinate Bus Number, the transaction is re-transmitted as a Type 1 transaction.

Accessing one of the PCI function’s Configuration Header involves writing the target bus number, device number, function number, doubleword number to the Configuration Address Port, and setting CAP[24] to 1 to set the Enable bit. Then the PPC405 or MicroBlaze reads or writes to the Configuration Data Port. In response, the Host/PCI Bridge converts the PPC read/write access to the Configuration Data Port on the OPB to a Type 0 configuration transaction on the PCI bus.

Figure 5-3: PCI Board

5.0v PCI Slot

5.0v PCI Slot

5.0v PCI Slot

5.0v PCI Slot

PCI_P_AD23

PCI to PCIBridge

ALiSouthbridge

Intel 10/100Ethernet NIC

5.0v PCI Slot

UG241_5-3_040606




The format for Type 0 and Type 1 configuration transactions is given in Figure 5-4.

When the OPB PCI Bridge is configured as a host bridge, its v3.0 Configuration Header must be configured first. The minimum that must be set is the Bus Master Enable bit in the Command register and the Latency Timer register. Stated another way, at start up, the v3.0 core has the capability to configure only itself. It cannot be used to configure other agents until the Bus Master Enable bit is set in the Command register and the Latency Timer register is set to avoid timeouts. If the v3.0 core Latency Timer remains at the default 0 value, configuration writes to PCI devices do not complete, and configuration reads of PCI devices terminate due to the Latency Timer expiration. Configuration reads of PCI devices with the Latency Timer set to default 0 return 0xFFFFFFFF.

IDSEL GenerationIDSEL is the chip select for a PCI device in a configuration cycle. There are several methods to generate IDSEL. The source for IDSEL can be the driver of the IDSEL signal on the PCI bus, or it can be one of the PCI bus AD address bits. Internally, the v3.0 is enabled by IDSEL_int, which is driven by these two sources. When the OPB PCI bridge is not configured with host bridge configuration functionality, the v3.0 IDSEL_int is connected to the IDSEL port on the PCI bus. When the OPB PCI bridge is configured with host bridge configuration functionality, the v3.0 IDSEL_int is connected internally to a PCI bus AD signal, and the IDSEL port of the OPB PCI bridge is not used. The connection of the AD signal to IDSEL_int is discussed below.

IDSEL only has meaning for Type 0 configuration transactions. There are separate IDSEL for each PCI device on the secondary bus. The PCI device that samples its IDSEL asserted is the targeted device. If the OPB PCI Bridge’s device decoder determines there are no devices in the target device position on its secondary bus, the access is ignored. The transaction results in a Master Abort since no target asserts DEVSEL_N.

Table 5-6: Example IDSEL Addresses

Figure 5-4: Format of Type 0 and Type 1 Configuration Transactions

0

0

1

1 2 7 10 11 31 8

Type 0 Configuration Format

UG241_5-4_071706

Reserved Func No.

DW Number

0

0

1

1 2 7 10 11 15 16 23 24 31 8

Type 1 Configuration Format

Reserved Func No.

Device No.

Bus No.

DW Number

Device IDSEL Address

South Bridge (Ali M1535D+) AD17,18,19,26,27,31

Intel EMAC (GD82559) AD23

TI Bridge (TI2250) AD25

3.3V PCI Slot 3 (S2 Board) AD22

3.3V PCI Slot 5 (Empty) AD21




Note: Section 3.7.4. of the PCI Local Bus Specification states that the method used to drive the IDSEL signals is left to the discretion of the host bridge designer. The PCI bus AD[31:11] signals are not used in the address phase of Type 0 configuration transactions. As shown in Figure 5-5, this allows these pins to be used to select IDSEL.

Table 5-6 shows example IDSEL address used on a Xilinx board.

Table 5-7 shows the address value to used for values of C_BRIDGE_IDSEL_ADDR_BIT. This example is to address the Command Status register, which is located at offset 0x04. In this table, bits [2:3] determine the device and function number. As an example, if C_BRIDGE_IDSEL_ADDR_BIT = 24, the configuration address port to use is 0x04400080, with 0x40 translating to 0b00100000 for the 5 bit device and 3 bit function fields.



Table 5-7: Configuration Address Port address for IDSEL

C_BRIDGE_IDSEL_ADDR_BIT Configuration Address Port

16 0x04000080

17 0x04080080

18 0x04100080

19 0x04180080

20 0x04200080

21 0x04280080

22 0x04300080

23 0x04380080

24 0x04400080

25 0x04480080

26 0x04500080

27 0x04580080

28 0x04600080

29 0x04680080

30 0x04700080

31 0x04780080

Device IDSEL Address




Internally, the OPB PCI Bridge decodes the target device number in the Configuration Address Port and sets one of AD[31:11] to 1. Each of the address lines is connected to the IDSEL input of separate PCI devices as shown in Table 5-6. The AD assignments to IDSEL_int in Figure 5-5 are based on the assignments used in Figure 5-3. Only a single IDSEL signal may be asserted during the address phase of a configuration transaction. Conventionally, IDSEL of device 0 is connected to AD[16], IDSEL of device 1 is connected to AD[17], and so on. This allows for sixteen devices to reside on the PCI Bus.

The source for IDSEL is from the driver of IDSEL pin on the PCI bus or an AD line. Figure 5-6 shows how parameters on the OPB PCI Bridge define the source of IDSEL. If the OPB PCI bridge has host bridge configuration functionality and C_INCLUDE_DEVNUM_REG = 0, IDSEL_I of the v3.0 core is connected internally to the AD bit specified by C_BRIDGE_IDSEL_ADDR_BIT.

If C_INCLUDE _DEVNUM_REG = 1, C_BRIDGE_IDSEL_ADDR_BIT is not used. HBDN[28:31] is translated to select the address line routed to IDSEL_I. The address used is calculated using

IDSEL_I <= AD_IO_out(16 + conv_integer(HBDN))

C_NUM_IDSEL specifies the number of PCI agents configured on the PCI bus. C_NUM_IDSEL is the number of IDSEL lines that are decoded and assigned to address lines AD[31:16]. Each device on the bus must have its IDSEL line connected to the PCI AD bus.

In practice, because of loading, the maximum number of devices on a PCI is 10. Due to the extra loading on the AD bus by the IDSEL pins, the IDSEL pin is usually resistively coupled to the AD bus. One exception in the PCI specification is if the input pin capacitance of the IDSEL pin of the agent is 8 pF or less, direct coupling of the AD bus to the IDSEL pin is allowed.

If a resistor is used, the signal driving the IDSEL pin may take a long time to reach a valid logic level. Host bridges may solve the timing problem by using address stepping to drive the address, but not assert FRAME_N, for one or more clock cycles. This allows the IDSEL pin to reach a valid logic level prior to sampling. Address stepping is not supported in the OPB PCI Bridge.

Figure 5-5: IDSEL Generation Using AD lines

CPU

OPB PLB2OPB and OPB2PLB bridges not shown

Host/PCIBridge

UG241_5-5_040606

Device 0

IDSEL

AD[31:0]

PCI

Device 0

IDSEL

AD[16] AD[17]




Configuration TransactionsThis section begins with descriptions of configuration reads and configuration writes on the PCI bus. This is followed by detailed waveforms using both OPB and PCI bus signals in configuration.

Figure 5-7 shows the timing of a configuration read. In the first clock cycle, the OPB PCI Bridge drives FRAME_N low to initiate the transaction.The address contains a Type 1 configuration transaction with AD[1:0] = 01, and the DW, function number, device number, and bus number are output AD[31:2]. A 1010 for a Configuration read is output CBE[3:0]. The OPB PCI Bridge asserts IRDY_N to indicate it is ready to receive data. The AD bus has a turnaround cycle in clock cycle 3, after which the target device provides the data to be read. The target asserts TRDY_N and DEVSEL_N in clock cycle 3 to claim the transaction.

Figure 5-8 shows the timing of a configuration write. In the first clock cycle, the OPB PCI Bridge drives FRAME_N low to initiate the transaction. The address contains a Type 1 configuration transaction with AD[1:0] = 01, and the DW, function number, device number, and bus number are output AD[31:2]. A 1011 for a Configuration read is output CBE[3:0]. The OPB PCI Bridge asserts IRDY_N to indicate that write data is available on AD[31:0]. The target asserts TRDY_N and DEVSEL_N in clock cycle 2 to claim the transaction.

Figure 5-6: Defining the Source for IDSEL

Host Bridge Device Number

C_INCLUDE_PCI_CONFIGC_INCLUDE_OPB_MST2PCI_TARG

C_INCLUDE_DEVNUM_REG

IDSEL V3

IDSEL_I

C_BRIDGE_IDSELADDRESS_BIT

UG241_5-6_040606

Figure 5-7: Configuration Read

0ns 20ns 40ns 60ns 80ns 100ns

CLK0

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_N

Address Data

1010

UG241_5-7_040606




Figure 5-9 is a write to the Configuration Address Port (CAP) . The location is C_BASEADDR + 0x10C, so OPB_ABus = 0x1000010C. The value written to OPB_DBus is 0x04480080. With byte swapping, this value is 0x80004804. Refer to Table 5-1 for the definition of the bit fields of the Configuration Address Port, which defines the bus, device, and function number, as well as the offset of the doubleword within the address space. CAP[0:7] = 0x04 specifies the Command/Status Register within the Configuration Header, since the CSR is located at offset 04. CAP[8:15] = 0x48 defines the Device and Function number. The device number is defined as CAP[8:12] = 0b01001 and the function number as CAP[13:15] = 0b000.

CAP[8:12] = 0b01001 indicates that the device number is 10. Since device number 0 uses AD[16], C_BRIDGE_IDSEL_ADDRESS_BIT = 25 is use to specify device number 9. This matches IDSEL = 0x0040, or 0b0000000001000000. The tenth device is selected.

Writing to the Configuration Address Port does not produce activity on the PCI bus.

Figure 5-8: Configuration Write

0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns

CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_N

IDSELUG241_5-8_040606




Figure 5-10 is a write to the Configuration Data Port, located at C_BASEADDR + 0x110, which is 0x10000110. The data written on OPB_DBus is 0xFFFFFFFF with OPB_xferAck asserted. In this case, the 0xFFFFFFFF is written to the Command Status Register (CSR) to illustrate the effect on the contents of the CSR. The PCI bus transactions are displayed in the bottom half of the figure.

When FRAME_N is asserted, the address 0x02000004 is driven on AD[31:0]. This is the Type 0 configuration transaction defined in Figure 5-4. In 0x02000004, the 02 activates AD[25], which is the IDSEL defined by C_BRIDGE_IDSEL_ADDRESS_BIT. The 04 identifies the doubleword offset for the Command Status Register in the Configuration Header. The 0xB on CBE[3:0] indicates a configuration write. The data on AD[31:0] is 0xFFFFFFFF when IRDY_N is asserted, and is written one clock cycle later when TRDY_N is asserted.

In CSR[39:0], CSR[39:32] defines the transaction status and CSR[31:0] is the status and command registers. The Command Status register contains 0x00020546 when the transaction is complete, even after 0xFFFFFFFF is written. As seen in Table 5-5, some bits are reserved to 0. The 0546 enables Memory space, Bus Master, Parity Errors, SERR, and disables interrupts.

Figure 5-9: OPB Write to Configuration Address Port (Command Status Register)

0002000000

C_BASEADDR

C_NUM_IDSEL

C_BRIDGE_IDSEL_ADDR_BIT

OPB_CLK

OPB_ABus

OPB_DBus

OPB_RNW

OPB_xferAck

OPB_select

PCLK

ADIO

IDSEL

BUSNUM

config_busnum_reg

nfig_addr_port_regd

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

CSR

IDSEL_int

10000000

16

25

1000010C

04480080

00000000

FFFFFFFF

8000 0040

00

00000000

00000000 80004804

FFFFFFFF

F

UG241_5-9_04060




Figure 5-11 is a write to the Configuration Address Port, similar to that in Figure 5-9, except the content on OPB_DBus. The OPB_DBus = 0x0C480080 addresses the same Configuration Header, but the 0x0C offset is to the Latency Timer double word rather than the Command Status register.

Figure 5-10: OPB Write to Configuration Data Port (Command Status Register)

UG241_5-10_040706

OPB_CLK

OPB_ABus

OPB_DBus

OPB_RNW

OPB_xferAck

OPB_select

CFG_VLD

CFG_HIT

IDSEL_INT

CFG_self

PCLK

ADIO

config_addr_port_regd

IDSEL

BUSNUM

config_busnum_reg

IDSEL_self

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

CSR

10000110 00000000

FFFFFFFF 00000000

FFFFFFFF 02000004 FFFFFFFF FFFFFFFF FFFFFFFF

80004804

0040

00

00000000

FFFFFFFF

02000000 02000004

FFFFFFFF FFFFFFFF

F 0 B 0 F

0002000000

2B02000000

0002000546




Figure 5-12 is a write to the Configuration Data Port. The OPB_DBus = 0xFFFFFFFF is written with OPB_xferAck for the Latency Timer. The AD[31:0] address with FRAME_N asserted is 0x0200000C. The 0xB on CBE[3:0] indicates a configuration write. The data is transferred when DEVSEL_N and TRDY_N are asserted.

Figure 5-11: OPB Write to Configuration Address Port (Latency Timer)

OPB_CLK

OPB_ABus

OPB_DBus

OPB_RNW

OPB_xferAck

OPB_select

CFG_VLD

CFG_HIT

IDSEL_INT

CFG_self

PCLK

ADIO


IDSEL

000000001000010C

00000000

0C480080

00000000

FFFFFFFF

80004804 8000480C

0040

UG241_5-11_040706




Figure 5-13 is an OPB read of the Configuration Data Port to verify the content of the Latency timer. This occurs following the write to the CDP of the 0xFF into the Latency Timer in the previous figure. Since the Configuration Address Port contents points to the Latency Timer doubleword, it does not need to be re-written. In the read transaction, the PCI bus transactions occur before the OPB transactions. CBE[3:0] = 0xA indicates a read command. The OPB_DBus 0x00FF0000 results are shown when OPB_xferAck is high.

The next step is the OPB write to the Configuration Address Port to address PCI BAR 0, located in the same Configuration Header, with an offset = 0x10. As with the previous writes to the Configuration, this operation is followed by a write to the Configuration Data Port. If Bar 1 or Bar 2 are used, these steps need to be repeated.

Self Configuration of Host/PCI Bridge v3.0

As illustrated in the previous section, the first step in configuration is to configure the v3.0 in the host OPB PCI Bridge. This section provides details of this process. The IDSEL signal routed to IDSEL_I on the v3.0 is asserted during the address phase of the transaction, using the direct coupling method for IDSEL generation. When the IPIF-v3 bridge drives an address onto the ADIO bus during M_ADDR_N assertion, the bit in the upper word of the address asserts IDSEL_I.

Figure 5-12: OPB Write to Configuration Data Port (Latency Timer)

OPB_CLK

OPB_ABus

OPB_DBus

OPB_RNW

OPB_xferAck

OPB_select

CFG_VLD

CFG_HIT

IDSEL_INT

CFG_self

PCLK

ADIO


IDSEL

BUSNUM

config_busnum_reg

IDSEL_self

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

10000110 00000000

FFFFFFFF 00000000

FFFFFFFF 0200000C FFFFFFFF FFFFFFFF

8000480C

0040

00

00000000

FFFFFFFF

00000000 0200000C

FFFFFFFF

F 0 B 0 F

FFFFFFFF

UG241_5-12_040706




CFG_SELF forces the value of the bus master enable bit of the command register. This allows the interface to generate configuration transactions as a bus master even after the bus master enable bit is cleared after a system reset.

The CFG_SELF signal also affects the internal data path, indicating to the v3.0 that data is transferred over the ADIO bus. CFG_SELF is asserted during self configuration transactions, even after the bus master enable bit has been set.

Figure 5-14 shows the waveforms for the self configuration write. The v3.0 is writing to its command and status register. IDSEL_I is sampled during the address phase. When FRAME_N is asserted, CBE[3:0] = 0xB, indicating a configuration write. A self-configuration cycle is signaled by CFG_SELF no later than one cycle before REQUEST (REQ_O) is asserted. CFG_SELF signal remains asserted until the transaction is complete,

Figure 5-13: OPB Read of Configuration Data Port (Latency Timer)

OPB_CLK

OPB_ABus

OPB_DBus

OPB_RNW

OPB_xferAck

OPB_select

CFG_VLD

CFG_HIT

IDSEL_INT

CFG_sel

PCLK

ADIO


IDSEL

BUSNUM

config_busnum_reg

IDSEL_self

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

FFFFFFFF 0200000C

FFFFFFFF 0200000C

FFFFFFFF

0000FF00

FFFFFFFF FFFFFFFF

FFFFFFFF 0200000C FFFFFFFF 0000FF00 FFFFFFFF

0040

00

00000000

FFFFFFFF

F 0 A 0 F

8000480C

UG241_5-13_040706

00000000 10000110

00000000 00000000

00000000




which is signalled by the de-assertion of M_DATA. The address on ADIO = 0x02000004 is valid during the assertion of M_ADDR_N.

Configuring Other AgentsAfter the host bridge is configured and enabled using self configuration cycles, it can configure other agents on the PCI Bus. The steps for generating configuration cycles are similar to the steps for generating other initiator transactions. The principle task is setting up the bus, device, and function numbers correctly in terms of the C_BRIDGE_IDSEL_ADDRESS_BIT generic and the addresses used in the writes to the Configuration Address Port. In the application note XAPP911 Reference Design: OPB PCI, the ML310 board and Avnet Spartan-3 Evaluation boards are used as a configuration example which does this setup.

Figure 5-14: Self Configuration Writes of v3.0 Core

10000110OPB_ABus

OPB_DBus

OPB_RNW

OPB_xferAck

OPB_select

PCLK

ADIO


IDSEL

BUSNUM

config_busnum_reg

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

CSR

REQ_O

GNT_I

IDSEL_self

CFG_self

IDSEL_INT

CFG_VLD

CFG_HIT

m_data

m_addr_n

m_src_en

m_data_vld

0002000000 0002000546

FFFFFFFF 02000004

80004804

0040

00

00000000

FFFFFFFFFFFFFFFF

FFFFFFFF

F 0 B 0 F 0FFFFFFFF

02000004FFFFFFFF

FFFFFFFF

FFFFFFFF

FFFFFFFF

FFFFFFFF

FFFFFFFF

00000000

00000000

00000000 1000011010000110

FFFFFFFF FFFFFFFF

02000004

00000000 10000110

00000000

UG241_5-14_040706

02000000

02000004

02000546




In the reference design example, the OPB PCI Bridge in the Xilinx Virtex based FPGA mother board interfaces to an OPB PCI Bridge in the XC3S1500 FPGA on the Avnet (1) Spartan-3 1500 Evaluation Board using the PCI slots. The OPB PCI in the 3S1500 is configured using Configuration Writes from the OPB PCI in the mother board.

Verifying the ConfigurationAfter downloading a design, the following procedure configures the OPB PCI Bridge, and verifies that the OPB PCI Bridge is configured correctly.

1. Configure the v3.0 Command Register, Latency Timer, and BAR(s).

2. Read the configuration header.

3. Configure the Command Register, Latency Timer, and BAR(s) of the other devices in the system.

4. Read the configuration headers of the other devices in the system.

5. Do a memory read of one of the IPIF BARs.

6. Do a memory write of one of the IPIF BARs.

This verification is done using either Xilinx Microprocessor Debugger (XMD) and/or the software projects discussed in Chapter 13. Text files of the XMD commands are provided in the XMD_command directory in the XAPP911 Reference Design: OPB PCI .

1. Invoke XMD.

The XMD commands below write to the Configuration Address Port and Configuration Data Port to write the Configuration Header. The Command/Status Register, Latency Timer, and Base Address Registers are written and read.

Figure 5-3 shows the device and function numbers for the example below. In the earlier examples given in this chapter, C_BASEADDR = 0x10000000. In this example, C_BASEADDR = 0x3C000000.

Start by reading the content of the Configuration Address Port.

mrd 0x3C00010C 1

Write 0x04400080 to the Configuration Address Port. The 0080 enables the Configuration Space mapping and addresses Bus Number 0. The 0440 addresses the Command Status Register and Device Number 8. Below, C_BRIDGE_IDSEL_ADDRESS_BIT = 24.

mwr 0x3C00010C 0x04400080

Write the Command Status register. Writing 0xFFFFFFFF to the Command Status register illustrates that the contents of the CSR includes a number of reserved and unsupported bits.

mwr 0x3C000110 0x86002002

Read the contents of the Command Status register. Table 5-8 and Table 5-9 provide expected read results, adjusted for byte swapping, for several types of reads.

mrd 0x3C000110 1

Read the Class Code and Revision ID, located at offset 08. This operation starts with a write to the Configuration Address Port.

1. Memec was acquired by Avnet in 2005.



Verifying the ConfigurationR

mwr 0x3C00010C 0x08400080

mrd 0x3C000110 1

Write 0xFF to the Latency Timer by writing to the Configuration Address Port which addresses the Latency Timer.

mwr 0x3C00010C 0x0C400080

mwr 0x3C000110 0x00FF0000

Read the Latency Timer.

mrd 0x3C000110 1

The next three write CAP/CDP pairs write BAR0, BAR1, and BAR2. The offsets in the Configuration Header are 10, 14, and 18.

mwr 0x3C00010C 0x10400080

mwr 0x3C000110 0x00000000

mrd 0x3C000110 1

mwr 0x3C00010C 0x14400080

mwr 0x3C000110 0x0080FFFF

mrd 0x3C000110 1

mwr 0x3C00010C 0x18400080

mwr 0x3C000110 0x0000105F

mrd 0x3C000110 1

Read the Subsystem ID and Subsystem Vendor ID.

mwr 0x3C00010C 0x2C400080

mrd 0x3C000110 1

The commands below configure the OPB PCI Bridge on the secondary bus from the OPB PCI Host Bridge in the Virtex-2P/Virtex-4. The same commands as above are used, except the device number is 30.

mwr 0x3C00010C 0x04300080

mwr 0x3C000110 0x86002002

mrd 0x3C000110 1

mwr 0x3C00010C 0x0C300080

mwr 0x3C000110 0x00FF0000

mrd 0x3C000110 1

mwr 0x3C00010C 0x10300080

mwr 0x3C000110 0x00000070

mrd 0x3C000110 1

mwr 0x3C00010C 0x14300080

mwr 0x3C000110 0x00000050




mrd 0x3C000110 1

mwr 0x3C00010C 0x18300080

mwr 0x3C00010C 0x0000004F

mrd 0x3C000110 1

Table 5-8 and Table 5-9 show the results for configuring the v3.0 core configuration header in the OPB PCI Bridge by both OPB-side configuration transactions and by PCI host bridge configuration from the PCI-side. This example assumes all PCI BARs are designated memory space, which is the only allowed PCIBAR memory type. The OPB-side configuration of the v3.0 core enables all functionality in the Command Status register and sets the Latency Timer to maximum count for any data value written to the registers.

Table 5-9 shows the content of the Latency Timer after self configuration and configuration by a host bridge.

Configuring OPB PCI Bridge from PCI SideIf the OPB PCI Bridge is not configured as a host bridge, the v3.0 core in the OPB PCI Bridge must be configured from the PCI side. The Configuration Status Register, Latency Timer, and at least one Base Address Register (BAR) must be configured. C_INCLUDE_PCI_CONFIG = 0 specifies that the OPB PCI Bridge is not configured as a host bridge.

Table 5-8: Command Register Reads

Data WrittenCommand Register

By Host Bridge By Self Configuration

0x0000 0x0000 0x4605

0x0100 0x0000 0x4605

0x0200 0x0200 0x4605

0x0300 0x0200 0x4605

0x0400 0x0400 0x4605

0x0500 0x0400 0x4605

0x8600 0x0600 0x4605

0x8700 0x0600 0x4605

0xFFFF 0x4605 0x4605

Table 5-9: Latency Timer Reads

Data Written

Latency Timer

By Host BridgeBy Self

Configuration

0x00 0x00 0xFF

0x01 0x01 0xFF

0xFF 0xFF 0xFF



Configuring OPB PCI Bridge from PCI SideR

Figure 5-15 shows a PCI initiator writing the Command Status register. IDSEL is asserted as a chip select for a configuration transaction. When FRAME_N is asserted, the address on AD[31:0] is 0x00000004, which is the address for the Command Status register. CBE[3:0] = 0xB to specify a configuration write. In the next clock cycle, the host initiator writes 0xFFFFFFFF data to AD[31:0] and asserts IRDY_N. The v3.0 core indicates that it recognizes this as a configuration cycle by asserting CFG_VLD and CFG_HIT. Since this is not a self configuration cycle, CFG_self is 0. The OPB PCI asserts DEVSEL_N claiming the transaction, and one clock later the write transfer occurs with TRDY_N and STOP_N asserted. One clock cycle after the transaction ends, CSR[31:0] = 0x02000546. In a four byte PCI double word, byte swapping is done by B3 -> B0, B2-> B1, B1-> B2, B0 -> B3.

Figure 5-16 shows an initiator reading the Command Status Register. In this case, the read follows the write described in Figure 5-15. IDSEL is asserted. When FRAME_N is asserted, AD[31:0] = 0x00000004 to address the CSR, and CBE[3:0] = 0xA to specify a configuration read. The initiator indicates that it is ready to read data by asserting IRDY_N. The v3.0

Figure 5-15: Writing Command Status Register from PCI Bus

C_INCLUDE_PCI_CONFIG

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

IDSEL

s_term

s_wrdn

s_data_vl

ADIO

s_cbe

IDSEL_int

CFG_self

CFG_HIT

CFG_VLD

CSR

0

00000004 FFFFFFFF FFFFFFFF

F B 0 F

FFFFFFFF

FFFFFFFF 00000004 FFFFFFFF FFFFFFFF

F B 0 F

0002000000 2B02000000 0002000546

UG241_5-15_040706




asserts CFG_VLD and CFG_HIT. The CSR[31:0] = 0x02000546 is output AD[31:0] when TRDY_N and STOP_N are asserted.

Figure 5-17 shows the initiator writing the Latency Timer. The address AD[31:0] = 0x0000000C and CBE[3:0] = 0xB is written and FRAME_N is asserted. The data written is 0xFFFFFFFF when IRDY_N is asserted. The transfer occurs when DEVSEL_N, TDRY_N, and STOP_N are asserted.

Figure 5-18 shows the initiator reading the Latency Timer. The address AD[31:0] = 0x0000000C and CBE[3:0] = 0xA is written and FRAME_N is asserted. IRDY_N is asserted

Figure 5-16: Reading Command Status Register from PCI Bus

Figure 5-17: Writing Latency Timer from PCI Bus

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

IDSEL

s_term

s_wrdn

s_data_vld

ADIO

s_cbe

IDSEL_int

CFG_self

CFG_HIT

CFG_VLD

CSR

00000004 FFFFFFFF

FFFFFFFF

FFFFFFFF 02000546

F A 0

FFFFFFFF 00000004 FFFFFFFF 02000546

F A 0

0002000546

2B02000546

FFFFFFFF

UG241_5-16_040706

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

FFFFFFFF

FFFFFFFF

FFFFFFFF

F B 0 F

0000000C

UG241_5-17_040706



Configuring OPB PCI Bridge from PCI SideR

to indicate that the initiator is ready to read the data. The transfer occurs with DEVSEL_N, TDRY_N, and STOP_N asserted, with 0x0000FF00 on AD[31:0].

Figure 5-19 shows the initiator writing BAR 0. The address AD[31:0] = 0x00000010 and CBE[3:0] = 0xB is written and FRAME_N is asserted. The data written is 0xFFFFFFFF with IRDY_N asserted. The transfer occurs with DEVSEL_N, TDRY_N, and STOP_N asserted.

Figure 5-20 shows the initiator reading BAR 0. The address AD[31:0] = 0x00000010 and CBE[3:0] = 0xA is written and FRAME_N is asserted. IRDY_N is asserted to indicate that the initiator is ready to read the data. The transfer occurs with DEVSEL_N, TDRY_N, and STOP_N asserted, with 0xFFFFFFFE on AD[31:0].

Figure 5-18: Read Latency Timer from PCI Bus

Figure 5-19: Writing Bar 0 from PCI Bus

Figure 5-20: Reading BAR 0 from PCI Bus

PCLK

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

AD

FFFFFFFF

0000000C FFFFFFFF FFFFFFFF 0000FF00

FFFFFFFF

F A 0

UG241_5-18_040706

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_NUG241_5-19_040706

FFFFFFFF

00000010 FFFFFFFF

FFFFFFFF

F B 0 F

AD

PCLK

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_NUG241_5-20_040706

FFFFFFFF

00000010 FFFFFFFF FFFFFFFF FFFFFFE8 FFFFFFFF

F A 0



R

Chapter 6

PCI to OPB Transactions

This chapter discusses PCI to OPB write and read transactions. These transactions involve the IPIF, IPIF-v3bridge, and v3.0 modules. The registers and generics used in PCI to OPB transactions are discussed. Block diagrams of the functional elements used in PCI to OPB transactions are provided, followed by a flow diagram of the modules used for PCI to OPB transactions. Write transactions are discussed first, followed by read transactions.

Signal waveforms of PCI write transactions are given, first as PCI Bus and OPB signal sets in isolation. This is followed by waveforms using an integrated set of signals from all three modules. This format is then followed for PCI to OPB read transactions.

In a PCI target, posted writes and prefetched reads are two methods to increase bandwidth. These techniques are discussed in the PCI Local Bus Specification. The use of FIFOs in PCI to OPB transactions is discussed.

Generics and RegistersThe C_INCLUDE_PCI_INT2OPB_SLV generic is set to 1 for PCI to OPB read and write transactions. The other types of generics for PCI to OPB transactions are address range, FIFO, and DMA generics. The number of address ranges, defined by C_PCIBAR_NUM, is from one to three. Each address range is defined by the following set of generics: C_PCIBAR_n, C_PCIBAR_LEN_n, C_PCIBAR2IPIFBAR_n, C_PCIBAR_ENDIAN_TRANSLATE_n, C_PCI_PREFETCH_n, and C_PCI_SPACETYPE_n, with n representing the number of the address range.

The PCI2IPIF FIFO is optionally used in PCI to OPB write transactions. The IPIF2PCI FIFO is optionally used in PCI to OPB read transactions. The C_IPIF2PCI_FIFO_ABUS_WIDTH generic defines the existence and depth of the IPIF2PCI FIFO. The C_PCI2IPIF_FIFO_ABUS_WIDTH defines the existence and depth of the PCI2IPIF FIFO. The useable depth is the FIFO depth minus 3.

Direct Memory Access (DMA) is done by a module in the IPIF. The generics defining DMA operation are C_DMA_CHANTYPE, C_DMA_BASEADDR, C_DMA_HIGHADDR, and C_DMA_LENGTH_WIDTH. Set C_DMA_CHAN_TYPE = 9 to exclude DMA functionality from the core. Set C_DMA_CHAN_TYPE = 0 to include simple DMA. Scatter Gather DMA is not supported in the OPB PCI Bridge. The C_DMA_LENGTH_WIDTH generic defines the number of bits in the length register.



Chapter 6: PCI to OPB TransactionsR

OPB PCI Bridge Functional DiagramsIn Figures 6-1 to 6-5, the block diagrams of the major modules used in PCI to OPB write transactions are given. These provide a reference for external and internal signals used.

Figure 6-1 is the top level pinout of the OPB PCI core. The OPB signals are on the left. The PCI signals are on the right. The OPB signals include signals for an OPB slave and OPB master. The OPB signals used are defined by the C_INCLUDE_OPB_MST2PCI_TARG and C_INCLUDE_PCI_INT2OPB_SLV generics.

Figure 6-1: OPB PCI Bridge

OPB_ABus[0:31] OPB_DBus[0:31]

PCI_ABUS[0:31] PCI_request PCI_busLock PCI_RNW PCI_BE PCI_seqAddr OPB_MGrant OPB_xferAck OPB_errAck OPB_retry OPB_timeout OPB_select OPB_RNW OPB_seqAddr OPB_BE PCI_xferAck PCI_errAck PCI_toutSup PCI_retry PCI_DBus_[0:31] IP2INTC_Irpt OPB_Clk OPB_Rst

PCBus

OPB

MasterSignals

SlaveSignals

AD[31:0] CBE[3:0]

PAR

FRAME_N

TRDY_N IRDY_N

STOP_N IDSEL

INTR_A

PERR_N SERR_N

REQ_N GNT_N

RST_N PCLK

INTR_A_INT REQ_N_toARB

FRAME_I IRDY_I

PCI_monitor[0:48]

RCLK

UG241_6-1_041206


OPB PCI v1.02a User GuideUG241 July 26, 2006 www.xilinx.com 87

OPB PCI Bridge Functional DiagramsR

Figure 6-2 shows the pinout for the v3.0 core. The PCI signals are on the right. Most of the signals on the left interface to the IPIF-v3 Bridge. For PCI to OPB writes and reads, the v3.0 target signals are used. PCI target signals use names with a S_* prefix. v3.0 initiator signals, which use names with a M_* prefix, are not used in PCI to OPB transactions.

Figure 6-2: v3.0 Connections

PC

I Bu

s

IPIF

-V3

Bri

dg

e

UG241_6-2_041206

FRAME_NTRDYQ_NIRDYQ_N

STOPQ_NDEVSELQ_N

ADDR[0:31]ADIO[0:31]CFG_VLDCFG_HITC_TERM

C_READYCFG_SELFBASE_HIT

ADDR_VLD

S_DATAS_TERM

S_READYS_ABORT

SWRDNS_SRC_EN

S_DATA_VLDS_CBE

PCI_CMDREQUEST

REQUESTHOLDCOMPLETE

M_WRDNM_READY

M_SRC_ENM_DATA_VLD

M_CBETIME_OUT

M_DATADR_BUS

M_ADDR_N

IDLEB_BUSY

BACKOFFINTR_N

PERRQ_NSERRQ_N

V3_read_request_abort_strbCSR[39:0]

SUB_DATARSTCLK

I_IDLEPCLKRCLK

REFRSTREFCLK

FRAME_NTRDYQ_NIRDYQ_NSTOPQ_NDEVSELQ_NADDR[0:31]ADIO[0:31]CFG_VLDCFG_HITC_TERMC_READYCFG_SELFBASE_HITADDR_VLD

S_DATAS_TERMS_READYS_ABORTS_WRDNS_SRC_ENS_DATA_VLDS_CBE

PCI_CMDREQUESTREQUESTHOLDCOMPLETEM_WRDNM_READYM_SRC_ENM_DATA_VLDM_CBETIME_OUTM_DATADR_BUSM_ADDR_N

IDLEB_BUSY

BACKOFFINTR_NPERRQ_NSERRQ_NKEEPOUTCSR[39:0]SUB_DATARSTCLKI_IDLEPCLKRCLKREFRSTREFCLK

AD_IO CBE_IO PAR_IO

FRAME_IO TRDY_IO IRDY_IO

STOP_IO DEVSEL_IO

IDSEL_I OE_INTA PERR_IO SERR_IO

REQ_O GNT_I RST_I

AD CBE PAR FRAME_N TRDY_N IRDY_N STOP_N DEVSEL_N IDSEL_int OE_INTA PERR_N SERR_N REQ_N GNT_I RST_N




The following target interface signals control target data transfer to and from the v3.0:

BASE_HIT[7:0]: v3.0 output indicates that one of the base address registers recognizes that it is the target of a current PCI transaction. This is the first indicator to the IPIF-v3 Bridge that a target transaction is about to begin.

ADIO[31:0]: Bidirectional bus used for data and address transfer to and from the v3.0.

ADDR[31:0]: v3.0 output is a registered PCI address which is valid in the cycle after ADDR_VLD is asserted, and remains valid through the entire transaction.

S_WRDN: v3.0 output indicates the direction of data transfer for the current target transaction. Logic high indicates that the IPIF-v3 Bridge is sinking data (i.e. target write). It is valid during the cycle BASE_HIT is asserted and is held through the transaction.

S_CBE[3:0]: A registered CBE delayed by one cycle. S_CBE indicates the PCI command and byte enables during a target transaction. This signal is used primarily for byte enable information, since the command is decoded and latched in PCI_CMD during the address phase of the transaction.

PCI_CMD[15:0]: v3.0 output is a decoded and latched version of the PCI command for the current bus transaction.

S_DATA_VLD: v3.0 output has two interpretations depending on the direction of data transfer. When the IPIF-v3 Bridge is sinking data (target writes), S_DATA_VLD indicates that the IPIF-v3 Bridge should capture valid data from the ADIO bus. When the IPIF-v3 Bridge is sourcing data (target reads), S_DATA_VLD indicates that a data phase has completed on the PCI Bus.

S_DATA: v3.0 output indicates that the target state machine is in the data transfer state.

ADDR_VLD: v3.0 output indicates that a valid PCI address is available on the ADIO bus. The assertion of ADDR_VLD does not mean that the IPIF-v3 Bridge is the selected target. The ADDR_VLD signal is asserted for a single cycle.

S_SRC_EN: v3.0 output is only used during target burst reads. It indicates to the IPIF-v3 Bridge that the data source which drives output data onto the ADIO bus must provide the next data. In most applications, this signals the IPIF-v3 Bridge to advance the data pointer for the data source providing the data.

CSR[39:0]: v3.0 output provides v3.0 status. The high eight bits provide status information for the current transfer. This status information is used primarily in target burst applications with non-prefetchable sources to determine if any associated address pointers must be “backed up”.

S_READY: Output from the IPIF-v3 Bridge indicates that it is ready to transfer data, and can be used to insert wait states during the first data phase of a transaction. With S_TERM, S_READY is also used to signal target terminations. S_READY cannot be used to insert wait states after the first data phase.

S_TERM: Output from the IPIF-v3 Bridge to stop the data transfer. S_TERM is also used with S_READY to signal target terminations.

S_ABORT: Output from the IPIF-v3 Bridge indicates that a serious (fatal) error condition has occurred and that the current transaction must stop.

The following signals are output by the target state machine in the v3.0. These states are defined in Appendix B of the PCI Local Bus Specification.

IDLE: v3.0 output indicates that the target state machine is in the idle state and that there is no activity on the PCI Bus.




B_BUSY: v3.0 output indicates that the target state machine has recognized the beginning of a PCI Bus transaction. The target state machine changes to the S_DATA state if it determines that it is the target of the transaction.

BACKOFF: v3.0 output indicates that the target state machine is waiting for a transaction to complete because the IPIF-v3 Bridge has asserted S_TERM.

In Figure 6-3, the IPIF-v3 Bridge interfaces to the v3.0 core on the right and to the OPB IPIF on the left. The interface to the OPB IPIF is to the IPIF Master Attachment module using the IP2Bus_Mst* and Bus2IP_Mst* signals, and to the IPIF Slave Attachment module using Bus2IP_* and IP2Bus_* signals. The interface to the v3.0 is to the v3.0 initiator signals M_*.

Figure 6-3: IPIF-v3 Bridge

IPIF_WrBurst_Imminent Inhibit_FaF_Writes

UG241_6-3_041206

Bus2IP_Clk Bus2IP_Reset Bus2IP_WrReq Bus2IP_RdReq Bus2IP_Burst Bus2IP_Addr[0:31] Bus2IP_Data[0:31] Bus2IP_BE[0:3]

IP2Bus_Retry IP2Bus_Addr[0:31] IP2Bus_Data[0:31] IP2Bus_RdAck IP2Bus_WrAck IP2Bus_Error IP2Bus_ToutSup IP2Bus_MstWrReq IP2Bus_MstRdReq IP2Bus_MstBurst IP2Bus_MstBusLock

IPIFBAR_RdCE_vector IPIFBAR_WrCE_vector IPIF_CE_vector IPIF_Override_Prefetch_vec_RdCE IPIF_Override_Prefetch_vec_WrCE Config_CE_vector Config_Addr_port_RdCE Config_Addr_port_WrCE Config_Data_port_RdCE Config_Data_port_WrCE IPIF_Inhibit_Xfer_RdCE IPIF_Inhibit_Xfer_WrCE IPIF_Mst_Addr_Def_RdCE IPIF_Mst_Addr_Def_WrCE IPIF_Mst_Rd_Addr_RdCE IPIF_Mst_Wr_Addr_RdCE PCI_Override_Prefetch_vec_RdCE PCI_Override_Prefetch_vec_WrCE

Bus2IP_MstRetry Bus2IP_MstTimeOut Bus2IP_MstWrAck Bus2IP_MstLastAck Bus2IP_IPMstTrans

IPIF_WrBurst_Imminent Inhibit_FaF_Writes FIFO2Bus_BE[0:31] DevNum

Bus2IP_Clk Bus2IP_Reset

Bus2IP_WrReq Bus2IP_RdReq

Bus2IP_Burst Bus2IP_Addr Bus2IP_Data

Bus2IP_BE

IP2Bus_Retry IP2Bus_Addr IP2Bus_Data

IP2Bus_RdAck IP2Bus_WrAck

IP2Bus_Error IP2Bus_ToutSup

IP2Bus_MstWrReq IP2Bus_MstRdReq

IP2Bus_MstBurst IP2Bus_MstBusLock

Bus2IP_MstRetry Bus2IP_MstTimeOut

Bus2IP_MstWrAck Bus2IP_MstLastAck Bus2IP_IPMstTrans

FIFO2Bus_BE DevNum

Bus2IP_RdCE(s)

OPB IPIF v3

Bus2IP_WrCE(s)

S_WRdN S_Data

S_SRC_EN S_Data_Vld

S_Term S_Ready

S_CBE

S_WRdN S_Data S_SRC_EN S_Data_Vld S_Term S_Ready S_CBE

IRDY_N SERRO_N PERRO_N Time_Out

INTR_N

M_Addr_N M_SRC_EN M_Data_Vld

M_Data M_Ready Complete Request

M_WRdN M_CBE

CFG_SELF

PCI_CMD_15_14 PCI_CMD_12_7_9

V3_RST V3_Clk

Base_Hit ADDR[0:31] ADIO[0:31]

IRDY_N SERRO_N PERRO_N Time_Out INTR_N

M_Addr_N M_SRC_EN M_Data_Vld M_Data M_Ready Complete Request M_WRdN M_CBE

CFG_SELF

V3_Rst V3_Clk

Base_Hit ADDR ADIO

Brdg_V3_Trans PCI_Init_Rd_SERR PCI_Init_Wr_SERR IPIF_Mst_RdWr_1

Brdg_V3




The lower left of the Figure 6-3 shows 18 register read and write clock enables generated by the OPB IPIF.

In Figure 6-4, the OPB IPIF interfaces to the IPIF-v3 Bridge on the right and to the OPB on the left. On the OPB side, the Mn_* signals are master signals, and the Sln_* signals are slave signals. On the OPB IPIF interface to the IPIF-v3 Bridge, the Bus2IP_* signals are outputs to the IPIF-v3 Bridge, and the IP2Bus are inputs from the IPIF-v3 Bridge.

Figure 6-4: OPB IPIF ConnectionsIP

IF-V

3 B

rid

ge

OPB_MnGrantOPB_xferAckOPB_errAckOPB_retryOPB_timeoutOPB_selectOPB_RNWOPB_seqAddrOPB_BE[0:3]OPB_ABus[0:31]OPB_DBus[0:31]

OPB_MnGrantOPB_xferAckOPB_errAck

OPB_retryOPB_timeout

OPB_selectOPB_RNW

OPB_seqAddrOPB_BE

OPB_ABusOPB_DBus

Sln_DBus[0:31]Sln_xferAckSln_toutSupSln_retry

PCI_DBus[0:31]PCI_xferAckPCI_toutSup

PCI_retry

Mn_ABus[0:31]Mn_RequestMn_BusLockMn_RNWMN_BE[0:31]Mn_seqAddr

PCI_ABusPCI_RequestPCI_BusLock

PCI_RNWPCI_BE

PCI_seqAddr

ResetOPB_ClkIP2INTC_Irpt

bus_rst_iOPB_Clk

IP2INTC_Irpt

IP2Bus[0:31]Bus2IPAddr[0:31]

Bus2IP_Data[0:31]Bus2IP_RNW

Bus2IP_CSBus2IP_CE

Bus2IP_RdCE

Bus2IP_BE[0:3]Bus2IP_WrReqBus2IP_RdReq

Bus2IP_IPMstTransBus2IP_Burst

IP2Bus_IntrEvent

Bus2IP_ClkBus2IP_Reset

RmtOPBmst2IP_WrBurst_imminentDMA2IP_WrImminent_n

IP2Bus_Data[0:31]IP2Bus_WrAckIP2Bus_RdAck

IP2Bus_RetryIP2Bus_Error

IPBus_ToutSupIP2Bus_PostedWrInh

IP2Bus_MstBEIP2Bus_MstWrReqIP2Bus_MstRdReq

IP2Bus_MstBurstIP2Bus_MstBusLock

IP2Bus_MstWrAckIP2Bus_MstRdAck

Bus2IP_MstRetryBus2IP2_MstError

Bus2IP_MstTimeOutBus2IP_MstLastAck

IP2BusBus2IPAddrBus2IP_DataBus2IP_RNWBus2IP_CSBus2IP_CEBus2IP_RdCE

Bus2IP_BEBus2IP_WrReqBus2IP_RdReqBus2IP_IPMstTransBus2IP_Burst

IP2Bus_IntrEvent


RmtOPBmst2IP_WrBurstDMA2IP_WrImminent_n

IP2Bus_Data_ByteswpdIP2Bus_WrAckIP2Bus_RdAckIP2Bus_RetryIP2Bus_ErrorIPBus_ToutSupInhibit_FaF_Writes

FIFO2Bus_BE_ByteswpdIP2Bus_MstWrReqIP2Bus_RdReqIP2Bus_MstBurstIP2Bus_MstBusLock

Bus2IP_MstWrAckBus2IP_MstRdAckBus2IP2_MstRetryBus2IP_MstErrorBus2IP_MstTimeoutBus2IP_MstLastAck

UG241_6-4_041206




In Figure 6-5, the PCI_INT2IPIF_SLV is a module in the IPIF-v3 Bridge, and consists of the ipif_mst_req_sm, ipif_addr_counter, pci2ipif_addr_translate, ipif_wr_ipmst_ipifretry_sm, pci_intrpt_addr_regs, and ip_master modules. This module contains the logic that translates PCI transactions to OPB transactions.

Figure 6-5: PCI_INT2IPIF_SLV Pinout

Set_S_Ready_strbRd_Addr_EQ_Wr_Addr_IPIF2PCI_FIFORd_pls1_eq_Wr_Rdside_IPIF2PCIWr_mnsTrg_It_Rd_mns3_IPIF2PCIData_N_Addr_RmtPCI2IPIFslv

Bus2IP_Clk

IP2Bus_WrAck_IPIF2PCI_fifo_ungtd

IP2Bus_MstRdReqIP2Bus_MstWrReqIP2Bus_MstBurstIP2Bus_MstBusLock

IP2Bus_RdAckIP2Bus_WrAckIP2Bus_Addr

PCI_Init_Rd_SERR_IPIF_Intrpt_strb_IPIFsidePCI_Init_Rd_SERR_IPIF_Intrpt_strb_IPIFside

Bus2IP_MstRetryBus2IP_MstErrorBus2IP_MstTimeOutBus2IP_MstLastAck

Basehit_vector_regd_PCIsideBasehit_active_PCIsideBasehit_active_gtdLoad_PCI_BE_for_IPIF_Rd

IPIF_WrBurst_ImminentBlock_RmtMst_OP_dueto_PCI_WrRetryPCI_Overdide_Prefetch_vectorRmt_IP_mst_rd_PCI_InProg_IPIFsideRmt_IP_mst_rd_PCI_InProg_PCIsideRmt_IP_mst_wr_PCI_InProg_IPIFsideRmt_IP_mst_wr_PCI_InProg_PCIsideRmt_IP_mst_init_rd_IPIF_InProg_IPIFsideSet_Rmt_PCI_init_rd_IPIF_InProg_PCIsideRmt_PCI_init_rd_IPIF_InProg_PCEsideRmt_PCI_init_wr_IPIF_InProg_IPIFsideSet_Rmt_PCI_init_wr_IPIF_InProg_PCIsideRmt_PCI_init_wr_IPIF_InProg_PCIsideRmt_PCI_init_rd_IPIF_InProg_PCIside_AD_oeIPIF2PCI_FIFO_Reset_IPmstIPIF2PCI_FIFO_Reset_IPmst_PCIsidePCI2IPIF_FIFO_Reset_IPmstPCI2IPIF_FIFO_Reset_IPmst_PCIside

Reset_IPIFside

V3IPIF

FIFO

Rd_Empty_PCI2IPIF_FIFOWr_eq_Rd_mns3_PCI2IPIF

Wr_En_PCI2IPIF_by_RmtPCIinitWr_ge_Rd_Plstrg_PCI2IPIF

PCI_CMD_15_14PCI_CMD_12_7_6INTR_N_strb_low

Reset_PCIside

V3_ClkSERRQ_NPERRQ_N

AddrV32IPIF_Addr

S_WRDNS_Data

S_CBE_regdS_Term

S_ReadyS_Data_Vld

UG241_6-5_041206




The IPIF2PCI FIFO is used in PCI to OPB read transactions. As shown in Figure 6-6, the IPIF2PCI FIFO module consists of the IPIF2PCI_FIFO_CNTL control, PF_DPRAM_SELECT dual port RAM, and ENDIAN_SWAP modules. The C_FIFO_ABUS_WIDTH generic determines the FIFO depth. The C_TRIG_PCI_DATA_XFER_OCC_LEVEL, C_TRIG_IPIF_READ_OCC_LEVEL, and C_INHIBIT_IPIF_READ_VAC_LEVEL generics control the functionality of the IPIF2PCI_FIFO_CNTL module.

The C_IPIFBAR_NUM, C_IPIF_ENDIAN_TRANSLATE_EN_n, C_PCIBAR_NUM, and C_PCI_ENDIAN_TRANSLATE_EN_n generics are used by the endian swap module to swap the order of the data and/or byte enables.

The PCI Initiator drives the Read Backup Strobe signals in the IPIF2PCI_FIFO_CNTL module.

Address TranslationThe address presented on the PCI bus is translated to the OPB address space by high-order bit substitution.

PCI to OPB Write TransactionsThis section discusses PCI single and burst write transactions to an OPB slave. In PCI to OPB transactions, the v3.0 core is a PCI target.

Figure 6-6: IPIF2PCI FIFO Functional Diagram

ENDIANSWAP

DS241_6-6_041206

IPIF_FIFO_CNTL

IPMASTER

PCIInitiator

WRITE_ABUSWR_ADVANCED_STRBWR_ABUS_GRAY_SYNCDFIFO_RESET_WR_CLK

WR_FULLWR_MNSTRG_LT_RE_MNS3WR_PLSVAC_LT_RD_MNS3

WR_CLK

WR_DATA

READ_ABUS

M_CBE

ADIO

DATA_N_ADDRADDR_TO_V3CORE[0:31]

PCI_CMD_REG[0:3]

READ_CLK

WR_GE_RD_PLSTRGRD_PLS1_EQ_WR_RDSIDE

RD_ADDR_EQ_WR_ADDR

RD_BACKUP1_STRBRD_BACKUP2_STRBRD_BACKUP3_STRB

PF_DPRAM_SELECTWR_RSTWR_CLKWR_ENABLEWR_REQ

WR_ADDRESS RD_ADDRESS

RD_RSTRD_CLK

RD_ENABLE

RD_DATA



PCI to OPB Write TransactionsR

Figure 6-7 provides the principle signals used in an PCI to OPB write operation.

In Figure 6-8, the initiator with a write transfer requirement requests ownership of the bus by asserting REQ_N (not shown). The arbiter grants access with GNT_N. Once GNT_N is received, the initiator waits until the bus is idle, as indicated by a high on the FRAME_N and IRDY_N pins.

On the first clock, the initiator drives the address on AD[31:0] and the command on CBE[3:0]. FRAME_N is asserted. Each target samples the address on AD[31:0], command on CBE[3:0], and FRAME_N to determine if it is the target.

In the second clock, the initiator asserts IRDY_N to indicate data is driven. FRAME_N is de-asserted to indicate that this is the last data written, i.e., that this is a single write transfer. The initiator drives the byte enables on CBE[3:0]. The addressed target asserts DEVSEL_N and TRDY_N to indicate that it is ready to accept the transaction. Data is written to the target when IRDY_N and TRDY_N are asserted. When the transaction is

Figure 6-7: PCI to OPB Write Flow

Figure 6-8: PCI Single Write of 3

OPBIPIF

OPB PCI

UG241_6-7_041206

IPIF- V3Bridge

Bus2IP_MstRetryBus2IP_MstError

Bus2IP_MstTimeOutBus2IP_MstWrAck

Bus2IP_MstLastAck

IP2Bus_MstWrReqIP2Bus_MstRdReqIP2Bus_MstBurst

IP2BusMstBusLock

V3

ADIOS_READYS_TERMS_CBE

ADCBE

FRAME_NTRDY_NIRDY_NSTOP_N

DEVSEL_NS_DATA_VALID

S_DATAS_WREN

Basehit_vector

PCI_ABUSPCI_DBUSPCI_RNW

PCI_REQUESTPCI_BE

PCI_SELECTPCI_xferAcEPCI_toutSup

PCI_RetryPCI_busLock

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_N


UG241_6-8_041206




complete, the initiator de-asserts IRDY_N and the target de-asserts TRDY_N and DEVSEL_N.

In Figure 6-9, the burst write transaction begins with signal transitions similar to that of a single write transaction. The initiator requests and gains access to an idle PCI bus. In the first clock cycle, the initiator asserts FRAME_N, and provides the address on AD[31:0] and the command on CBE[3:0]. In clock cycle 2, the initiator asserts IRDY_N and drives data on AD[31:0] and byte enables on CBE[3:0]. When FRAME_N is asserted, targets decode the address and command. The addressed target asserts DEVSEL_N and TRDY_N.

In clock cycle 3, the initiator and target both sample IRDY_N and TRDY_N asserted and the data transfer of the first written data occurs. Here the first difference with the single write transfer occurs. The initiator keeps FRAME_N asserted, indicating that it is not the last data written. The length of the burst write is determined by the duration FRAME_N is asserted. The initiator only writes the first address in a burst transaction. Each target contains an address counter which increments the start address provided on AD[31:0] by 4 to determine the address of the next DWORD.

If TRDY_N and IRDY_N are both asserted, the write burst of data occurs without wait states. If the initiator or target needs additional time to generate/receive data, IRDY_N and/or TRDY_N are de-asserted to insert wait states.

Figure 6-9: PCI Burst Write

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_N


ADDR DATA1 DATA2 DATA3

CMD

UG241_6-9_041206




The initiator indicates the last data of the burst by de-asserting FRAME_N. The end of the burst does not occur until IRDY_N and TRDY_N are de-asserted.

Figure 6-10 shows the OPB IPIF signals for PCI to OPB write operations. The master starts by asserting the IP2Bus_MstWrReq request signal. Each transfer is acknowledged by Bus2IP_MstWrAck. There is more than one acknowledge if the transaction is a burst. The burst size is 8. The acknowledge indicates that the data has reached its final destination. The last acknowledge is accompanied by Bus2IP_MstLastAck.

Figure 6-10: IPIF Single and Burst Transactions

valid valid

A1 A2 don’t care but usually will increment with each ack

L1 L2 don’t care

single read(write) burst read(write) (8 transfers per burst)

UG241_6-10_041206

Bus2IP_Clk

IP2Bus_MstRd(Wr)Req

IP2Bus_MstBurst

IP2Bus_MstBE

IP2Bus_MstBusLock

IP2Bus_Addr

IP2IP_Addr

Bus2IP_MstRd(Wr)Ack

Bus2IP_MstLastAck

Bus2IP_MstError

Bus2IP_MstRetry

Bus2IP_MstTimeOut

Annotation




Figure 6-11 shows the OPB signals for a single write transaction in a PCI to OPB write transaction. The OPB IPIF outputs an address on PCI_ABus and data on PCI_DBus. Since this is a write, PCI_RNW is output low. PCI_Select is output high. When address and data are valid, the data is written to the OPB Slave destination; the slave drives the PCI_XferAck.

Only one PCI to OPB write is can be done at a time. Write transactions are not queued in the bridge.

Figure 6-12 shows the OPB signals for a sequential write. This is similar to the single write with the difference that PCI_seqAddr is output high, and multiple address/data are written on PCI_ABus and PCI_DBus. The OPB does not directly support burst modes. The sequential address allows slaves to achieve burst-like response. The next transfer is to the next sequential address in the same direction. M_busLock must be asserted during sequential transactions.

Since all OPB address space is memory space, the PCI Memory Write is the only write command supported. The PCI I/O write command is ignored. The duration of FRAME_N determines whether the write operation is a burst or single. Byte enables are buffered with data on PCI initiator writes to a OPB slave. All memory write commands are posted, with error notification usually delayed until the PCI transaction has completed.

Dynamic byte enables are supported in burst writes to OPB slaves.

To realize maximum data throughput, a multiple of eight words must be transferred on the PCI bus. If a PCI initiator writes data that is not an integer multiple of eight words, the

Figure 6-11: OPB Single Write

Figure 6-12: OPB Sequential Write

UG241_6-11_041206

OPB_CLK

PCI_ABus[0:31]

PCI_DBus[0:31]

PCI_RNW

PCI_Select

PCI_xferAck

0ns 20ns 40ns 60ns 80ns 100ns 120ns


OPB_CLK

PCI_ABus[0:31]

PCI_DBus[0:31]

PCI_RNW

PCI_Select

PCI_xferAck

PCI_seqAddr

UG241_6-12_041206




maximum integer number of OPB burst is transferred (i.e., eight words per burst), followed with single OPB transactions to complete the operation. Data is buffered until either the PCI write operation terminates or until eight words are accepted. When eight words are buffered, the eight are burst written over the OPB. If the PCI write is terminated before eight words are written, multiple single OPB write transactions are used.

PCI writes to OPB are not buffered. Only one PCI initiator write to an OPB slave is supported at a time. If a read or write command is received from a PCI initiator during a write operation, a Disconnect Without Data (i.e., PCI retry) termination is generated until the posted write operation is complete.

If posted writes are pending due to an OPB retry, the bridge attempts to complete the write operation. PCI read requests cannot be serviced while posted writes are in progress.

The next figures show the IPIF-v3 Bridge to v3.0 interface for PCI to OPB writes.

The IPIF-v3 Bridge monitors outputs from the v3.0 to respond to target transactions. The signals used in target transactions are active and available at different times. The most important signal is BASE_HIT[x], which indicates that the v3.0 has claimed the current PCI transaction for base address register x. It is asserted for a single cycle.

Figure 6-13 shows transactions involving PCI Bus signals interfacing to the v3.0 core and interface signals between the v3.0 core and IPIF-v3 Bridge. During a target write operation, data is captured from the ADIO bus to a data register in the IPIF-v3 Bridge. The critical gating signal is S_DATA_VLD which qualifies the write operation.

The v3.0 signals which interface to the PCI Bus use names with a *_IO suffix. The address on AD_IO[31:0] is 0x20000000. The data on AD_IO[31:0] is 0x12153524. CBE_IO[3:0] is 0x7, which is output on S_CBE[3:0] to specify a memory write. FRAME_N is asserted and de-asserted to specify a single write transaction. The target responds with DEVSEL_N

Figure 6-13: v3.0 Signals in a PCI write to OPB

FF

ad_io

cbe_io

frame_io

trdy_io

irdy_io

stop_io

devsel_io

pclk

adio

addr_vld

base_hit

s_term

s_ready

s_abort

s_wrdn

s_src_en

s_data_vld

s_cbe

pci_cmd

FFFFFFF 78563412 FFFFFFFF

FFFFFFFF

00001000 78563412 FFFFFFFF

F 7 0 F

00001000

F 7 0 F

0000010000000000 0000000010000000

00000000 0000000000000001

UG241_6-13_041206




followed by TRDY_N. ADDR_VLD is active to indicate that ADIO is valid. S_WRDN is high to specify a write. S_DATA_VLD indicates that 0x12153524 on ADIO[31:0] is valid.

Figure 6-14 is the same transaction as Figure 6-13 except FRAME_N is asserted to specify a burst. S_DATA_VLD is asserted for the duration of the burst.

Figure 6-14: v3.0 Signals in PCI to OPB Burst Write Transaction

HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

11011111100011001100101010011000

0111

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

PERR_N

SERR_N

PAR

AD_IO

CBE_IO

FRAME_IO

TRDY_IO

IRDY_IO

STOP_IO

DEVSEL_IO

S_TERM

S_READY

S_ABORT

S_WRDN

S_SRC_EN

S_DATA_VLD

00000000

00000000

FFFFFFFF DF8CCA98920C6975

FFFFFFFF

F 7 0 F


HHHH 0000 HHHH

UG241_6-14_041206




Figure 6-15 shows the signals in a PCI to OPB write operation to address range 0. The generic settings for address range 0 are C_PCIBAR_0 = 0x00010000, C_PCIBAR_LEN_0 = 5, C_PCIBAR2IPIFBAR_0 = 0x00010000, C_PCI_PREFETCH_0 = 1, C_ENDIAN_TRANSLATE_0 = 0, C_SPACETYPE_0 = 1. The address written on AD[31:0] in the first clock cycle is 0x00010000. The data written on AD[31:0] is 0x12345678. The address is in the address range defined by C_PCI BAR_0 and C_PCIBAR_LEN_0. Chapter 8 provides information on address translation.

The PCI_DBus signals are in PCI_DBus[0:31] format, and the PCI data signals in AD[31:0]. The 0xFFFFFFFF display on the inactive AD is 0xHHHHHHHH when the user descends into individual AD bits. The target asserts DEVSEL_N and TRDY_N to accept data.The address and data used are the values present when PCI_Select is high. The low on PCI_RNW specifies a write operation. In the circled area in the figure, the values for PCI_DBus and PCI_ABus are 0x12345678 and 0x00010000. The PCI_xferAck is generated.

Figure 6-15: PCI Single Write to OPB Slave

00000000 12345678

00000000 00010000

00001000

UG241_6-15_041206

OPB_Clk

OPB_DBus

OPB_ABus

OPB_RNW

OPB_seqAddr

OPB_Select

OPB_xferAck

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

FFFFFFFF 78563412 FFFFFFFF

F 7 0 F

00000000




Figure 6-16 shows a PCI to OPB write transaction of a half word. The address written to AD[31:0] is 0x00001000. The data written on AD[31:0] is 0x00003412. The CBE is 0xC or 0b1100. On the PCI Bus, the memory write (7) on CBE[3:0] is followed by 0xC to indicate the byte enables. The OPB_BE format is OPB_BE[0:3]. The CBE format is CBE[3:0].

Figure 6-16: PCI single halfword write to OPB

FFFFFFFF

00010000

12340000

1100

0000

00000000

UG241_6-16_04120

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

OPB_CLK

PCI_ABus

PCI_DBus

CI_request

PCI_select

PCI_RNW

PCI_BE

00000000

00000000

0000

00001000 00003412 FFFFFFFF

F 7 C F




Figure 6-17 shows the signals in a burst write on the PCI bus. The start address is 0x00002000. Subsequent addresses are incremented by 4. FRAME_N is asserted for 30 clock cycles, so this is a burst of 30 doublewords. The first data is 0x98CA8CDF. On the OPB, there are 3 bursts of 8 doublewords shown.

Figure 6-17: PCI Burst Write to OPB slave

OPB_Cl k

OPB_DBus

OPB_ABus

OPB_RNW

OPB_seqAddr

OPB_Select

OPB_xferAck

AD FFFFFFFF 920C6975

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N UG241_6-17_041206

00000000

00000000

DF8CCA98 FFFFFFFF

F 7 0 F

00000000




Figure 6-18 shows the details of the first burst of eight on the OPB. The first dword is 0x98CA8CD7. The PCI_Buslock and PCI_Select are active for eight dwords.

PCI to OPB Read TransactionsThis section discusses a PCI initiator reading data from a OPB slave. In these transactions, the v3.0 core is a PCI target.

The PCI read commands supported by the OPB PCI Bridge are the Memory Read, Memory Read Multiple, and Memory Read line commands. During an execution of PCI read commands, an OPB retry from a OPB slave is translated to a PCI retry. Only one PCI initiator read of an OPB slave is supported at a time.

Figure 6-18: OPB Burst Transaction for PCI to OPB Burst Write

OPB_Cl k

OPB_DBus

OPB_ABus

OPB_RNW

OPB_seqAddr

OPB_Select

OPB_xferAck

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N UG241_6-18_041206

00000000 00000000

00000000 00000000

FFFFFFFF

F

98CA8CDF E8269C9D 10923D9B A839AC8B 39328710 ABEDECFD 198750D9 75690C92

00010000 00010004 00010008 0001000C 00010010 00010014 00010018 0001001C



PCI to OPB Read TransactionsR

Figure 6-19 shows the flow for PCI to OPB read transactions.

In Figure 6-20, the initiator with a read transfer requirement requests ownership of the PCI bus by asserting REQ_N. The arbiter grants access with GNT_N. Once GNT_N is received, the initiator waits until the bus is idle, as indicated by a high on the FRAME_N and IRDY_N pins.

On the first clock, the initiator drives the address on AD[31:0] and the read (0x6) command on CBE[3:0]. FRAME_N is asserted. Each target samples the address on AD[31:0], command on CBE[3:0], and FRAME_N to determine if it is the target.

In the second clock, the initiator asserts IRDY_N to indicate that it is ready to read data. The initiator also stops driving AD[31:0]. In read operations, the initiator drives AD[31:0] with the read address. This is followed by the target driving AD[31:0] with read data. A turnaround cycle is used in clock 2 to avoid bus contention on AD[31:0]. FRAME_N is de-asserted to indicate that this is the last data, i.e., that this is a single read transfer.

In clock cycle 3, the initiator drives the byte enables on CBE[3:0]. The addressed target asserts DEVSEL_N and TRDY_N to indicate that it is ready for the transaction. Data is read from the target when IRDY_N and TRDY_N are asserted. When the transaction is

Figure 6-19: PCI to OPB Read Flow

Figure 6-20: PCI Single Read

OPBIPIF

OPB PCI

UG241_6-19_041306

IPIF- V3Bridge

Bus2IP_MstRetryBus2IP_MstError

Bus2IP_MstTimeOutBus2IP_MstWrAck

Bus2IP_MstLastAck

IP2Bus_MstWrReqIP2Bus_MstRdReqIP2Bus_MstBurst

IP2BusMstBusLock

V3

ADIOS_READYS_TERMS_CBE

ADCBE


DEVSEL_NS_DATA_VALID

S_DATAS_WRDN

Basehit_vector

PCI_ABUSPCI_DBUSPCI_RNW

PCI_REQUESTPCI_BE

PCI_SELECTPCI_xferAcEPCI_toutSup

PCI_RetryPCI_busLock

PCI_CLK

FRAME_N

AD[31:0]

CBEN[3:0]

IRDY_N

TRDY_N

DEVSEL_N


UG241_6-20_041206




complete, the initiator de-asserts IRDY_N. The target de-asserts TRDY_N and DEVSEL_N, and stops driving AD[31:0].

In Figure 6-21, the burst read transaction begins with signal transitions similar to that of a single read transaction. The initiator requests and gains access to an idle PCI bus. In the first clock cycle, the initiator asserts FRAME_N, and provides the address on AD[31:0] and the command on CBE[3:0]. In clock cycle 2, the initiator asserts IRDY_N to indicate it is ready to read data. When FRAME_N is asserted, targets decode the address and command. As with the single PCI read, clock cycle 2 is a turnaround cycle, so the initiator stops driving AD[31:0].

In clock cycle 3, the target asserts DEVSEL_N and TRDY_N. The first difference with the single read transfer occurs here. The initiator keeps FRAME_N asserted, indicating that it is not the last data to be read. The initiator only writes the first address in a burst transaction. Each target contains an address counter which increments the start address on AD[31:0] by 4 to determine the address of the next DWORD.

If TRDY_N and IRDY_N are both asserted, the read burst of data occurs without wait states. If the initiator or target needs additional time to generate/receive data, IRDY_N and/or TRDY_N are de-asserted to insert wait states.

The initiator indicates the last data of the burst by de-asserting FRAME_N. The end of the burst does not occur until IRDY_N and TRDY_N are de-asserted. The target stops driving AD[31:0]

Figure 6-21: PCI Burst Read

UG241_6-21_041206


PCI_CLK

FRAME_N

AD[31:0]

CBE_N[3:0]

IRDY_N

TRDY_N

DEVSEL_N




Figure 6-22 shows the OPB IPIF signals for OPB read operations. The master starts by asserting the IP2Bus_MstRdReq request signal. Each transfer is acknowledged by Bus2IP_MstRdAck. There is more than one acknowledge if the transaction is a burst. The acknowledge indicates that the data has reached its final destination. The last acknowledge is accompanied by Bus2IP_MstLastAck.

Figure 6-23 shows the OPB signals for two single read transactions. The bus master outputs an address on PCI_ABus and data on PCI_DBus. Since this is a read, PCI_RNW is output high. PCI_Select is output high.

Figure 6-22: IPIF Master Single and Burst Read Transactions

Figure 6-23: PCI Initiator Read of OPB Slave

valid valid

A1 A2don’t care but usually will increment with each ack

L1 L2 don’t care

single read(write) burst read(write) (8 transfers per burst)

UG241_6-22_041206

Bus2IP_Clk

IP2Bus_MstRd(Wr)Req

IP2Bus_MstBurst

IP2Bus_MstBE

IP2Bus_MstBusLock

IP2Bus_Addr

IP2IP_Addr

Bus2IP_MstRd(Wr)Ack

Bus2IP_MstLastAck

Bus2IP_MstError

Bus2IP_MstRetry

Bus2IP_MstTimeOut

Annotation


OPB_CLK

PCI_ABus[0:31]

PCI_DBus[0:31]

PCI_RNW

PCI_Select

PCI_xferAckUG241_6-23_041206




Figure 6-24 shows the OPB signals for a sequential read. The sequential read of three word is for illustration purposes only, as the only bursts of eight are supported. This is similar to the single read with the difference that PCI_seqAddr is output high, and multiple address/data are driven on PCI_ABus/PCI_DBus. The OPB does not directly support burst modes. The sequential address allows slaves to achieve burst-like response. The next transfer is to the next sequential address in the same direction. M_busLock must be asserted during sequential transactions.

Figure 6-24: PCI Initiator Burst Read of OPB Slave

OPB_CLK

PCI_ABus[0:31]

PCI_DBus[0:31]

PCI_RNW

PCI_Select

PCI_xferAck

PCI_seqAddrUG241_6-24_041206

0ns 50ns 100ns




Figure 6-25 shows transactions involving PCI Bus signals interfacing to the v3.0 core and interface signals between the v3.0 core and IPIF-v3 Bridge. During a target read operation, data is captured from the ADIO bus to a data register in the IPIF-v3 Bridge. The critical gating signal is S_DATA_VLD which qualifies the write operation.

The v3.0 signals which interface to the PCI Bus are designated with *_IO names. The address on AD_IO[31:0] is 0x00001000. The data on AD_IO[31:0] is 0xDFCA2078. CBE_IO[3:0] is 0x6, which is output on S_CBE[3:0] to specify a memory write. FRAME_N is asserted and de-asserted to specify a single write transaction. The target responds with DEVSEL_N followed by TRDY_N. ADDR_VLD is active to indicate that ADIO is valid. S_WRDN is low to specify a read. S_SRC_EN indicates that 0xDFCA2078 on ADIO[31:0] is valid.

Target initiated wait states allow additional time before the first data transfer, and target initiated terminations limit the number of data phases in a transaction. These features are useful in both burst and non-burst targets.

Figure 6-25: v3.0 signals in PCI to OPB Read Transaction

11111111111111111111111111111111

0110 0000

7820CADF

00010000

FFFFFFFF

00001000

00000000000000000001000000000000


00000000000000000100000000001000

11111111111111111111111111111111

HHHH0110 0000

UG241_6-25_041206

OPB_Clk

OPB_DBus

OPB_ABus

OPB_RNW

OPB_Select

OPB_xferAck

OPB_seqAddr

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

AD_IO

CBE_IO

FRAME_IO

TRDY_IO

IRDY_IO

STOP_IO

DEVSEL_IO

S_TERM

S_READY

S_ABORT

S_WRDN

S_SRC_EN

S_DATA_VLD

S_CBE

PCI_CMD

1111 0110 0000

0000010000000000 0000000001000000

00000000 00000000

00000000 00000000

F 6 0





Figure 6-26 is a similar transaction to Figure 6-25 except FRAME_IO is asserted to specify a burst. A Memory Read Multiple (0xC) is driven on CBE_IO[3:0]. S_SRC_EN is asserted for the duration of the burst.

Figure 6-26: v3.0 Signals in PCI to OPB Burst Read Transaction

0 A

00000000

00000000

DFCA2078

329B3C98

AB58C3CO

DFDC2308

9D3802786D8592A

FEAD2398

CB82C0EA

A


UG241_6-26_041206

OPB_Clk

OPB_DBus

OPB_ABus

OPB_RNW

OPB_Select

OPB_xferAck

OPB_seqAddr

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

AD_IO

CBE_IO

FRAME_IO

TRDY_IO

IRDY_IO

STOP_IO

DEVSEL_IO

S_TERM

S_READY

S_ABORT

S_WRDN

S_SRC_EN

S_DATA_VLD

S_CBE

PCI_CMD

00000000

00000000

FFFFFFFF

0

FFFFFFFF

F

0000 HHHH

0000 1111

0001000000000000

11111111111111111111111111111111




Figure 6-27 shows the signals in a PCI to OPB read operation to address range 0. The generic settings for address range 0 are C_PCIBAR_0 = 0x00010000, C_PCIBAR_LEN_0 = 5, C_PCIBAR2IPIFBAR_0 = 0x00010000, C_PCI_PREFETCH_0 = 1, C_ENDIAN_TRANSLATE_0 = 0, C_SPACETYPE_0 = 1. Address translation is discussed in Chapter 8. The address written on AD[31:0] in the first clock cycle is 0x00010000. The address is in the address range defined by C_PCI BAR_0 and C_PCIBAR_LEN_0. The PCI_DBus signals are in PCI_DBus[0:31] format, and the PCI data signals in AD[31:0].

The OPB PCI Bridge asserts DEVSEL_N and TRDY_N to accept data.The address and data used are the values present when PCI_xferAck is high. The high on PCI_RNW specifies a read operation. The PCI_xferAck is generated.

Byte enables from the PCI bus are passed correctly to the OPB in single read transactions.

For Memory Read commands (i.e., not Memory Read Multiple), the PCI address is translated to the OPB address by high-order bit substitution. The 2 LSBs are set as defined by the byte enable vector for the first data phase. The LSBs are set to the lowest address of the byte lane asserted in the byte enable vector.

Figure 6-27: OPB Single Read Transaction from PCI to Address Range 0

7820CADF

00010000

FFFFFFFF

00001000FFFFFFFF

00004008 DFCA2078

FFFFFFFF

F

00010000

OPB_Clk

OPB_DBus

OPB_ABus

OPB_RNW

OPB_Select

OPB_xferAck

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

PCI_DBUS

PCI_ABUS

PCI_REQUEST

PCI_BUSLOCK

PCI_SELECT

PCI_RNW

DEVSEL_N

PCI XFERACK

00000000 00000000

00000000 00000000

FFFFFFFF

F 6 0

00000000

00000000 00000000




Figure 6-28 is similar to Figure 6-27 except the read is to the address range 1. For this address range, C_PCIBAR_1 = 0x00002000, C_PCIBAR_LEN_1 = 9, C_PCIBAR2IPIFBAR_1 = 0x00020000, C_PCIBAR_ENDIAN_TRANSLATE_1 = 1, C_PCI_PREFETCH_1 = 1, and C_PCI_SPACETYPE_1 = 1.

Figure 6-29 shows a PCI to OPB read transaction of a half word. The address written to AD[31:0] is 0x00001000. CBE is 0x6 or 0b0011. On the PCI Bus, the Memory Read (0x6) on CBE[3:0] is followed by 0x3 to indicate the byte enables. The OPB_BE format is OPB_BE[0:3]. The CBE format is CBE[3:0].

Figure 6-28: PCI to OPB Read Transaction to Address Range 1

Figure 6-29: PCI to OPB Halfword Read Transaction

FFFFFFFF

00020000

00000000

UG241_6-28_041206

OPB_CLK

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

PCI_DBus

PCI_ABus

PCI_request

PCI_select

PCI_RNW

PCI_BE

00000000

00000000

0000 1111 0000

00002000 FFFFFFFF 329B3C98 FFFFFFFF

F 6 0

00001000 00000000 DFCA2078 FFFFFFFF

1100

UG241_6-29_041206

OPB_CLK

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

PCI_DBus

PCI_ABus

PCI_request

PCI_select

PCI_RNW

PCI_BE

00000000

00000000 00000000

0000 0000

FFFFFFFF FFFFFFFF

F 6 C F




Figure 6-30 shows the signals in a PCI burst read of an OPB slave. The start address is 0x00001000. Subsequent addresses are incremented by 4. FRAME_N is asserted for a number clock cycles. The first data on AD[31:0] is DFCA2078.

Memory read multiple commands that translates to a burst read operation use the full 32 bits on the OPB independent of the byte enable specified by the PCI initiator.

FIFO Operation in PCI to OPB Read TransactionsData throughput can be high with Memory Read Multiple transactions. Memory Read Multiple commands of prefetchable memory are translated to repeated OPB burst read transactions of eight words. The OPB PCI Bridge supports only single word transfers and burst transfers of eight words. Repeated bursts of eight fill the IPIF2PCI FIFO until the first word address is seven or less words from the high-address of the OPB slave or the PCI initiator ends the transaction. When the high-address is approached, single OPB read requests read the last seven or less words. All byte enables are asserted. After the PCI initiator terminates the read transaction, the IPIF2PCI_FIFO is flushed of prefetched data that has not been read by the PCI initiator.

When read data is received from a OPB slave, the data is loaded in the IPIF2PCI FIFO. The OPB slave can throttle the data read by the PCI initiator. The IPIF2PCI FIFO is emptied when the PCI initiator accepts data faster than the OPB slave provides it. In this case, the OPB PCI Bridge generates a Disconnect with Data termination.

Figure 6-30: PCI to OPB Burst Read Transaction

FFFFFFFF00001000

FFFFFFFF 00000000 DFCA2078

329B3C98AB58C3C0

DFDC2308

9D380278 6D8592ACFEAD2398

CB82C0EA

FFFFFFFF

UG241_6-30_041206

OPB_Clk

OPB_DBus

OPB_ABus

OPB_RNW

OPB_Select

OPB_xferAck

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

PCI_DBUS

PCI_ABUS

PCI_REQUEST

PCI_BUSLOCK

PCI_SELECT

PCI_RNW

DEVSEL_N

PCI_XFERACK

PCI_TOUTSUP

PCI_RETRY

00000000 00000000

00000000 00000000

FFFFFFFF

F C 0 F

00000000

00000000 00000000




Throttling can cause low data throughput. The negative effect on system performance can be minimized by optimizing C_TRIG_PCI_XFER_OCC_LEVEL. C_TRIG_PCI_XFER_OCC_LEVEL sets the FIFO level at which the first data is transferred on the PCI bus during a Memory Read Multiple operation. The OPB PCI Bridge can throttle the first data transfer to PCI until C_TRIG_PCI_DATA_XFER_OCC_LEVEL words are in the FIFO. This parameter differs for different clock rates and must be adjusted to insure that the PCI specification not be violated. C_TRIG_PCI_XFER_OCC_LEVEL insures that the transfer is a minimum number of words even if the OPB slave throttles data.

C_TRIG_IPIF_READ_OCC_LEVEL defines the FIFO occupancy level that triggers prefetching more data from the OPB slave. Set C_TRIG_IPIF_READ_OCC_LEVEL to insure that the FIFO does not empty while the PCI initiator is requesting data.

In a PCI initiator read multiple command of an OPB slave, the IPIF attempts to keep the IPIF2PCI_FIFO full of data read from an OPB slave device for subsequent transfer to the PCI initiator. Data remaining in the IPIF2PCI FIFO when the PCI initiator terminates the read multiple command is discarded. Prefetch is not performed on Memory Read commands (i.e., not Memory Read Multiple).

A single Memory Read transaction is not affected by differences in the OPB and PCI clock speeds. A Memory Read Multiple is affected by differences in the OPB and PCI clock speeds. If the OPB clock is faster, the data flow is limited by the PCI bus and the data flow is one continuous read multiple.

If the OPB clock is slower, the data flow is a series of PCI transactions that are terminated by a Disconnect Without Data after the number of data phases specified by C_TRIG_PCI_DATA_XFER_OCC_LEVEL. The series of PCI transactions occurs when the OPB slave does not supply data fast enough for execution of read multiple command with single PCI clock cycle data phases.

Non-Prefetchable Data SourcesNon-prefetchable data sources, such as FIFOs, exhibit “side effects” from reads. Data can be altered or lost. The use of S_SRC_EN results in reading the data source ahead of the actual transfer.

Figure 6-31 illustrates some of the functionality required when using FIFOs.

The FIFO must have an additional control signal to back up, or “undo” three reads. The back up is included in a FIFO by making the actual depth three less than the maximum possible, and by using a bidirectional read pointer. This prevents new data entering the FIFO from overwriting data in the FIFO that may need to be restored.

Figure 6-31: Non-Prefetchable Data Source

PUSHPOPBACK_UP

AFTFAETE

DI

ADIO[31:0]

FIFO_OE

DO

Non_prefetcabledata source (FIFO)

FIFO_WRFIFO_RD

BACK_UPCLK

ALMOST_FULLTOTALLY_FULLALMOST_EMPTYTOTALLY_EMPTY

UG241_6-31_041206




The FIFO must also have a set of flags that provide FIFO status information. The general functionality of the flags, and their uses, are listed below. The actual flags used by the OPB PCI Bridge are given in Figure 6-6, and are more complex.

Totally Empty: If the FIFO is totally empty at the beginning of a read transaction, a Retry is generated.

Totally Full: If the FIFO is totally full at the beginning of a write transaction, a retry is generated.

Almost Empty: When the FIFO becomes almost empty during a read transaction, a Disconnect is generated. The threshold for almost empty depends on the type of disconnect that is signalled (with or without data).

Almost Full: When the FIFO becomes almost full during a write transaction, a Disconnect is generated. The threshold for almost full depends on the type of disconnect that is signaled (with or without data).

To determine the number of times the FIFO must be backed up after a target read, the difference between anticipated transfers and actual transfers is monitored. When a target read has completed, the address pointer should back up the FIFO if necessary.

The OPB Master cannot throttle data in burst mode. This can be a concern during DMA operation because the data source is an OPB slave which can throttle data. If the IPIF2PCI_FIFO empties because the OPB slave is throttled, the OPB PCI Bridge terminates the PCI transaction. The OPB PCI Bridge starts a new transaction when the IPIF2PCI_FIFO has filled to the parameter-defined occupancy level, or the DMA transaction has completed. To increase data throughput, set C_TRIG_PCI_DATA_XFER_OCC_LEVEL to 16 when DMA is included.



R

Chapter 7

OPB to PCI Transactions

This chapter discusses OPB to PCI write and read transactions. These transactions involve the IPIF, IPIF-v3 bridge, and v3 modules. The registers and generics used in OPB to PCI transactions are discussed. Block diagrams of the functional elements used in OPB to PCI transactions are provided, followed by a flow diagram of the modules used for an OPB to PCI transactions. Write transactions are discussed first, followed by read transactions.

Signal waveforms of OPB write transactions are given, first as OPB signal and PCI Bus signal sets in isolation. This is followed by waveforms using an integrated set of signals from all three modules. This format is then followed for OPB read transactions.

Generics and RegistersThe C_INCLUDE_OPB_MST2PCI_TRG generic is set to 1 for OPB to PCI read and write transactions. The other types of generics for OPB to PCI transactions are address range, FIFO, and DMA generics. The number of address ranges, defined by C_IPIFBAR_NUM, is from one to six. Each address range is defined by the following set of generics: C_IPIFBAR_n, C_IPIFBAR_HIGHADDR_n, C_IPIFBAR2PCIBAR_n, C_IPIFBAR_ENDIAN_TRANSLATE_n, C_IPIF_PREFETCH_n, and C_IPIF_SPACETYPE_n, with n representing the number of the address range.

Either a register or a generic can be used to specify the address translation used in OPB to PCI transactions. The C_INCLUDE_BAROFFSET_REG generic specifies whether IPIFBAR2PCIBAR_n registers are used instead of the C_IPIFBAR2PCIBAR_n generics in the address translation. The address translation registers are located beginning at C_BASEADDR + 0x180.

The IPIF2PCI FIFO is optionally used in OPB to PCI write transactions. The PCI2IPIF FIFO is optionally used in OPB to PCI read transactions. The C_IPIF2PCI_FIFO_ABUS_WIDTH generic defines the existance and depth of the IPIF2PCI FIFO. The C_PCI2IPIF_FIFO_ABUS_WIDTH defines the existance and depth of the PCI2IPIF FIFO.

Direct Memory Access (DMA) is done by a module in the IPIF. The generics defining DMA operation are C_DMA_CHANTYPE, C_DMA_BASEADDR, C_DMA_HIGHADDR, and C_DMA_LENGTH_WIDTH. Set C_DMA_CHAN_TYPE = 9 to exclude DMA functionalty from the core. Set C_DMA_CHAN_TYPE = 0 to include simple DMA. Scatter Gather DMA is not supported in the OPB PCI Bridge. The C_DMA_LENGTH_WIDTH generic defines the number of bits in the length register.

OPB PCI Functional DiagramsIn Figures 7-1 and 7-2 to 7-5, block diagrams of the major modules used in OPB to PCI write transactions are given. These provide a reference for external and internal signals used.



Chapter 7: OPB to PCI TransactionsR

Figure 7-1 is the top level pinout of the OPB PCI core. The OPB signals are on the left. The PCI bus signals are on the right. The OPB signals include signals for an OPB slave and OPB master. The OPB signals used are defined by the C_INCLUDE_OPB_MST2PCI_TARG and C_INCLUDE_PCI_INT2OPB_SLV generics.

Figure 7-2 shows the pinout for the v3 core. The PCI signals are on the right. Most of the signals on the left interface to the IPIF-v3 Bridge. For OPB to PCI writes and reads, the v3 initiator signals are used. PCI initiator signals use names with a M_* prefix. v3 target signals, which use names with a S_* prefix, are not used in OPB to PCI transactions.

The following signals control initiator data transfer to and from the v3.

ADIO[31:0]: Bidirectional bus between the v3 core and IPIF-v3 Bridge for data and address transfer.

M_DATA_VLD: When the IPIF-v3 Bridge is sinking data (initiator reads), M_DATA_VLD indicates that valid data is on the ADIO bus. When the IPIF-v3 Bridge is sourcing data (initiator writes), M_DATA_VLD indicates that a data phase has completed on the PCI Bus.

M_SRC_EN: v3 output to IPIF-v3 Bridge is used during initiator burst writes. It indicates to the IPIF-v3 Bridge that the data source which drives output data onto the ADIO bus must provide the next data.

TIME_OUT: v3 output to IPIF-v3 Bridge indicates that the latency timer has expired. TIME_OUT indicates that the OPB PCI Bridge has exceeded the maximum number of clock cycles allowed by the system configuration software. It is used in initiator burst transactions.

Figure 7-1: OPB PCI

OPB_ABus[0:31]OPB_DBus[0:31]

PCI_ABUS[0:31]PCI_requestPCI_busLockPCI_RNWPCI_BEPCI_seqAddr

OPB_MGrant

OPB_xferAckOPB_errAckOPB_retryOPB_timeoutOPB_selectOPB_RNWOPB_BE

PCI_xferAckPCI_errAckPCI_toutSupPCI_DBus_[0:31]

IP2INTC_IrptOPB_ClkOPB_Rst

PCIBus

OPB

AD[31:0]CBE[3:0]

PAR

FRAME_N

TRDY_NIRDY_N

STOP_NIDSEL

INTR_A

PERR_NSERR_N

REQ_NGNT_N

RST_NPCLK

INTR_A_INTREQ_N_toARB

FRAME_IIRDY_I

PCI_monitor[0:48]

RCLK

UG241_7-1_011806



OPB PCI Functional DiagramsR

CSR[39:0]: v3 output to IPIF-v3 Bridge provides status on the current transfer. This is used primarily in initiator burst applications with non-prefetchable sources to determine if any associated address pointers must be “backed up”.

REQUEST: IPIF-v3 Bridge output to the v3 core to request the PCI Bus and to begin an initiator transaction once GNT_I is asserted.

REQUESTHOLD: IPIF-v3 Bridge output to the v3 core to continue requesting the PCI Bus for an extended period of time.

M_WRDN: IPIF-v3 Bridge output to the v3 core indicating the direction of data transfer for the current initiator transaction. Logic high indicates that the IPIF-v3 Bridge is sourcing data (i.e. initiator write).

M_CBE[3:0]: IPIF-v3 Bridge output to the v3 core indicating the PCI command and byte enables during an initiator transaction. The command is valid during the assertion of M_ADDR_N by the v3. The byte enables are valid during each data phase.

M_READY: IPIF-v3 Bridge output indicating that it is ready to transfer data. M_READY can be used to insert wait states during the first data phase of a transaction.

COMPLETE: IPIF-v3 Bridge output requesting that the initiator state machine complete the current transaction.

The following signals are output by the initiator state machine in the v3. These states are defined in Appendix B of the PCI Local Bus Specification.

I_IDLE indicates that the initiator state machine is in the idle state and that it is not actively driving the PCI Bus.

DR_BUS indicates that the initiator state machine is driving the PCI Bus because the arbiter has parked the bus on the v3 (GNT_I asserted with no pending or active request for bus grant from the IPIF-v3 Bridge).

M_ADDR_N indicates that the initiator state machine expects the IPIF-v3 Bridge to drive ADIO with the PCI Bus address for a requested transaction. This is not a confirmation that a bus transaction will begin.




M_DATA indicates that the initiator state machine is in the data transfer state.

In Figure 7-3, the IPIF-v3 Bridge interfaces to the v3 core on the right and to the OPB IPIF on the left. The interface to the OPB IPIF is to the IPIF’s Master Attachment module using the IP2Bus_Mst* and Bus2IP_Mst* signals, and to the Slave Attachment module, using Bus2IP_* and IP2Bus_* signals. The interface to the v3 is to the v3 initiator signals M_*. For OPB2PCI writes and reads, the v3 target signals S_* and the IPIF-v3 Bus2IP_Mst* and

Figure 7-2: V3 Connections

FRAME_NTRDYQ_NIRDYQ_NSTOPQ_NDEVSELQ_NADDR[0:31]ADIO[0:31]CFG_VLDCFG_HITC_TERMC_READYCFG_SELFBASE_HITADDR_VLDS_DATAS_TERMS_READYS_ABORTS_WRDNS_SRC_ENS_DATA_VLDS_CBEPCI_CMDREQUESTREQUESTHOLDCOMPLETEM_WRDNM_READYM_SRC_ENM_DATA_VLDM_CBETIME_OUTM_DATADR_BUSM_ADDR_NIDLEB_BUSYBACKOFFINTR_NPERRQ_NSERRQ_NKEEPOUTCSR[39:0]SUB_DATARSTCLKI_IDLEPCLKRCLKREFRSTREFCLK

FRAME_NTRDYQ_NIRDYQ_N

STOPQ_NDEVSELQ_N

ADDR[0:31]ADIO[0:31]CFG_VLDCFG_HITC_TERM

C_READYCFG_SELFBASE_HIT

ADDR_VLDS_DATAS_TERM

S_READYS_ABORT

SWRDNS_SRC_EN

S_DATA_VLDS_CBE

PCI_CMDREQUEST

REQUESTHOLDCOMPLETE

M_WRDNM_READY

M_SRC_ENM_DATA_VLD

M_CBETIME_OUT

M_DATADR_BUS

M_ADDR_NIDLE

B_BUSYBACKOFF

INTR_NPERRQ_NSERRQ_N

V3_read_request_abort_strbCSR[39:0]

SUB_DATARSTCLK

I_IDLEPCLKRCLK

REFRSTREFCLK

AD_IOCBE_IOPAR_IO

FRAME_IOTRDY_IOIRDY_IO

STOP_IODEVSEL_IO

IDSEL_IOE_INTAPERR_IOSERR_IO

REQ_OGNT_IRST_I

ADCBEPARFRAME_NTRDY_NIRDY_NSTOP_NDEVSEL_NIDSEL_intOE_INTAPERR_NSERR_NREQ_NGNT_IRST_N

PCI BusSignals

IPIF-V3Bridge Signals

UG241_7-3_040406




IP2Bus_Mst* pins are not used. The lower left of the figure shows 18 register read and write clock enables generated by the OPB IPIF.

In Figure 7-4, the OPB IPIF interfaces to the IPIF-v3 Bridge on the right and to the OPB on the left. On the OPB side, the Mn_* signals are master signals, and the Sln_* signals are slave signals. On the interface to the IPIF-v3 Bridge, the Bus2IP_* signals are outputs to the

Figure 7-3: IPIF-v3 Bridge

Bus2IP_ClkBus2IP_ResetBus2IP_WrReqBus2IP_RdReqBus2IP_BurstBus2IP_Addr[0:31]Bus2IP_Data[0:31]Bus2IP_BE[0:3]

IP2Bus_RetryIP2Bus_Addr[0:31]IP2Bus_Data[0:31]IP2Bus_RdAckIP2Bus_WrAckIP2Bus_ErrorIP2Bus_ToutSupIP2Bus_MstWrReqIP2Bus_MstRdReqIP2Bus_MstBurstIP2Bus_MstBusLock

IPIFBAR_RdCE_vectorIPIFBAR_WrCE_vectorIPIF_CE_vectorIPIF_Override_Prefetch_vec_RdCEIPIF_Override_Prefetch_vec_WrCEConfig_CE_vectorConfig_Addr_port_RdCEConfig_Addr_port_WrCEConfig_Data_port_RdCEConfig_Data_port_WrCEIPIF_Inhibit_Xfer_RdCEIPIF_Inhibit_Xfer_WrCEIPIF_Mst_Addr_Def_RdCEIPIF_Mst_Addr_Def_WrCEIPIF_Mst_Rd_Addr_RdCEIPIF_Mst_Wr_Addr_RdCEPCI_Override_Prefetch_vec_RdCEPCI_Override_Prefetch_vec_WrCE

Bus2IP_MstRetryBus2IP_MstTimeOutBus2IP_MstWrAckBus2IP_MstLastAckBus2IP_IPMstTrans

IPIF_WrBurst_ImminentInhibit_FaF_Writes

FIFO2Bus_BE[0:31]DevNum


Bus2IP_WrReqBus2IP_RdReq

Bus2IP_BurstBus2IP_AddrBus2IP_Data

Bus2IP_BE

IP2Bus_RetryIP2Bus_AddrIP2Bus_Data

IP2Bus_RdAckIP2Bus_WrAck

IP2Bus_ErrorIP2Bus_ToutSup

IP2Bus_MstWrReqIP2Bus_MstRdReq


Bus2IP_MstRetryBus2IP_MstTimeOut

Bus2IP_MstWrAckBus2IP_MstLastAckBus2IP_IPMstTrans

IPIF_WrBurst_ImminentInhibit_FaF_Writes

FIFO2Bus_BEDevNum

Bus2IP_RdCE(s)

Bus2IP_WrCE(s)

S_WRdNS_Data

S_SRC_ENS_Data_Vld

S_TermS_Ready

S_CBE

S_WRdNS_DataS_SRC_ENS_Data_VldS_TermS_ReadyS_CBE

IRDY_NSERRO_NPERRO_NTime_Out

INTR_N

M_Addr_NM_SRC_ENM_Data_Vld

M_DataM_ReadyCompleteRequest

M_WRdNM_CBE

CFG_SELF

PCI_CMD_15_14PCI_CMD_12_7_9

V3_RSTV3_Clk

Base_HitADDR[0:31]ADIO[0:31]

IRDY_NSERRO_NPERRO_NTime_OutINTR_N

M_Addr_NM_SRC_ENM_Data_VldM_DataM_ReadyCompleteRequestM_WRdNM_CBE

CFG_SELF

V3_RstV3_Clk

Base_HitADDRADIO

Brdg_V3_TransPCI_Init_Rd_SERRPCI_Init_Wr_SERRIPIF_Mst_RdWr_1

Brdg_V3

UG241_7-3_030206




IPIF-v3 Bridge, and the IP2Bus_* are inputs from the IPIF-v3 Bridge. The IP2Bus_Mst* and Bus2IP_Mst* signals are not used in OPB to PCI transactions.

Figure 7-5 provides the pinout of the IPIF_Mst2PCI_targ module. This module consists of the pci_initiator_req_sm and pci_wr_initiator_pciretry_sm state machines, and the pci_initiator, pci_addr_counter, ipif2pci_bar_reg, ipif2pci_addr_translate, and ipifmst_intrpt_addr_regs modules.

Figure 7-4: OPB IPIF Connections

OPB_MnGrantOPB_xferAckOPB_errAckOPB_retryOPB_timeoutOPB_selectOPB_RNWOPB_seqAddrOPB_BE[0:31]OPB_ABus[0:31]OPB_DBus[0:31]

OPB_MnGrantOPB_xferAckOPB_errAck

OPB_retryOPB_timeout

OPB_selectOPB_RNW

OPB_seqAddrOPB_BE

OPB_ABusOPB_DBus

Sln_DBus[0:31]Sln_xferAckSln_toutSupSln_retry

Mn_ABus[0:31]Mn_requestMn_busLockMn_RNWMN_BE[0:3]Mn_seqAddr

Bus2IP_BEBust2IP_WrReqBus2IP_RdReqBus2IP_IPMstTransBus2IP_Burst

IP2Bus_IntrEvent

OP

B

IPIF

-V3

Bri

dg

e

Bus2IP_BE[0:31]Bust2IP_WrReqBus2IP_RdReq

Bus2IP_IPMstTransBus2IP_Burst

IP2Bus_IntrEvent



RmtOPBmst2IP_WrBurstDMA2IP_Wr_Imminent_n

RmtOPBmst2IP_WrBurst_imminentDMA2IP_Wr_Imminent_n

ResetOPB_ClkIP2INTC_Irpt

PCI_DBusPCI_xferAckPCI_toutSup

PCI_retry

PCI_ABusPCI_request

PCI_busLockPCI_RNW

PCI_BEPCI_seqAddr

bus_rst_iOPB_Clk

IP2INTC_Irpt

UG241_7-5_040406

IP2Bus_AddrBus2IP_AddrBus2IP_DataBus2IP_RNWBus2IP_CSBus2IP_CEBus2IP_RdCEBus2IP_WrCEIP2Bus_Data_ByteswpdIP2Bus_WrAckIP2Bus_RdAckIP2Bus_RetryIP2Bus_ErrorIP2Bus_ToutSupInhibit_FaF_WritesFIFO2Bus_BE_ByteswpdIP2Bus_MstWrReqIP2Bus_MstRdReqIP2Bus_MstBurstIP2Bus_MstBusLockBus2IP_MstWrAckBus2IP_MstRdAckBus2IP_MstRetryBus2IP_MstErrorBus2IP_MstTimeOutBus2IP_MstLastAck

IP2Bus_Addr_[0:31]Bus2IP_Addr_[0:31]Bus2IP_Data_[0:31]

Bus2IP_RNWBus2IP_CSBus2IP_CE

Bus2IP_RdCEBus2IP_WrCE

IP2Bus_Data_[0:31]IP2Bus_WrAckIP2Bus_RdAck

IP2Bus_RetryIP2Bus_Error

IP2Bus_ToutSupIP2Bus_PostedWrInh

FIFO2Bus_BE_ByteswpdIP2Bus_MstWrReqIP2Bus_MstRdReq


Bus2IP_MstWrAckBus2IP_MstRdAckBus2IP_MstRetryBus2IP_MstError

Bus2IP_MstTimeOutBus2IP_MstLastAck




Figure 7-5: IPIF_MST2PCI_TARG Module

Bus2IP_ClkBus2IP_WrReqBus2IP_WrReq_CEgtdBus2IP_RdReqBus2IP_BurstBus2IP_AddrBus2IP_DataBus2IP_IPMstTransIPIFBAR_CE_vectorIPIF2PCI_BAR_RdCEIPIF2PCI_BAR_WrCEIP2Bus_RetryIPIF2IP_WrBurst_ImminentPass_RmtMst_Bus2IP_RdWrReqReg2IPIF_Data_intrpt_addr_regsReg2IPIF_Data_BAR_regIP2Bus_RdAck_addr_regIP2Bus_WrAck_addr_regIP2Bus_RdAck_BAR_regIP2Bus_WrAck_BAR_regIP2Bus_Retry_PCI_init_SMIP2Bus_ToutSup

IPIF2PCI_Mst_Rd_Addr_phase_PCInitWrFull_IPIF2PCILoad_IPIF_BE_fo_PCI_RdRd_Advance_strb_IPIF2PCIWr_ge_Rd_plsTrg_IPIF2PCIRd_Addr_EQ_Wr_IPIF2PCI_FIFORd_pls1_eq_Wr_IPIF2PCIRd_Backup1_strb_IPIF2PCIRd_Backup2_strb_IPIF2PCIRd_Backup3_strb_IPIF2PCIData_N_Addr_RmtMst2PCItargBus2IP_Addr_translated

Config_Addr_port_RdCEConfig_Addr_port_WrCEConfig_Data_port_RdCEConfig_Data_port_WrCEIPIF_Inhibit_Xfer_RdCEIPIF_Inhibit_Xfer_WrCEIPIF_Mst_Addr_Def_RdCEIPIF_Mst_Addr_Def_WrCEIPIF_Mst_Rd_Addr_RdCEIPIF_Mst_Wr_Addr_WrCE

Block_RmtMst_OP_dueto_PCI_WrRetryRequest_for_PCI_RdRd_Req_to_V3_occured_FlagPCI_CMDPCI_Read_Req_by_IP_mst_PCIsideRmt_IPIFmst_RdReq_InhibitRmt_IPIFmst_WrReq_InhibitRmt_IP_mst_rd_PCI_InProg_IPIFsideRmt_IP_mst_rd_PCI_InProg_PCIsideRmt_IP_mst_wr_PCI_InProg_IPIFsideRmt_IP_mst_wr_PCI_InProg_PCIsideRmt_PCI_init_rd_IPIF_InProg_IPIFsideSet_Rmt_PCI_init_rd_IPIF_InProg_PCIsideRmt_PCI_init_rd_IPIF_InProg_PCIsideRmt_PCI_init_wr_IPIF_InProg_IPIFsideSet_Rmt_PCI_init_wr_IPIF_InProg_PCIsideDoNot_load_pci2ipif_fifo_aborted_RdIPIF_Override_Prefetch_vectorBridge_xfer_CE_active_IPIFsideBridge_xfer_CE_vector_regdDo_Burst_PCI_read_IPIFsidePCI_Retry_on_Rd_bit_strbPCI_Retry_on_Wr_bit_strbBrdg_V3_Trans_Reg

IPIF_Mst_RdWr_Intrpt_vector

PCI2IPIF_FIFO_Reset_PCInitPCI2IPIF_FIFO_Reset_PCInit_IPIFside

Wr_eq_Rd_mns3_PCI2IPIF Wr_mnsTrg_lt_Rd_mns3_PCI2IPIF

Wr_Advance_strp_PCI2IPIF

Reset_IPIFside Reset_PCIside

IPIF2PCI_FIFO_PCInitIPIF2PCI_FIFO_PCInit_IPIFside

V3_ClkM_Addr_N

M_SRC_EnM_Data_Vld

M_DataSERRO_NPERRO_NTime_Out

CFG_SELFM_ReadyRequest

CompleteV3_read_request_abort_strb

M_WRdN

UG241_7-5_030206




As shown in Figure 7-6, the IPIF2PCI FIFO module consists of the IPIF2PCI_FIFO_CNTL control, PF_DPRAM_SELECT dual port RAM, and ENDIAN_SWAP modules. The C_FIFO_ABUS_WIDTH generic determines the FIFO depth. The C_TRIG_PCI_DATA_XFER_OCC_LEVEL, C_TRIG_IPIF_READ_OCC_LEVEL, and C_INHIBIT_IPIF_READ_VAC_LEVEL generics control the functionality of the IPIF2PCI_FIFO_CNTL module.

The C_IPIFBAR_NUM, C_IPIF_ENDIAN_TRANSLATE_EN_n, C_PCINUM, and C_PCI_ENDIAN_TRANSLATE_EN_n generics are used by the endian swap module to swap the order of the data and/or byte enables.

The PCI Initiator drives the Read Backup Strobe signals in the IPIF2PCI_FIFO_CNTL module.

Address TranslationThe address presented on the OPB is translated to the PCI address space by high-order bit substitution with the 2 least significant bits (LSBs) set as follows. If the target PCI address space is memory space, the 2 LSBs are set to 00 (i.e., linear incrementing mode). If the PCI target address space is IO-space, the 2 LSBs are passed unchanged from that presented on the OPB bus.

OPB to PCI Write TransactionsThis section discusses OPB single and burst write transactions to a PCI target. In OPB to PCI transactions, the v3 core is the PCI initiator. The OPB master can be the local DMA, a master device, or a bridge, such as the PLB-to-OPB Bridge.

Commands supported in OPB master write operations are PCI I/O write and memory write (both single and burst). The PCI command used is based on the address/qualifier

Figure 7-6: IPIF2PCI FIFO Functional Diagram

ENDIANSWAP

DS241_7-7_040406

IPIF_FIFO_CNTL

IPMASTER

PCIInitiator

WRITE_ABUSWR_ADVANCED_STRBWR_ABUS_GRAY_SYNCDFIFO_RESET_WR_CLK

WR_FULLWR_MNSTRG_LT_RE_MNS3WR_PLSVAC_LT_RD_MNS3

WR_CLK

WR_DATA

READ_ABUS

M_CBE

ADIO

DATA_N_ADDRADDR_TO_V3CORE[0:31]

PCI_CMD_REG[0:3]

READ_CLK

WR_GE_RD_PLSTRGRD_PLS1_EQ_WR_RDSIDE

RD_ADDR_EQ_WR_ADDR

RD_BACKUP1_STRBRD_BACKUP2_STRBRD_BACKUP3_STRB



RD_RSTRD_CLK

RD_ENABLE

RD_DATA



OPB to PCI Write TransactionsR

decode, which includes the address, memory type (e.g., I/O or memory type) and if OPB_seqAddr is asserted. Both the single write transactions and burst write transactions are posted writes.

Figure 7-7 provides the principle signals used in an OPB2PCI write operation.

Figure 7-8 shows the OPB signals for a single write transaction by an OPB Master. The bus master outputs an address on OPB_ABus and data on OPB_DBus. Since this is a write, OPB_RNW is output low. The bus master outputs OPB_Select high. When address and data are valid, the IPIF-v3 Bridge IP2Bus_WrAck output causes the OPB_xferAck to be output high.

Only one OPB to PCI write is can be done at a time. Write transactions are not queued in the bridge. During the interval in which the OPB write is complete and the PCI write is in progress, the OPB PCI Bridge asserts an OPB retry to terminate subsequent OPB transactions. When a posted write is complete, another OPB write transaction can be initiated.

Figure 7-9 shows the OPB signals for a sequential write. This is similar to the single write with the difference that OPB_seqAddr is output high, and multilple address/data are written on OPB_ABus and OPB_DBus. The OPB does not directly support burst modes. The sequential address signal allows slaves to achieve burst-like response. The next

Figure 7-7: OPB to PCI Write Flow

Figure 7-8: OPB Single Write Transaction

OPBIPIF

DS241_7-2_040406

IPIF- V3Bridge

BUS2IP_ADDRBUS2IP_DATABUS2IP_RNW

BUS2IP_BURSTBUS2IP_WRCE

IP2BUS_WRACKIP2BUS_RETRY

IP2BUS_TOUTSUP

INHIBIT_FAF_WRITES

V3

ADIOREQUEST

COMPLETEM_READYM_WRDNM_CRE

ADCBE


DEVSEL_NM_DATA_VALID

M_DATAM_ADDR_NM_SRC_EN

OPB_ABUSOPB_DBUSOPB_RNW

OPB_SEQADDROPB_BE

OPB_SELECTPCI_xferAck

PCI_Retry


OPB_CLK

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_RNW

OPB_Select

OPB_xferAck

UG241_7-8_040406




transfer is to the next sequential address in the same direction. M_busLock must be asserted during sequential transactions.

Figure 7-10 shows the signals from the OPB IPIF to the IPIF-v3 Bridge for OPB write operations to registers in the IPIF-v3 Bridge. These writes do not generally result in PCI Bus transactions. Four words are transmitted out on Bus2IP_Data. The IPIF-v3 Bridge uses the Bus2IP_WrCE(i) signals to enable registers. The IPIF-v3 Bridge responds with IP2Bus_Wrack for data D1, D2, and D3. The acknowledge is delayed for data D2, so IP2Bus_Toutsup is asserted. There is an error for data D3 and a retry for data D4.

In Figure 7-11, the initator with a write transfer requirement requests ownership of the bus by asserting REQ_N (not shown). The arbiter grants access with GNT_N. Once GNT_N is received, the initiator waits until the bus is idle, as indicated by a high on the FRAME_N and IRDY_N pins.

On the first clock, the initiator drives the address on AD[31:0] and the command on CBE[3:0]. FRAME_N is asserted. Each target samples the address on AD, command on CBE[3:0], and FRAME_N to determine if it is the target.

In the second clock, the initiator asserts IRDY_N to indicate data is driven. FRAME_N is de-asserted to indicate that this is the last data written, i.e., that this is a single write transfer. The initiator drives the byte enables on CBE[3:0]. The addressed target asserts DEVSEL_N and TRDY_N to indicate that it is ready to accept the transaction. Data is written to the target when IRDY_N and TRDY_N are asserted. When the transaction is

Figure 7-9: OPB Sequential Write Transaction

Figure 7-10: IPIF Register Write Operation


OPB_CLK

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_RNW

OPB_Select

OPB_xferAck

OPB_seqAddr

UG241_7-9_040406

Bus2IP_Clk

Bus2IP_WrCE(i)

Bus2IP_WrReq

Bus2IP_Data

IP2Bus_Toutsup

IP2Bus_WrAck

IP2Bus_Error

IP2Bus_Retry

Annotation

D1 D2 D3 D4

write

write w/timeout supression UG241_7-10_040406




complete, the initiator de-asserts IRDY_N and the target de-asserts TRDY_N and DEVSEL_N.

Figure 7-11: PCI Single Write

In Figure 7-12, the burst write transaction begins with signal transitions similar to that of a single write transaction. The initiator requests and gains access to an idle PCI bus. In the first clock cycle, the initiator asserts FRAME_N, and provides the address on AD[31:0] and the command on CBE[3:0]. In clock cycle 2, the initiator asserts IRDY_N and drives data on AD[31:0] and byte enables on CBE[3:0]. When FRAME_N is asserted, targets decode the address and command, and the addressed target asserts DEVSEL_N and TRDY_N.

In clock cycle 3, the initiator and target both sample IRDY_N and TRDY_N asserted and the data transfer of the first written data occurs. Here the first difference with the single write transfer occurs. The initiator keeps FRAME_N asserted, indicating that it is not the last data written. The initator only writes the first address in a burst transaction. Each target contains an address counter which increments the start address provided on AD[31:0] by 4 to determine the address of the next DWORD.

If TRDY_N and IRDY_N are both asserted, the write burst of data occurs without wait states. If the initiator or target needs additional time to generate/receive data, IRDY_N and/or TRDY_N are de-asserted to insert wait states.

The initiator indicates the last data of the burst by de-asserting FRAME_N. The end of the burst does not occur until IRDY_N and TRDY_N are de-asserted.

The previous figures contain waveforms which show the functionality of the OPB IPIF, IPIF-v3 Bridge, and v3 in isolation. The following figures show interaction between the IPIF-v3 Bridge and v3 core.

The OPB Master cannot throttle data in burst mode. During DMA operation, a OPB slave can throttle data. If the IPIF2PCI_FIFO empties because the OPB slave is throttled, the OPB PCI Bridge terminates the PCI transaction. The OPB PCI Bridge starts a new transaction when the IPIF2PCI_FIFO has filled to the parameter-defined occupancy level, or the DMA


PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_NUG241_7-11_040506




transaction has completed. To increase data throughput, set C_TRIG_PCI_DATA_XFER_OCC_LEVEL to 16 when DMA is included.

Figure 7-13 shows a burst transfer of the v3. It also shows the timing of selected IPIF-v3 Bridge and

PCI Bus signals during the transaction the v3 performing a burst transfer. The process is started with the REQUEST from the IPIF-v3 Bridge. The v3 is granted access to the PCI Bus. Data is provided to the v3 on the ADIO pins. The IPIF-v3 Bridge provides the memory write command (0x7) on M_CBE[3:0]. The process is complete when the IPIF-v3 Bridge asserts COMPLETE.

Figure 7-12: PCI Burst Write

0ns 50ns 100ns 150ns

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_NUG241_7-12_040506




The next set of figures provide examples of OPB to PCI write transactions using the entire OPB PCI Bridge. Some focus is given on address translation, which is discussed in Chapter Address Translation.

Figure 7-14 shows the signals in an OPB to PCI write operation to address range 0. The generic settings for address range 0 are C_IPIFBAR_0 = 0x12340000, C_IPIFBAR2PCIBAR_0 = 0xC0000000, C_ENDIAN_TRANSLATE_0 = 1, C_SPACETYPE_0 = 1. The address written on OPB_ABus in the first clock cycle is 0x12340000, and the data written on OPB DBus is 0x12345678. The address and data used are the values present when OPB_Select is high. The low on OPB_RNW specifies a write operation. The OPB_xferAck indicates that the write operation is processed by the OPB IPIF.

Chapter 8 discusses address translation. The address is in the address range defined by C_IPIFBAR_0/C_IPIF_HIGHADDR_0. When FRAME_N is asserted, 0xC0000000 is written to the PCI AD[31:0] pins, and a Memory Write (0x7) is asserted. This is the high order bit translation defined by C_IPIFBAR2PCIBAR_0. Following the address, the data 0x12345678 is output the AD pins when IRDY_N is asserted. The OPB_DBus signals are in OPB_DBus[0:31] format, and the PCI data signals in AD[31:0]. The target asserts DEVSEL_N and TRDY_N to accept data.

Figure 7-13: v3 Initiator Write Transfer


0000 0111

0111 0000 0000

F 0 7 0 F

HHHH 0000 HHHH

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

AD_IO

CBE_IO

FRAME_I0

TRDY_IO

IRDY_IO

STOP_IO

M_ADDR_N

M_SRC_EN

M_READY

REQUEST

COMPLETE

M_WRDN

M_CBE

DEVSEL_IO

DEVSEL_NUG241_7-13_040506




In Figure 7-15, C_IPIFBAR_1 = 0xABCDE000 and C_IPIFBAR2PCIBAR_1 = 0xA0000000. C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 = 0. This is written to address range 1. When FRAME_N is asserted, CBE is 0x7 to specify a memory write. The address written to AD is 0xA0000000. The 0x12345678 on OPB_DBus is transmitted as 0x78563412 on AD[31:0]. When data is written to AD[31:0], the v3 asserts IRDY_N. The target responds by asserting TRDY_N and DEVSEL_N.

Figure 7-14: OPB to PCI Single Write to Address Range 0

Figure 7-15: OPB to PCI Single Write to Address Range 1

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

PB_xferAck

OPB_select

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_O

GNT_I

12340000 00000000

12345678 00000000

0 F 0

FFFFFFFF 00004008 C0000000 12345678 FFFFFFFF

F 0 7 0 F

UG241_7-14_0405

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_O

GNT_I

F 0 7 0 F

UG241_7-15_04050

FFFFFFFF A9C8B2E2 A0000000 78563412 FFFFFFFF

0 F 0

ABCDE000 00000000

12345678 00000000




Figure 7-16 shows a OPB to PCI write transaction of a half word. The address written to OPB_ABus is 0x12340002. The OPB BE is 0011. On the PCI Bus, the memory write (0x7) on CBE[3:0] is followed by 0xC to indicate the byte enables. The OPB_BE format is OPB_BE[0:3]. The CBE format is CBE[3:0], so 0x3 is equivalent to 0xC.

Figure 7-17 shows the OPB signals in a burst write on the OPB from address 0x12340000. Subsequent addresses are incremented by 4. The OPB to PCI burst write is similar to the single write, except OPB_SEQADDR is high. OPB_RNW is low and OPB_SELECT is high.

Figure 7-16: OPB to PCI Single Halfword Write

Figure 7-17: OPB to PCI Burst Write Transaction

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

PB_xferAck

OPB_select

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_O

GNT_I

12340000 00000000

12341212 00000000

0 C 0


F E 7 3 F

UG241_7-16_0405

kOPB_Cl

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N UG241_7-17_040506

00000000 12340000

00000000 90ABCDEF

FFFFFFFF

F

12340010 12340014 12340018

92387CBE AC9238CF 018340C0 3298CAFC A9C8B2E2 00000000

12340030 12340034 12340038 0000000012340024 12340028 1234002C

FAC92CD5

1234001C 12340020

A398FDEC 19C923DFAEC32FB8 7291A8FC B8D32950 1039DF8A

12340008 1234000C12340004

87654321 28359183




Figure 7-18 provides the OPB and PCI signals used in an OPB to PCI burst write. The OPB signals are similar to those in Figure 7-17. On the PCI side, the starting address is output on AD followed by data. The FRAME_N is held low to indicate multiple data transfers are occuring. IRDY_N is also asserted low while data is available. The target asserts DEVSEL_N and TRDY_N during the burst write.

Figure 7-19 shows internal OPB IPIF, IPIF-v3 Bridge, and v3 signals used in an OPB to PCI write operation. The OPB IPIF provides 0xABCDE000 on Bus2IP_Addr and 0x12345678 on Bus2IP_Data. The swapped data 0x78563412 is provided out Bus2IP_data_byteswpd. The IPIF-v3 Bridge receives Bus2IP_wrreq and responds with IP2Bus_wrack. The v3 writes M_ADDR_N to the IPIF-v3 bridge to indicate an active address cycle, followed by M_DATA to indicate a data phase is in progress. The v3 M_DATA_VLD output indicates the data phase on the PCI bus is complete.

Figure 7-18: OPB to PCI Burst Write - PCI Signals

OPB_Clk

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

00000000

00000000

FFFFFFFF

F 0 7 0

FFFFFFFF

F

C0000000 87654321 2835918312345678 AEC32FB8 7291A8FC B8D32950 1039DF8A A398FDEC FAC92CD5 92387CBE AC9238CF 018340C0 3298CAFC A9C8B2E2

UG241_7-18_040506

19C923DF




Dynamic byte enable is supported in Xilinx OPB write burst operation.

Figure 7-19: OPB PCI Write with v3 Signals

OPB_Clk

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

AD_IO

CBE_IO

FRAME_I

TRDY_IO

IRDY_IO

STOP_IO

M_ADDR_N

M_SRC_EN

M_READY

REQUEST

COMPLETE

M_WRDN

M_CBE

DEVSEL_IO

DEVSEL_N

PCI_XFERACK

AD

00000000 00000000

00000000 0000000012340000 90ABCDEF

FFFFFFFF FFFFFFFF

F 0 7 0 F

HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH0000 0111

0000 HHHH

0000 0111 0000 0000

UG241_7-19_040506




Figure 7-20 shows the PCI bus, v3, and OPB IPIF signals in a OPB to PCI single and burst write transactions.

Figure 7-21 shows the FIFO write data of 0x78563412 in the first clock cycle on wr_data. The data transmitted out on rd_data and rd_data_endian_swap.

Data is loaded in the FIFO on each clock cycle in which the write request is asserted and the address decode is valid. If OPB_SeqAddr = 0, a single PCI transaction (I/O or memory Write command) is done. In OPB sequential transfers, the data is buffered and the PCI transfer is initiated when the FIFO is filled to the level defined by the parameter C_TRIG_PCI_DATA_XFER_OCC_LEVEL, or when the OPB write is completed.

Both single transfers and burst transfers are posted writes. Data is buffered in the IPIF2PCI FIFO, which has a depth defined by the parameter C_IPIF2PCI_FIFO_ABUS_WIDTH. Due to the FIFO backup requirement of the v3 core, the FIFO usable buffer depth is the actual depth minus 3 words.

Abnormal Write TransactionsAbnormal transactions are discussed in Chapter Abnormal Transactions. The next two figures provide a brief introduction to OPB to PCI write abnormal transactions. To inhibit subsequent OPB to PCI write tranactions when abnormal terminations occur, set the appropriate bit in the Inhibit Transfers on Error Register. When inhibit is enabled, subsequent transactions are enabled by clearing appropriate bits in the OPB Master Error Definition register.

The OPB PCI Bridge re-issues commands when a PCI retry is asserted. To avoid an infinite series of retries, a maximum of C_NUM_PCI_RETRIES_IN_WRITES posted writes are attempted. The re-issue of the write operation on the PCI is automatic.

The OPB PCI Bridge does not support fast back-to-back PCI transactions.

Figure 7-20: OPB to PCI Single and Burst Write Transactions

AD

OPB_Clk

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

00000000 00000000

00000000 00000000

FFFFFFFF

F F 0 F

FFFFFFFF

UG241_7-20_040506




Figure 7-21: IPIF2PCI FIFO Write

F

00000000

12340000

90ABCDEF

FF

F

00000000

E2B2C8

000000

UG241_7-21_0

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

pcibar_base_hit

wr_data

rd_data

ata_endian_swap

ddress_to_v3core

addr_eq_wr_addr

rd_en

wr_clk

rd_clk

wr_en

data_n_addr

00000000 00000000

00000000 00000000

0 F 0

C 7 0

FFFFFFFF

F

0000

34123412 EFCDAB90 E2B2C8A

34123412 12341234 90ABCDEF A9C8B2E

00000000 C0000000

EFCDAB90




Figure 7-22 shows the v3 signals when an OPB to PCI write command to a target is terminated by the target. With STOP_IO asserted and TRDY_IO de-asserted, data is not transferred, and the target needs the initiator to retry the transaction.

Figure 7-22: Initiator Write Retried by Target

PCLK

AD_IO[31:0]

CBE_IO[3:0]

PAR_IO

FRAME_IO

IRDY_IO

DEVSEL_IO

TRDY_IO

STOP_IO

GNT_1

STATE

ADIO[31:0]

M_CBE[3:0]

REQUEST

COMPLETE

M_WRDN

M_ADDR_N

M_DATA

M_DATA_VLD

M_SRC_EN

M_READY

OE

LOAD

REQ_O

IDL REQ WR WRWR REQRTY

00 00 00 7

UG241_7-22_040506



OPB to PCI Read TransactionsR

Figure 7-23 shows the initiator re-issuing the original write command. The target responds with TRDY_IO asserted and STOP_IO de-asserted, so the transaction completes normally.

OPB to PCI Read TransactionsThe first part of this chapter on the registers, generics, and functional diagrams in Figure 7-1 to Figure 7-6 also applies to OPB to PCI read transactions. As with OPB to PCI write transactions, the v3 core is a PCI initiator and an OPB slave in OPB to PCI read transactions. The OPB master can be a processor, local DMA, a OPB master device, or a bridge, such as the OPB PCI Bridge. Only one OPB master read of a PCI target can be done at a time.

The read operation is the same whether the PCI space is memory or I/O space with the exception of the command sent to the v3.0 core. The C_IPIF_SPACETYPE_N generic associated with each BAR defines the address range as either I/O or memory, determining whether an I/O or memory command is asserted.

PCI commands supported in OPB master read operations are I/O read, memory read, and memory read multiple. The command used is based on the address/qualifier decode, which includes the address, memory type (e.g., I/O or memory type), if OPB_seqAddr is asserted, and the address space prefetchability.

Figure 7-23: Initiator Write Retried and Completed

LOAD

PCLK

AD_IO[31:0]

CBE_IO[3:0]

PAR_IO

FRAME_IO

IRDY_IO

DEVSEL_IO

TRDY_IO

STOP_IO

GNT_1

STATE

ADIO[31:0]

M_CBE[3:0]

REQUEST

COMPLETE

M_WRDN

M_ADDR_N

M_DATA

M_DATA_VLD

M_SRC_EN

M_READY

OE

REQ_O

RTY REQ DUN IDLWR WRWR

00 00 00 7

UG241_7-23_012306




The flow for an OPB to PCI read transaction is given in Figure 7-24. The modules used are the OPB IPIF, IPIF-V3 Bridge, and v3 core. The OPB signals are on the left. The PCI bus is on the right. These are the same signals used in OPB to PCI write transactions.

Figure 7-25 shows the OPB signals for two single read transactions by an OPB Master. The bus master outputs an address on OPB_ABus and data on OPB_DBus. Since this is a read, OPB_RNW is output high. The bus master outputs OPB_Select high. The IPIF-v3 Bridge IP2Bus_RdAck output causes the OPB_xferAck to be output high.

In actual OPB to PCI read transactions, there is latency for the data to be read.

Figure 7-26 shows the OPB signals for a sequential read. This is similar to the single read with the difference that OPB_seqAddr is output high, and multiple address/data are read on OPB_DBus. The OPB does not directly support burst modes. The sequential address

Figure 7-24: OPB to PCI Read Flow

Figure 7-25: OPB Single Read of PCI Transactions

OPB IPIF

OPB PCI

DS241_7-24_040506

IPIF- V3 Bridge

OPB_ABUSOPB_DBUSOPB_RNW

OPB_SEQADDROPB_BE

OPB_SELECT

BUS2IP_ADDR BUS2IP_DATA BUS2IP_RNW

BUS2IP_BURST BUS2IP_WRCE

IP2BUS_WRACK IP2BUS_RETRY

IP2BUS_TOUTSUP

INHIBIT_FAF_WRITES

V3

ADIO REQUEST

COMPLETE M_READY M_WRDN M_CRE

ADCBEFRAME_NTRDY_NIRDY_NSTOP_NDEVSEL_N

M_DATA_VALID M_DATA

M_ADDR_N M_SRC_EN

OPB_CLK

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_RNW

OPB_Select

OPB_xferAck


DS241_7-25_040506




allows slaves to achieve burst-like response. The next transfer is to the next sequential address in the same direction. M_busLock must be asserted during sequential transactions.

Figure 7-27 shows the signals from the OPB IPIF to the IPIF-v3 Bridge for OPB read operations to registers in the IPIF-v3 Bridge. Two words are read on IP2Bus_Data. The IPIF-v3 Bridge uses the Bus2IP_RdCE(i) signals to enable registers. The IPIF-v3 Bridge responds with IP2Bus_RdAck for data D1, D2, and D3. The acknowledge is delayed for data D2, so IP2Bus_Toutsup is asserted. There is an error for data D3 and a retry for data.

Note: Bus transactions are transmitted using the FIFOs, not using a register.

In Figure 7-28, the initiator with a read transfer requirement requests ownership of the bus by asserting REQ_N (not shown). The arbiter grants access with GNT_N. Once GNT_N is received, the initiator waits until the bus is idle, as indicated by a high on the FRAME_N and IRDY_N pins.

On the first clock, the initiator drives the address on AD[31:0] and the command on CBE[3:0]. FRAME_N is asserted. Each target samples the address on AD, command on CBE[3:0], and FRAME_N to determine if it is the target.

In the second clock, the initiator asserts IRDY_N to indicate that it is ready to read data. The initiator also quits driving AD[31:0]. In read operations, the initiator drives AD with the read address, followed by the target driving the bus with read data. A turnaround cycle

Figure 7-26: OPB Sequential Read of PCI transaction

Figure 7-27: IPIF Register Read Signals

DS241_7-26_040506

OPB_CLK

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_RNW

OPB_Select

OPB_xferAck

OPB_seqAddr

0ns 50ns 100ns

Bus2IP_Clk

Bus2IP_RdCE(i)

Bus2IP_RdReq

IP2Bus_Data

IP2Bus_Toutsup

IP2Bus_RdAck

IP2Bus_Error

IP2Bus_Retry

Annotation

D1 0 D2 0 0 0

read

read w/timeout supression UG241_7-27_040506




is used in clock 2 to avoid bus contention. FRAME_N is de-asserted to indicate that this is the last data written, i.e., that this is a single read transfer.

In clock cycle 3, the initiator drives the byte enables on CBE[3:0]. The addressed target asserts DEVSEL_N and TRDY_N to indicate that it is ready for the transaction. Data is read from the target when IRDY_N and TRDY_N are asserted. When the transaction is complete, the initiator de-asserts IRDY_N. The target de-asserts TRDY_N and DEVSEL_N, and quits driving AD[31:0].

In Figure 7-29, the burst read transaction begins with signal transitions similar to that of a single read transaction. The initiator requests and gains access to an idle PCI bus. In the first clock cycle, the initiator asserts FRAME_N, and provides the address on AD[31:0] and the command on CBE[3:0]. In clock cycle 2, the initiator asserts IRDY_N to indicate it is ready to read data. When FRAME_N is asserted, targets decode the address and command. As with the single PCI read, clock cycle 2 is a turnaround cycle, so the initiator quits driving AD[31:0].

In clock cycle 3, the target asserts DEVSEL_N and TRDY_N asserted. Here the first difference with the single read transfer occurs. The initiator keeps FRAME_N asserted, indicating that it is not the last data to be read. The initator only writes the first address in a burst transaction. Each target contains an address counter which increments the start address provided on AD[31:0] by 4 to determine the address of the next DWORD.

If TRDY_N and IRDY_N are both asserted, the read burst of data occurs without wait states. If the initiator or target needs additional time to generate/receive data, IRDY_N and/or TRDY_N are de-asserted to insert wait states.

The initiator indicates the last data of the burst by de-asserting FRAME_N. The end of the burst does not occur until IRDY_N and TRDY_N are de-asserted. The target quits driving AD[31:0]

The next figures show read transactions using the v3 core signals, and the PCI bus and IPIF-v3 Bridge interface are given.

Figure 7-28: PCI Single Read

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_N


UG241_7-28_040506




Figure 7-30 shows a single read. The REQUEST is generated from the IPIF-v3 Bridge which causes the v3 core to generate REQ_N. The IPIF-v3 Bridge writes a 0x6 memory read command on M_CBE[3:0]. After gaining access to the PCI bus, the v3 core asserts FRAME_N for one clock cycle. Each target decodes the address and CBE[3:0] to determine if it is to provide read data. In the next clock cycle IRDY_N is asserted. The AD_IO has a turnaround cycle. In the next clock cycle, the target asserts DEVSEL_N and TRDY_N, and provides read data on AD[31:0]. The read operation completes when the target de-asserts DEVSEL_N and TRDY_N, and stops driving AD[31:0].

During initiator reads, the v3 transfers burst data using a pipelined data path. The data valid signal, M_DATA_VLD, is used to advance the initiator address pointer.

Figure 7-29: PCI Burst Read

n

UG241_7-29_040506

0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

IRDY_N

TRDY_N

DEVSEL_N




An initiator burst read is shown in the waveform of Figure 7-31. This waveform includes both PCI Bus signals and internal IPIF-v3 Bridge signals. In this figure, the initiator address pointer is implemented to provide a local pointer to index storage elements. During initiator reads, this pointer is incremented when M_DATA_VLD is asserted.

M_CBE is written as 0xC for a memory read multiple. FRAME_N is held asserted to define the length of the burst.

Figures 32 through 35 show the full OPB PCI Bridge signals, including internal signals.

Figure 7-30: v3 Signals in a Single Memory Read

00004008 C0000000 FFFFFFFF 87654321

UG241 7-30 040506

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_N

GNT_N

complete

m_wrdn

m_ready

m_src_en

m_data_vld

m_cbe

request

m_data

m_addr_n

00000000 12340000 0000000

00000000 00000000

0 F 0

FFFFFFFF FFFFFFFF

F 0 6 0 F

0000 0110 0000




Figure 7-32 is an OPB to PCI read transaction.The generic settings for address range 0 are C_IPIFBAR_0 = 0x12340000, C_IPIFBAR2PCIBAR_0 = 0xC0000000, C_ENDIAN_TRANSLATE_0 = 1, C_SPACETYPE_0 = 1. The address written on OPB_ABus in the first clock cycle is 0x12340000. OPB_Select output high. The high on OPB_RNW specifies a read operation. The OPB_xferAck indicates that the read operation is processed by the OPB IPIF. The address is in the address range defined by C_IPIFBAR_0/C_IPIF_HIGHADDR_0. Access to the PCI bus is granted.When FRAME_N is asserted, the translated address 0xC0000000 is written to the PCI AD pins. This is the high order bit translation defined by C_IPIFBAR2PCIBAR_0. The target recognizes its address and the memory read command, asserts TRDY_N and 0x87654321 output data.

Figure 7-31: v3 Signals in a Burst Memory Read

00000000

FFFFFFFF A0000000 FFFFFFFF 78563412 210F9CA3 4F933C92 DF312859

UG241_7-31_040506

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_N

GNT_N

complete

m_wrdn

m_ready

m_src_en

m_data_vld

m_cbe

request

m_data

m_addr_n

ABCDE000 00000000

00000000 00000000

0 F 0


F 3 C 0 F

0000 1100 0000




Figure 7-33 is an OPB to PCI halfword read transaction. The address written on OPB_ABus in the first clock cycle is 0x12340002. The value 0x0010 is output OPB_BE[0:3]. OPB_Select and OPB_RNW are output high. PCI Bus access is requested and granted. The address 0xC0000000 is transmitted out AD[31:0] when FRAME_N is asserted. The value 0x1101 is output CBE[3:0]. IRDY_N is asserted to indicate the initiator is ready to receive data. The

Figure 7-32: OPB to PCI Single Read Transaction

0000

00004008 C0000000 FFFFFFFF 87654321

0000

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_N

GNT_N

bar_base_hit

12340000 000000

00000000 0000000

0 F 0

FFFFFFFF FFFFFFFF

F 0 6 0 F

UG241 7-32 0405




target asserts DEVSEL_N and TRDY_N, and provides 0x00008700 on AD. The 0x00008700 is output OPB_DBus.

Figure 7-34 shows an OPB to PCI burst read transaction to address range 0. A 0x12340000 is output OPB_ABus, and OPB_Select, OPB_RNW, and OPB_SeqAddr are output high. The initiator requests and gains access to the PCI bus. When FRAME_N is asserted, 0xC0000000 is output AD[31:0]. In the next clock cycle, the initiator indicates it is ready to

Figure 7-33: OPB to PCI Halfword Read Transaction

00000000

UG241_7-33_040606

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_N

GNT_N

pcibar_base_hit

12340000

00000000

0 C 0

00000000

00000000

FFFFFFFF FFFFFFFF

F E 6 3 F

0000

FFFFFFFF C0000000 FFFFFFFF 87650000




receive data by asserting IRDY_N. The target generates DEVSEL_N and TRDY_N, and writes read burst data to AD[31:0]. The read burst data is output OPB_DBus[0:31].

Figure 7-35 shows an OPB to PCI burst read transaction to address range 1. The transactions in this figure are the same as those in Figure 7-34 except for the generics used: C_IPIFBAR_1 = 0xABCDE000 and C_IPIFBAR2PCIBAR_1 = 0xA0000000.

Figure 7-34: OPB to PCI Burst Read Transaction to Address Range 0

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_N

GNT_N

bar_base_hit

FFFFFFFF 00000000

F C 0

0000

12340000

00000000

0 F 0

12340004 12340008 1234000C 12340010 12340014 12340018 1234001C 12340020 00

00

FFFFFFFF C0000000 FFFFFFFF 12345678 A39C0F21 BCF9E203 7CD02A24 549CCEFA 923C934F 8371C0BA EF9AC3CB 592831DF

UG241 7 34 040




C_IPIFBAR_ENDIAN_TRANSLATE_EN_1 = 0. The master writes 0xABCDE000 to OPB_ABus. The address output AD[31:0] is 0xA0000000.

Address TranslationThe address presented on the OPB is translated to the PCI address space by high-order bit substitution with the 2 least significant bits (LSBs) set as follows. If the target PCI address space is memory space, the 2 LSBs are set to 00, i.e., linear incrementing mode. If the PCI target address space is I/O-space, the 2 LSBs are passed unchanged from that presented on the OPB bus.

FIFO Operation and Prefetchable DataIn a read operation, the PCI2IPIF FIFO is used rather than the IPIF2PCI FIFO. Figure 7-36 is a functional diagram of the PCI2IPIF FIFO.

Figure 7-35: OPB to PCI Burst Read Transaction to Address Range 1

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

REQ_N

GNT_N

pcibar_base_hit

FFFFFFFF

F 3 C 0 F

0000

ABCDE000 00000000

00000000 00000000

0 F 0

00000000

FFFFFFFF

A0000000

FFFFFFFF

78563412

210F9CA3

03E2F9BC

242AD07C

FACE9C54

4F933C92

BAC07183

CBC39AEF

DF312859

00000000

ABCDE004

FFFFFFFF

UG241_7-35_040506




If the transaction is an OPB burst transaction, the OPB PCI Bridge writes a memory read multiple command on CBE[3:0], and begins filling the PCI2IPIF FIFO. Throttling by the OPB PCI Bridge supplying data to the OPB master is done by delaying acknowledgements until the data is loaded in the FIFO. Because the PCI bus is usually slower than the OPB, significant throttling time can occur. If the PCI2IPIF FIFO fills or the Latency Timer expires, the OPB PCI Bridge terminates the prefetch read operation. The prefetch read operation can be terminated by the PCI target as well.

C_TRIG_PCI_READ_OCC_LEVEL specifies the number of words in the FIFO below which the OPB PCI Bridge starts prefetch reads of the PCI target. The OPB PCI Bridge prefetches consecutive data when new read operations are intitiated.

If the PCI2IPIF_FIFO empties before data is prefetched, an OPB time-out occurs. When the OPB master terminates the transaction with data remaining in the FIFO, the FIFO is flushed. Because the data is required to be prefetchable, data is not lost when the FIFO is flushed. With prefetchable data sources, such as RAM or a register file, the data can be discarded. The original data remains in the RAM or the register file for future use.

For non-prefetchable data sources, as a FIFO, popping data from the FIFO may be destructive. The unused data must be restored in the FIFO. This requires counters or keeping a shadow copy of the previous data values.

Conditions requiring “back up” occur when the target signals a disconnect, terminating the transaction before the initiator is able to complete the full transfer. The FIFO control logic uses control signal to back up, or “undo” reads. The PCI2IPIF FIFO consists of dual port BRAM, a read pointer, and a write pointer. Back up in the PCI2IPIF FIFO uses a FIFO with an actual depth three less than the maximum possible, and by using a bidirectional read pointer. This prevents new data entering the FIFO from overwriting data in the FIFO that may need to be restored.

The FIFO has a set of flags that provide FIFO status information. The general functionaity of the flag is listed below. The actual flags used in the OPB PCI Bridge are given in Figure 7-6.

Figure 7-36: PCI2IPIF FIFO

ENDIANSWAP

PCI2IPIF_FIFO_CNTL

IPMASTER

WRITE_ABUSWR_ADVANCED_STRB

FIFO_RESET_WR_CLK

Wr_eq_RD_mns3_PCI2IPIFWr_mnsTrg_LT_Rd_WrsideWr_GE_Rd_plsTrg_Rdside

WR_CLK

WR_DATA

READ_ABUS

Rd_BE

Rd_Data_Endian_swapWR_DATA_

and_BE

READ_CLK

Rd_advance_strbRd_EQ_Wr_Rdside



RD_RSTRD_CLK

RD_ENABLE

RD_DATA

UG241_7-36_040506




• Totally Empty. If the IPIF2PCI FIFO is totally empty and an initiator write transaction is requested, the OPB PCI Bridge ignores the request.

• Totally Full. If the PCI2IPIF FIFO is totally full and an initiator read transaction is requested, the OPB PCI Bridge ignores the request.

• Almost Empty. When the IPIF2PCI FIFO is almost empty during an initiator write, the IPIF-v3 Bridge signals it to complete the transaction because it is about to underrun the FIFO.

• Almost Full. When the PCI2IPIF FIFO is almost full during an initiator read, the IPIF-v3 Bridge signals it to complete the transaction because it is about to overrun the FIFO.

For designs with transfer lengths less than or equal to the FIFO size, it is not necessary to monitor the FIFO status flags.

For transfer lengths greater than the FIFO size, the flags are important. In this case, there are two “terminating” conditions. One occurs when the transfer is complete, as determined by the transfer counter, and the other occurs when the FIFO becomes almost full (initiator read) or almost empty (initiator write). In the second case, the FIFO must be emptied (initiator read) or refilled (initiator write) by logic in the IPIF-v3 Bridge before it requests another transaction to continue the transfer.

Abnormal TransactionsWhen an abnormal transaction termination occurs, a bit is set in the OPB Master Error Definition register. Subsequent OPB master read operations can be inhibited by enabling the inhibit feature for OPB master read operations in the Inhibit Transfers on Error register.

Upon an abnormal termination, the bit in the OPB Master Error Definition register that is set must be cleared to enable the OPB read of PCI target operation.



R

Chapter 8

Address Translation

This chapter discusses OPB to PCI and PCI to OPB address translation. An address range is a set of contiguous addresses defined by a base and high address, used to read and write memories or registers

Registers and GenericsThere are six OPB to PCI address ranges which can be translated. The generics which define the translation are C_IPIFBAR_n, C_IPIF_HIGHADDR_n, C_IPIFBAR2PCIBAR_n, C_IPIFBAR_ENDIAN_TRANSLATE_EN_n, C_IPIF_PREFETCH_n, and C_IPIF_SPACETYPE_n, with n=0 to 5. In OPB to PCI translations, C_INCLUDE_BAROFFSET_REG determines whether C_IPIFBAR2PCIBAR_n or the IPIFBAR2PCIBAR register(s) defines the high order substitution used in address translation.

There are three PCI to OPB address ranges which can be translated. The generics which define the translation are C_PCIBAR_m, C_PCIBAR_LEN_m, C_PCIBAR2IPIFBAR_m, C_PCIBAR_ENDIAN_TRANSLATE_EN_m, C_IPIF_PREFETCH_m, and C_PCI_SPACETYPE_m, with m=0 to 2. C_PCIBAR2IPIFBAR_n defines the high order substitution used in PCI to OPB address translation.

The set of generics for the OPB to PCI and PCI to OPB address ranges are independently configured.

C_IPIFBAR_ENDIAN_TRANSLATE_EN_n and C_PCIBAR_ENDIAN_TRANSLATE_EN_m are used to translate doublewords. This allows a memory location to be read with the same value by both an OPB master and a PCI initiator. This requires bytes to be swapped in the address translation. With endianess



Chapter 8: Address TranslationR

translation enabled, a word is transferred unaltered from one bus to the other. By default, endian translation is disabled.

Figure 8-1 illustrates the address translation requirement in the context of a Xilinx motherboard, which uses a Virtex-4 device, and has 4 PCI slots. PCI Boards based on FPGAs such as the Spartan series can be inserted into a PCI slot. On the Virtex-4 based motherboard, the PPC has direct access to PLB BRAM, PLB DDR, and PLB DDR2 memory as defined by the addresses in the system.mhs. To access the BRAM and SDRAM on the Spartan-3E based card, address translation is required, since the daughterboard addresses are defined by the addresses in the system.mhs which defines the Spartan-3E based design. The MicroBlaze in the Spartan-3E addresses the OPB BRAM and OPB SDRAM directly as defined in the system.mhs for the Spartan-3E. To access the BRAM and DDR2 in the Virtex-4 motherboard address space, address translation is required.

Figure 8-2 shows the signals used in PCI to OPB address translation.

If a PCI initiator needs to access memory in the OPB address space, the address must be translated. The number of address ranges (C_PCIBAR_NUM) which can be translated is 1-3. Each address range has parameters for base address (C_PCIBAR_n), high address (C_PCIBAR_LEN_n), address translation (C_PCIBAR2IPIFBAR_n), endianess translation (C_PCIBAR_ENDIAN_TRANSLATE_EN_n), prefetch enable (C_IPIF_PREFETCH_n), and the memory designator (C_PCISPACETYPE_n).

Figure 8-1: Address Translation Requirement

Figure 8-2: pci2ipif_addr_translate Block Diagram

UG241_8-1_0411

PPC

PCIPLB

BRAM

Virtex™-4

OPB PCIBridge

MB

OPBBRAM

Spartan™-3E

OPB PCIBridge

PLBDDR2

OPBSDRAM

V3Addr[31:0]

PCI2IPIF_Addr_translate[0:31]

Base_hit_regd[0:31]

UG241_8-2_041106



Address Translation Using High Order Bit SubstitutionR

The C_PCIBAR2IPIFBAR_n values are loaded into the Configuration Header at C_BASEADDR + offsets 0x10, 0x14, 0x18. The space type and prefetchability must be mirrored in the PCI configuration registers.

Figure 8-3 is a block diagram of the ipif2pci_addr_translate module. The six IPIFBAR2PCIBAR generics are loaded into the OPB PCI registers located at the OPB PCI Bridge C_BASEADDR + 180h - 194h.

If an OPB Master needs access to memory in the PCI address space, the address must be translated. The number of address ranges (C_IPIFBAR_NUM) is 1-6. Each address range has parameters for base address (C_IPIFBAR_n), high address (C_IPIF_HIGHADDR_n), address translation (C_IPIFBAR2PCIBAR_n), endianess translation (C_IPIFBAR_ENDIAN_TRANSLATE_EN_n), prefetch enable (C_IPIF_PREFETCH_n), and the memory designator (C_IPIF_SPACETYPE_n).

Address Translation Using High Order Bit SubstitutionIn address translation in both directions, high-order address bits are substituted. In an OPB to PCI address translation, the number of high-order bits substituted is the number of bits in C_IPIFBAR_N and C_ IPIF_HIGHADDR_N that are the same. In a PCI to OPB address translation, the number of high-order bits substituted is the bus width minus C_PCIBAR_LEN_N. The low-order bits are transferred unchanged.

Figure 8-3: ipif2pci_addr_translate Block Diagram

IPIFBAR2PCI_0[0:31]IPIFBAR2PCI_1[0:31]IPIFBAR2PCI_2[0:31]IPIFBAR2PCI_3[0:31]IPIFBAR2PCI_4[0:31]IPIFBAR2PCI_5[0:31]

Bus2IP_Addr_translate[0:31]

Bus2IP_Addr_in[0:31]Brdg_xfer_CE_vector_regd[0:5]

UG241_8-3_041106

Figure 8-4: OPB to PCI Address Translation

C_IPIFBAR2PCIBAR_0

IPIFBAR2PCIBAR_0PCI Address AD[31:0]

OPB_ABus[0:31]

C_INCLUDE_BAROFFSET_REG

UG241_8-4_041106




Figure 8-4 is a functional diagram of the OPB to PCI Address translation. C_INCLUDE_BAROFFSET_REG is used to select whether the generic or register is used in the high order bit substitution.

Figure 8-5 is a functional diagram of the PCI to OPB Address translation. C_INCLUDE_BAROFFSET_REG is not used in this translation.The high order bits are substituted and the low order bits are translated unchanged.

Figure 8-5: PCI to OPB Address Translation

PCIAddress_AD[31:0]

C_PCIBAR2IPIFBAR_0 OPB_ABus[0:31]

C_PCIBAR_LEN_0UG241_8-4_041106




In Figure 8-6, C_INCLUDE_BAROFFSET_REG = 0, C_IPIFBAR_0 = 0x12340000, C_IPIFBAR2PCIBAR = 0xC0000000, and C_ENDIAN_TRANSLATE_EN_0 = 1. The address on OPB_ABus is 0x12340000, and the data on OPB_DBus is 0x12345678. When FRAME_N is asserted on the PCI bus, CBE[3:0] = 0x7 indicating a memory write, and the address on AD[31:0] is 0xC0000000. In the next clock cycle, with IRDY_N active, data on AD[31:0] is 0x12345678.

As a second example using the above generics with C_IPIFBAR2PCIBAR_0 = 0x5671XXXX, an OPB address OPB_ABus = 0x12340ABC is translated to an AD[31:0] = 0x56710ABC.

Figure 8-6: OPB to PCI Address Translation - Address Range 0

F

C_IPIFBAR_0

C_IPIF_HIGHADDR_0

C_IPIFBAR2PCIBAR_0

C_ENDIAN_TRANSLATE_EN_0

C_IPIF_SPACETYPE_0

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

12340000

1234FFFF

C0000000

1

1

00000000

12340000 00000000

00000000

12345678 00000000

0 F 0

FFFFFFFF

F 0 7 0 F

UG241_8-6_041106

00004008 C0000000 12345678 FFFFFFFF




In Figure 8-7, C_INCLUDE_BAROFFSET_REG = 0, C_IPIFBAR_0 = 0xABCDE000, C_IPIFBAR2PCIBAR = 0xA0000000, and C_ENDIAN_TRANSLATE_EN_0 = 0. The address on OPB_ABus is 0xABCDE000, and the data on OPB_DBus is 0x12345678. When FRAME_N is asserted on the PCI bus, CBE[3:0] = 0x7 indicating a memory write, and the address on AD[31:0] is 0xA0000000. In the next clock cycle, data on AD[31:0] is 0x78563412.

As a second example using the above generics with C_IPIFBAR2PCIBAR_1 = 0xFEDC0XXX, an OPB_ABus = 0xABCDF123 is translated to an AD[31:0] = 0xFEDC1123.

Figure 8-7: OPB to PCI Address Translation - Address Range 1

UG241_8-7_041106

C_IPIFBAR_1

C_IPIF_HIGHADDR_1

C_IPIFBAR2PCIBAR_1


C_IPIF_SPACETYPE_1

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

AD

CBE

ABCDE000

ABCDEFFF

A0000000

0

1

00000000

12345678 00000000

0 F 0

ABCDE000

FFFFFFFFA9C8B2E2

A0000000

78563412

FFFFFFFF

F 0 7 0 F F




In Figure 8-8, C_PCIBAR_0 = 0x00001000, C_PCIBAR2IPIFBAR = 0x00010000, and C_ENDIAN_TRANSLATE_EN_0 = 0. C_INCLUDE_BAROFFSET_REG is not used in PCI to OPB address translations. The address on AD[31:0] is 0x00001000. In the next clock, the data on AD[31:0] is 0x12345678. When OPB_Select is asserted on the OPB, the address on OPB_ABus is 0x00010000. Data on OPB_DBus is 0x12345678.

As a second example using the above generics with C_PCIBAR_0 = 0xABCDE800 and C_PCIBAR2IPIFBAR_0 = 0x123450XX, the PCI address AD[31:0] = 0xABCDEFF4 is translated to an OPB_ABus = 0x123457F4.

Figure 8-8: PCI to OPB Address Translation - Address Range 0

FFFFFFFF

00001000

00010000

12345678

t0000

C_PCIBAR_0

C_PCIBAR_LEN_0

C_PCIBAR2IPIFBAR_0

ENDIAN_TRANSLATE_EN_0

C_PCI_SPACETYPE_0

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

pcibar_base_hi

00001000

5

00010000

0

1

78563412 FFFFFFFF

F 7 0 F

00000000 00000

00000000 00000

0 F 0

0000 1000

UG241_8-8_0411




In Figure 8-9, C_PCIBAR_0 = 0x00002000, C_PCIBAR2IPIFBAR = 0x00020000, and C_ENDIAN_TRANSLATE_EN_0 = 1. The address on AD[31:0] is 0x00002000, and the data on OPB_DBus is 0x12345678. When FRAME_N is asserted on the PCI bus, CBE[3:0] = 0x7 indicating a memory write, and the address on OPB_ABus is 0x00020000. Data on OPB_DBus is 0x12345678.

As a second example using the above generics with C_PCIBAR_1 = 0x12000000 and C_PCIBAR2IPIFBAR_0 = 0xFEXXXXXX, the PCI address AD[31:0] = 0x1235FEDC is translated to OPB_ABus = 0xFE35FEDC.

Figure 8-9: PCI to OPB Write Address Translation - Address Range 1

00020000

12345678

UG241_8-9_04110

C_PCIBAR_1

C_PCIBAR_LEN_1

C_PCIBAR2IPIFBAR_1


C_PCI_SPACETYPE_1

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

OPB_CLK

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

pcibar_base_hit

00002000

9

00020000

1

1

00002000 12345678 FFFFFFFF

F 7 0 F

00000000

00000000

0 F

0000 0100



R

Chapter 9

Abnormal Terminations

This chapter discusses abnormal terminations of PCI bus transactions. These include Master Abort, Target Abort, Disconnect with Data, Disconnect without Data, and Retry. In some abnormal terminations, data is transferred without error. Other abnormal terminations are errors. This chapter should be read with Chapter 10 Error Conditions, which deals with PCI parity and system errors, and then discusses errors in the context of more general conditions, including OPB errors and abnormal terminations.

Registers and GenericsC_NUM_PCI_RETRIES_IN_WRITES is the maximum number of PCI retries in posted write transactions. C_NUMPRD_RETRY_AFTER_PCIWRRETRY is the number of PCI clock periods that OPB master operations are retried after a PCI retry. This allows a PCI write transaction which is a retry to complete. C_NUM_PCI_PRDS_BETN_RETRIES_IN WRITES is the number of PCI clock periods between retries in posted write operations.

Table 9-1 is the status register in the Configuration Header. The abnormal terminations are described in the remainder of this chapter. The Signaled Target Abort and Signaled System Error are set by the target device. The Received Target Abort and Received Master Abort are set by the bus master.

Table 9-1: Status Register

Bit R/W Function

3:0 Reserved

4 R Capabilities List

5 R 1 - Device can run at 66 MHz0 - Device cannot run at 66 MHz

6 Reserved

7 R Fast Back to Back Capable. Hardwired to 0.

8 R/W Master Data Parity Error

10:9 R DEVSEL_N Timing

00 - Fast01 - Medium10 - Slow11 - Reserved

11 R/W Signaled Target Abort



Chapter 9: Abnormal TerminationsR

Abnormal Target TerminationsA target uses DEVSEL_N, TRDY_N, and STOP_N to end PCI bus transactions with Disconnect with Data, Disconnect without Data, Retry, and Target Abort terminations. Disconnect with Data is used by a target to indicate to the initiator that the current data transfer is valid but the next data transfer cannot occur. This differs from the Disconnect without Data termination in which the current transaction does not occur. In a Retry, no data is transferred, and the initiator is required to retry the transaction. In a Target Abort, the target indicates to the master that no data can be transferred, and the initiator should not retry the transaction later.

There are four reasons a target signals a Disconnect with Data. A Disconnect with Data is signaled if the target does not support burst transactions, if the target is unable to transfer data in 8 clocks (except in the first data phase), if the memory addressing as defined in AD[1:0] isn’t linear, or if the data transfer is not within its address range.

In Disconnect with Data, TRDY_N, STOP_N, and DEVSEL_N are all asserted. Keeping DEVSEL_N asserted allows the initiator to optionally resume the transaction later, at the point it is disconnected.

The two types of Disconnect with Data are Disconnect A and Disconnect B. The OPB PCI Bridge will react the same way to both of these disconnect types.

Figure 9-1 shows a Disconnect with Data A. The Disconnect with Data is signaled when IRDY_N is de-asserted.

12 R/W Received Target Abort

13 R/W Received Master Abort

14 R/W Signaled System Error

15 R/W Detected Parity Error

Table 9-1: Status Register (Continued)

Bit R/W Function

Figure 9-1: Disconnect with Data A

s0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160n

PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_NUG241_9-1_041106



Abnormal Target TerminationsR

Figure 9-2 shows a Disconnect with Data B. The Disconnect with Data B is signaled when IRDY_N is asserted.

The two types of Disconnect without Data are Type 1 and Type 2. In both, the target asserts STOP_N and DEVSEL_N, and de-asserts TRDY_N. The difference in Type 1 and Type 2 is the state of the IRDY_N. As with the Disconnect with Data termination, the initiator can optionally resume the transaction later.

Figure 9-3 shows a Disconnect without Data Type 1 in which IRDY_N is asserted.

Figure 9-4 shows a Disconnect without data Type 2 in which IRDY_N is de-asserted.

A Disconnect without Data differs from a Retry in that the initiator has the option to rearbitrate for the bus to retry the transaction. It is optional for the initiator to retry on

Figure 9-2: Disconnect with Data B

Figure 9-3: Disconnect without Data Type 1

Figure 9-4: Disconnect without Data Type 2


PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_NUG241_9-2_041106


PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_NUG241_9-3_041106

s

PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N

0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160n

UG241_9-4_041106




Disconnects because it may have been doing a prefetch which isn’t necessary to complete. A Retry requires the initiator to retry the transaction.

The PCI Specification requires that the first data phase be transferred within 16 clocks for initiators. The requirement is 32 clocks if the initiator is also a host bridge. A target signals a retry if it cannot meet this requirement. The signaling for a Retry is identical to that of Disconnect without Data. STOP_N and DEVSEL_N are asserted, and TRDY_N is de-asserted. The difference in signaling is that a Retry termination occurs on the first data phase in a transaction, while Disconnect without Data termination occurs on data phases which follow the first data phase.

A Retry termination is used if the target is too slow to complete the first transaction in 16 clocks, the bridge is locked, or if the target is busy with another function at the time of the transaction. When a Retry is received, the initiator is required to retry the transaction using the same address, command, byte enables, etc., as the original transaction.

Figure 9-5 shows the target signaling a Retry with IRDY_N asserted.

Figure 9-6 shows a target signaling a Retry with IRDY_N de-asserted.

The number of retries is limited. After C_NUM_PCI_RETRIES_IN WRITES is reached, the transaction on the PCI bus is allowed to complete. If the transaction is a read, the bridge responds with 0xFFFFFFFF. If the transaction is a write, the bridge allows the transaction to occur without generating a Retry termination. This allows the processor to handle the problem causing the Retry.

There are four reasons a target signals a Target Abort termination. A Target Abort termination is signaled if there is an addressing error, if the target is not functional, if there

Figure 9-5: Retry with IRDY_N Asserted

Figure 9-6: Retry with IRDY_N Not Asserted

n

UG241_9-5_041106

0ns 50ns 100ns 150ns 200

PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N

n

UG241_9-6_041106

0ns 50ns 100ns 150ns 200

PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N




is an address phase parity error, or if there is a Master Abort on the other side of a PCI to PCI Bridge. When Target Abort occurs, the initiator sets the Received Target Abort bit and the target sets the Signaled Target Abort bit, both in the Configuration Header’s Status Register.

As shown in Figure 9-7, to signal a Target Abort, the target asserts STOP_N and de-asserts TRDY_N and DEVSEL_N. DEVSEL_N is de-asserted earlier than in the Disconnect without Data termination. When an initiator receives a Target Abort, it either generates an interrupt so the OPB PCI driver can check the status of the transaction, or asserts SERR_N.

.

The IPIF-v3 Bridge uses the S_TERM and S_READY signals to control v3 target terminations as summarized in Table 9-2. The table defines four conditions. The Wait condition inserts wait states at the beginning of a PCI Bus transaction by delaying the assertion of TRDY. This delays the first data phase. The Normal condition allows PCI Bus data phase(s) to complete without the insertion of extra wait states or termination by the target. The Disconnect without Data condition terminates the current PCI Bus transaction without data transfer on the final data phase. A Disconnect without Data on the first data phase is

Figure 9-7: Target Abort

Table 9-2: Data Phase Control Signals for Targets

Condition TRDY_N DEVSEL_N STOP_N S_TERM S_READY

Wait 1 0 1 Low Low

Normal 0 0 1 Low High

Disconnect Without Data

(Retry)

1 0 0 High Low

Disconnect With Data

0 0 0 High High

UG241_9-7_041106


PCI_CLK

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N




equivalent to a Retry. The Disconnect with Data condition terminates the current PCI Bus transaction with data transfer on the final data phase.

In Figure 9-8, the initiator writes CBE[3:0] = 0x7 to indicate a memory write transaction, and FRAME_N is asserted for a two doubleword burst transaction. The address written to AD[31:0] is 0xC0000000. In the next clock, IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target signals a Disconnect with Data by asserting TRDY_N, DEVSEL_N, and STOP_N. Since IRDY_N is asserted, this is a Disconnect with Data B.

Figure 9-8: Disconnect with Data on OPB to PCI Write Transaction

1

F

00004008 C0000000 12345678 87654321 FFFFFFFF

F 7 0 F

1

0000

12340088 12340090 12340098

1234009C

123400A0

123400A4

123400A8

123400AC

123400B0

123400B4

123400B8

123400BC

123400C0123400C4

25908D3B

D8FA0391

FEDC398A

2D3F9C91

2DC5AC9F

7BCE2389

3C8FC92A

4C001830

CFAC2983

BE229C8A

29DF3A87

12340084 1234008C57682341 98138352

9AC923F3 42317658 2BF8EC3A

12340094

UG241_9-9_041106

AF8C2917

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

DEVSEL_N

IRDY_N

TRDY_N

STOP_N

C_PCI_SPACETYPE_0

pcibar_base_hit

wr_data

FFFFFFFF




In Figure 9-9, the initiator writes CBE[3:0] = 0x7 to indicate a memory write transaction, and FRAME_N is asserted for a two doubleword burst transaction. The address written to AD[31:0] is 0xC0000000. In the next clock, IRDY_N is asserted and 0x12345678 data is written to AD[31:0]. The target signals a Disconnect without Data by asserting DEVSEL_N and STOP_N, and leaving TRDY_N de-asserted.

In Figure 9-10, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a single write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is

Figure 9-9: Disconnect without Data on OPB to PCI Write Transaction

Figure 9-10: Target Abort on OPB to PCI Write Transaction


F 0 7 0 F

12340070

C2AC893F

12340074

C3010840

12340078

F832A9CC

1234007C

E8A92CB212340080

9873DA2F

1234008C

4231765812340090

98138352

12340094

2BF8EC3A

12340098

AF8C2917

1234009C

25908D3B

123400A0

D8FA0391

123400A4

FEDC398A

123400A8

2D3F9C91

123400AC

2DC5AC9F

123400B0

7BCE2389

123400B4

3C8FC92A123400B8

4C001830

123400BC

CFAC2983

123400C0

BE229C8A

123400C4

29DF3A87123400C8

123400C

6538412

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

PB_seqaddr

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

F

12340088

12340084

57682341

9AC923F3

UG241_9-10_041106

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

FFFFFFFF 12345678FFFFFFFF

F 0 7 0 F

00004008 C0000000

1234000000000000

1234567800000000

F 0

UG241_9-11_041106




written to AD[31:0]. The target signals a Target Abort by asserting STOP_N but leaving DEVSEL_N and TR DY_N de-asserted.

Master Initiated Abnormal TerminationsA Master Abort is generated by an initiator if it writes an address to a target and the target does not respond. The initiator detects that there is no response from a target if DEVSEL_N remains de-asserted. In a Master Abort, no data is transferred to/from a target. When an initiator experiences a Master Abort, the Received Master Abort bit in the Status Register is set.

Figure 9-12 shows signaling for a Master Abort.

A second type of abnormal termination by an initiator is when the initiator is pre-empted as the PCI Bus master by another bus master. This occurs in two cases: GNT_N is de-asserted and the Latency Timer is not expired, and the Latency Timer is expired but GNT_N is still asserted. In both cases, data is transferred in the burst, but some data remains to be transferred

Figure 9-11: Master Abort

OPB_ABus

OPB_DBus

OPB_BE

OPB_RNW

OPB_xferAck

OPB_select

OPB_seqaddr

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

0


F 0 7 F

12340000 00000000

12345678 00000000

F 0

00004008 C0000000

UG241_9-12_041106


PCI_CLK

FRAME_N

IRDY_N

TRDY_N

DEVSEL_N

0ns 50ns 100ns 150ns 200n

UG241_9-8_041106



Master Initiated Abnormal TerminationsR

In Figure 9-11, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted for one clock cycle to indicate a single write transaction. The 0xC0000000 address is written to AD[31:0]. The initiator asserts IRDY_N and writes 0x12345678 data to AD[31:0]. The targets’ de-asserted state of DEVSEL_N, TRDY_N, and STOP_N indicate to the initiator that no target claims the transaction.



R

Chapter 10

Error Conditions

The previous chapter discussed abnormal terminations of PCI bus transactions. The two types of errors on the PCI bus are parity error and system error. This chapter discusses the generation and reporting of parity and system errors.

When the OPB PCI Bridge is configured as a host bridge, some of the abnormal terminations and the parity and system errors are reported to the processor through the OPB. The two mechanisms for reporting errors and abnormal terminations to the OPB are interrupts and with error registers. This chapter discusses reporting errors and abnormal terminations to the OPB using error registers. Chapter 11 Interrupts discusses reporting errors and abnormal terminations using interrupts.

The OPB PCI Bridge generates and checks parity and reports errors as required by the PCI Local Bus Specification. For more information on error conditions, see Section 3.8 of the PCI Local Bus Specification.

Registers and Generics

The Configuration Header Status register content is provided in Table 9.1 in the previous chapter. The bits in the Status register related to errors are Detected Parity Error and Signaled System Error.

Table 10-1 provides the contents of the Command Register. The Parity Error Response and SERR_N Enable bits are used in error reporting.

The OPB Master Error Definition, Master Read Address, and Master Write Address registers are present if C_INCLUDE_ERR_REG_MODULE=1. The status information provided by the interrupt registers and the error registers is largely duplicated. To reduce logic used, many users include only the errors reported through interrupts. C_INCLUDE_INTR_MODULE determines if the interrupt function is included in the OPB PCI Bridge.



Chapter 10: Error ConditionsR

d System Error are set by the target device. The Received Target Abort and Received are

Table 10-2 is the Status Register. The Signaled Target Abort and SignaleMaster Abort are set by the bus master.

Table 10-1: Command Register

Bit Definition

15:10 Reserved.

9 Fast Back to Back Enable. Not supported. Hardwired to 0.

8 SERR_N Enable.

7 Stepping Control. Not used. Hardwired to 0.

6 Parity Error Response enables the generation of PERR_N.

5 VGA Palette Snoop. Hardwired to 0.

4 Memory Write and Invalidate Enable indicates the bridge is capable of converting posted memory writes to Memory Write and Invalidate transactions. Not supported in the OPB PCI Bridge.

3 Special Cycle. Hardwired to 0.

2 Bus Master allows the bridge to act as a master on the primary side.

1 Memory Space Enable

0 I/O Space Enable

Table 10-2: Status Register

Bit R/W Function

3:0 Reserved

4 R Capabilities List

5 R 1 - Device can run at 66 MHz0 - Device cannot run at 66 MHz

6 Reserved

7 R Fast Back to Back Capable. Hardwired to 0.

8 R/W Master Data Parity Error

10:9 R DEVSEL_N Timing

00 - Fast01 - Medium10 - Slow11 - Reserved

11 R/W Signaled Target Abort

12 R/W Received Target Abort

13 R/W Received Master Abort



Registers and GenericsR

Table 10-3 is the OPB Master Error Register.

Table 10-4 is the Master Read Address Register. The Master Read Address register is loaded with the OPB address of the error which invoked the error. If the Inhibit Master Read bit in the Inhibit Transfer on Errors register is set, the error inhibits subsequent read

Table 10-5 is the Master Write Address Register. The OPB Master Write Address register is loaded with the OPB address of the error which invoked the error. If the Inhibit Master Write bit in the Inhibit Transfer on Errors register is set, the error inhibits subsequent write operations. If the inhibit bit is not set and multiple errors occur, the Master Write Address Register contains the last address with a write error.

14 R/W Signaled System Error

15 R/W Detected Parity Error

Table 10-2: Status Register (Continued)

Bit R/W Function

Table 10-3: Master Error Definition Register

Bit Description

0-20 Unused.

21 OPB Master FIFO Overrun. In a posted OPB Master burst write to a PCI target, the FIFO was overrun.

22 OPB Master Write Retry Timeout in a PCI write to OPB transaction.

23 OPB Master Write Retry Disconnect in a PCI write to OPB transaction.

24 OPB Master Write Retry in a PCI write to OPB transaction.

25 OPB Master Write Master Abort in a PCI write to OPB transaction.

26 OPB Master Write Target Abort in a PCI write to OPB transaction.

27 OPB Master Write PERR in a PCI write to OPB transaction.

28 OPB Master Write SERR in a PCI write to OPB transaction.

29 OPB Master Read Target Abort in a PCI read of OPB transaction.

30 OPB Master Read PERR in a PCI read of OPB transaction.

31 OPB Master Read SERR in a PCI read of OPB transaction.

Table 10-4: OPB Master Read Address Register

Bit(s) Description

0-31 Provides the most recent address of a read error.




Table 10-6 is the Inhibit Transfers on Error register.

The Inhibit Transfers on Error Register is read/write and allows users to inhibit subsequent transfers following an error. The two fields, OPB Master Read Transfers and OPB Master Write Transfers, are inhibited independently.

.

Parity ErrorsParity is generated and checked during the address and data phase of PCI bus transactions. Even parity is calculated on the AD[31:0] and CBE[3:0] signals. The PAR signal is used to signal parity calculated by the driver of the PCI bus. The PAR bit is driven one clock after the address and data phase. The device receiving address or data calculates parity and compares the result to the value on PAR.

The receiver has the option to report parity. Parity is reported if the Parity Error Response bit in the Command register is set. A parity error is reported by setting the Detected Parity

Table 10-5: Master Write Address Register

Bits Description

0-31 Contains the most recent address experiencing a write error.

Table 10-6: Inhibit Transfers on Error Register

Bit(s) Name Description

0-29 Unassigned

30 Inhibit OPB Master Write Transfers

When set to 1, OPB Master Write transfers are inhibited following a write error. OPB retries are issued when inhibited.

31 Inhibit OPB Master Read Transfers

When set to 1, OPB Master Read transfers are inhibited following a read error. OPB retries are issued when inhibited.



Parity ErrorsR

Error bit in the status register and asserting PERR_N. The command and status register state is provided in CSR[39:0].

Figure 10-1 shows parity in a read transaction. The address parity is verified by the target. The initiator drives the address AD[31:0] and CBE[3:0] and outputs parity on PAR. After receiving the address, the target calculates even parity on AD[31:0] and CBE[3:0]. If there is a difference in the calculated parity and the value on PAR, the target reports a system error if the SERR_N Enable bit is set.

The target generates data on AD[31:0]. TRDY_N asserted indicates valid data from the target. One clock cycle later, the target generates PAR for this transaction. The initiator receives the data and PAR, and determines if parity is correct. If parity is incorrect and the Parity Error Response in the Command register is set, PERR_N is asserted.

Figure 10-2 shows parity in a write transaction. The initiator drives the address and data on AD[31:0]. IRDY_N asserted indicates valid data. One clock cycle later, parity is generated on PAR. The target calculates even parity on AD[31:0] and CBE[3:0]. If there is a difference in the calculated parity and the value on PAR, the target reports an error if the Parity Error Response bit is set.

Figure 10-1: Parity in a Read Transaction

Figure 10-2: Parity in a Write Transaction

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

PAR

PERR_N

IRDY_N

TRDY_N

DEVSEL_N

0ns 50ns 100ns 150ns 200ns

UG241_10-01_041006

0ns 50ns 100ns 150ns 200ns

PCI_CLK

FRAME_N

AD[31:0]

CBE[3:0]

PAR

PERR_N

IRDY_N

TRDY_N

DEVSEL_N

UG241_10-02_041006




Parity error recovery can be done by the master, device driver, or operating system. The PCI specification recommends that it is done by the master. In error recovery, the transaction is attempted again, and if successful, the error is not reported. If the parity error re-occurs, the error is reported.

System ErrorsSystem errors occur due to an address phase parity error or a system failure. Both SERR_N and SERR# are used to indicate the active low system error. The SERR# Enable bit in the Command register (see Table 10-1)must be set for SERR_N to be asserted. If a system error is detected with SERR# Enable set, the Signaled System Error in the Status register is set and SERR_N is asserted. Even if SERR_N is not set due to the SERR# Enable bit not being set, the Detected Parity Error is set.

In Figure 10-3, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a burst write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target responds with DEVSEL_N and TRDY_N. SERR_N is active for one clock cycle. The Master Error Definition register is updated with 0x008 in the last

Figure 10-3: SERR_N on Data Phase

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

MST_ADDR_DEF

MST_RD_ADDR

MST_WR_ADDRUG241_10-03_041006

C0000000 12345678 87654321 28359183 AEC32FB8 7291A8FC FFFFFFFF

0 7 0 F

000 008

00000000

00000000 12340000

00004008



System ErrorsR

clock cycle shown. The Master Write Address is loaded with 0x12340000. This is the OPB address translated from the 0xC0000000 PCI address using C_PCIBAR2IPIFBAR_0.

In Figure 10-4, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted for a single write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target responds with DEVSEL_N and TRDY_N. SERR_N is active for one clock cycle.

The Master Error Definition (Mregister is updated with 0x008 in the last clock cycle shown. The Master Write Address is loaded with 0x12340000. This is the OPB address translated from the 0xC0000000 PCI address using C_PCIBAR2IPIFBAR_0.

In Figure 10-5, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a single write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is

Figure 10-4: SERR_N on Address Phase

Figure 10-5: Parity Error on Data Phase

00004008 PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

MST_ERR

MST_RD_ADDR

MST_WR_ADDR

C0000000 12345678 FFFFFFFF FFFFFFFF

0 7 0 F F

000 008

00000000

00000000 12340000

UG241_10-04_041006

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

MST_ERR_DEF

MST_RD_ADDR

MST_WR_ADDR

000 010

00000000

00000000 12340000

C0000000 12345678 FFFFFFF FFFFFFFF

0 7 0 F F

UG241_10-05_041006




written to AD[31:0]. The target responds with DEVSEL_N and TRDY_N. PERR_N is active for one clock cycle.

The Master Error Definition register is updated with 0x010 in the last clock cycle shown. The Master Write Address is loaded with 0x12340000. This is the OPB address translated from the 0xC0000000 PCI address using C_PCIBAR2IPIFBAR_0.

If a parity error is detected on a burst transfer, the PCI transaction is aborted and data transfer stops. If Inhibit on Error is disabled, an OPB timeout is allowed to occur. If Inhibit on Error is enabled, an OPB Retry is asserted after the FIFO is emptied.

In Figure 10-6, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a single write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target signals a Target Abort by asserting STOP_N but leaving DEVSEL_N and TRDY_N de-asserted. A timeout is allowed to occur.

Figure 10-6: Target Abort Error

00004008

UG241_10-06_041006

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

MST_ADDR_DEF

MST_RD_ADDR

MST_WR_ADDR

000 020

00000000

00000000 12340000

C0000000 12345678 FFFFFFFF

0 7 0 F



Reporting ErrorsR


In Figure 10-7, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted for one clock cycle to indicate a single write transaction. The 0xC0000000 address is written to AD[31:0]. The initiator asserts IRDY_N and writes 0x12345678 data to AD[31:0]. The targets’ de-asserted state of DEVSEL_N, TRDY_N, and STOP_N indicates to the initiator that no target claims the transaction.


Reporting ErrorsAbnormal terminations and errors occur in configuration, OPB Master to PCI target, and PCI Initiator to OPB slave transactions, for both read and write transactions. The error reporting mechanism, described below for OPB Master reads of PCI targets, is similar for the different transactions.

When an error occurs, the transaction address is stored is the Master Read Address register. The error is provided in the OPB Master Error Definition register. If enabled, subsequent read operations are inhibited until the bits in the OPB Master Error Definition register are cleared. OPB Retries are asserted when the transaction is inhibited.

If the target signals either a Disconnect with Data or Disconnect without Data on a burst transfer, the PCI transaction is terminated. When the PCI2IPIF FIFO occupancy is below C_TRIG_PCI_READ_OCC_LEVEL, another PCI transaction is attempted if the OPB master request is active. If a Retry is issued on a subsequent PCI transfer, and the OPB master is requesting more data, a retry is issued when the FIFO occupancy is below C_TRIG_PCI_READ_OCC_LEVEL.

If the initiator Latency Timer expires on a burst transfer, the OPB PCI Bridge terminates the PCI transaction. When the PCI2IPIF FIFO occupancy is below the predetermined level, another PCI transaction is attempted if the OPB master request is active.


UG241_10-04_041006

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

MST_ADDR_DEF

MST_RD_ADDR

MST_WR_ADDR

000 040

00000000

00000000 12340000

12345678 FFFFFFFF

0 7 0 FC0000000

00004008




If the address is outside the valid range on a burst transfer, the OPB PCI Bridge terminates the PCI read operation on the last valid address. The FIFO contains only data from valid addresses. Transfers continue until the OPB master terminates the transaction or the FIFO is empty.

Table 10-7 summarizes the handling of abnormal terminations and error conditions.

Table 10-7: Abnormal terminations/Error conditions

Condition Single Transfer Burst

SERR OPB timeout.

OPB Master Read SERR asserted.

OPB timeout.

OPB Master Read SERR asserted

Master Abort OPB timeout. OPB timeout.

PCI Retry OPB Retry. OPB Retry.

Disconnect Without Data

N/A Data is buffered in PCI2IPIF FIFO. The PCI transaction is terminated by the disconnect. At a predefined FIFO occupancy level, the OPB PCI Bridge issues another PCI transaction at the correct address. PCI Retry(s) are automatically retried. PCI_toutSup is asserted while trying to get the requested data.

Disconnect with Data Completes.

Latency Timer expiration

N/A

PERR on data phase Data is transferred. Master Read PERR is asserted

Data transfer is stopped, releasing PCI_toutSup. Master Read PERR is asserted.

Target Abort Immediately release PCI_toutSup. Allow OPB timeout. OPB Master Read Target Abort is asserted

Data transfer is stopped, releasing PCI_toutSup. OPB Master Read Target Abort is asserted.

Address increments beyond valid range

N/A Stop PCI transaction after last valid address. Allow data transfer to continue.



R

Chapter 11

Interrupts

This chapter discusses interrupts in terms of how abnormal terminations and error conditions are provided to the OPB using the interrupt controller in the OPB PCI Bridge.

Interrupts on the PCI Bus are discussed briefly.

Generics and RegistersThe interrupt module is included if C_INCLUDE_INTR_MODULE = 1. The interrupt module can only be included if FIFOs are included in the bridge. If DMA is included, the full interrupt module must be included.

The device Interrupt Pending Register (IPR) and the device interrupt ID register (IID) are included using C_INCLUDE_DEV_PENCODER and C_INCLUDE_DEV_ISC, respectively.

C_INTR_A_BUF is used to insert a buffer on the PCI INTR_A output.

Interrupt Status RegisterThe thirteen interrupts in the OPB PCI Bridge are described in Table 11-1.

Table 11-1: Interrupt Status Register

Bit(s) Description

0-18 Unassigned

19 PCI Initiator Write SERR. A system error occurs during a PCI initiator write to an OPB slave.

20 PCI Initiator Read SERR. A system error occurs during a PCI initiator read from an OPB slave.

21 OPB Master FIFO Overrun. The FIFO is overrun during a posted OPB Master burst write to a PCI target.

22 OPB Master Burst Write Retry Timeout. A retry timeout occurs during an OPB Master burst write to a PCI target. PCI write retries were not successful due to a latency timeout.

23 OPB Master Burst Write Retry Disconnect. During an OPB Master burst write to a PCI target, PCI write retries were not successful due to a target disconnect.

24 OPB Master Write Retry. During an OPB Master burst write to a PCI target, PCI write retries were not successful.


http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_ipif.pdf


Chapter 11: InterruptsR

The bits in Table 11-1 are read/toggle on write. All have reset values of 0.

Device Interrupt Source Controller RegistersThe device Interrupt Source Controller (ISC) registers (ISR, IPR, IER and IID) must be included if DMA is included. These are included by setting C_INCLUDE_DEC_ISC = 1.

Global Interrupt Enable Register A Global Interrupt Enable (GIE) register is used to globally enable or disable interrupts from the PCI device. The GIE is ANDed with the output to the interrupt controller. Bit assignment is shown in Table 11-2. Unlike most registers, this Global Interrupt Enable bit is the MSB on the OPB. GIE is read/write and cleared upon reset.

Interrupt Enable Register Each of the thirteen interrupts are independently enabled. The Interrupt Enable Register bit assignment corresponds to the Interrupt Register bit assignment in Table 11-1. All bits

25 OPB Master Write Master Abort. A Master Abort is asserted due to no response from a target.

26 OPB Master Write Target Abort. A Target Abort is asserted during an OPB Master Write to a PCI target.

27 OPB Master Write PERR. A parity error is detected during an OPB Master write to a PCI target.

28 OPB Master Write SERR. A system error occurs during a OPB Master write to a PCI target.

29 OPB Master Read Target Abort. A Target Abort occurs during a OPB Master read from a PCI target.

30 OBP Master Read PERR. A parity occurs during a OPB Master read from a PCI target.

31 OPB Master Read SERR. A system error occurs during a OPB Master read from a PCI target.

Table 11-1: Interrupt Status Register (Continued)

Bit(s) Description

Table 11-2: Global Interrupt Enable Register

Bit(s) Name Description

0Global Interrupt Enable

Global Interrupt Enable enables all individually enabled interrupts to be passed to the interrupt controller.

• 0 - Not enabled

• 1 - Enabled

1-31 Unassigned



OPB PCI Interrupt ControllerR

are read/write and cleared upon reset. A ‘1’ enables the interrupt. Bit assignment in the Bridge Interrupt Enable Register is shown in Table 11-3.

OPB PCI Interrupt Controller

Figure 11-1 is a block diagram of the interrupt controller in the OPB PCI Bridge. The three sub-modules of the interrupt module are the IP ISC, the Device ISC, and the IPIF Bus interface. The IP ISC block processes most of the interrupts discussed in this chapter. The Device ISC processes internal IPIF interrupts and the single interrupt from the IP ISC. The

Table 11-3: Bridge Interrupt Enable Register

Bit(s) Description

0-18 Unassigned.

19 PCI Initiator Write SERR Enable

20 PCI Initiator Read SERR Enable

21 OPB Master FIFO Overrun

22 OPB Master Burst Write Retry Timeout Enable. Enables the OPB Master Burst Write Retry Timeout interrupt

23 OPB Master Burst Write Retry Disconnect Enable

24 OPB Master Write Retry Enable

25 Master Write Master Abort Enable

26 OPB Master Write Target Abort Enable

27 OPB Master Write PERR Enable

28 OPB Master Write SERR Enable

29 OPB Master Read Target Abort Enable

30 OPB Master Read PERR Enable

31 OPB Master Read SERR Enable

Figure 11-1: Interrupt Block Diagram

IP2Bus_IntrEvent[0:G1-1]

IPIF_Lvl_Interrupts[0:G2-1]

IPIF_Reg_Interrrups[0]

IPIF_Reg_Interrrups[1]

IPISC

DeviceISC

ISR Read Data

IEN Read Data

Write Data

ISR Read Data

IER Read Data

IPR Read Data

IID Read Data

GIE Read Data

Write Data

Intr2Bus_ToutSup

Intr2Bus_Retry

Intr2Bus_Error

Intr2Bus_RdAck

Intr2Bus_WrAck

Bus_RdReq_sa

Bus_WrReq_sa

Bus2IP_Data_sa[0:G5-1]

Intr2Bus_DBus[0:G5-1]

Intr2Bus_DevIntr

Interrupt_RdCE[0:G6-1]

Interrupt_WrCE[0:G6-1]

IPIFBus

Interface

Interrupt

Bus_RdReq_sa

UG241_11-01_041006




IPIF Bus Interface provides Read, Write, and Toggle on Write (TOW) control of the registers in the IP ISC and Device ISC.

The IP ISC has an Interrupt register and Interrupt Enable register, as shown in Table 11-1 and Table 11-3.

The Device ISC is included using C_INCLUDE_DEV_ISC. The interrupts are prioritized using C_INCLUDE_DEV_PENCODER.




Figure 11-2 shows the hierarchy of the IP and Device interrupts. Combined as shown, a single interrupt is generated (IP2INTC_IRPT), gated by the Global Interrupt Enable bit defined in Table 11-2.

Figure 11-2: Interrupt Hierarchy

Figure 11-3: SERR_N Interrupt on Data Phase

IPIF ISC N IPIF ISC 2 IPIF ISC 1

Reserved(IPIF growth)

IP2Bus_Error_sa

IPISC

IPIF InterruptSource N

IPIF InterruptSource 2

IPIF InterruptSource 1

IPIP Interrupts

Device ISC

1

1 1 1

1

1

1

InterruptIPIFDevice

Single Interrupt to theSystem Interrupt Controller UG241_11-02_041006

C_IP_INTR_MODE

C_INCLUDE_DEV_PENCODER

C_INCLUDE_DEV_ISC

IP_IRPT_STATUS_REG

IP_IRPT_ENABLE_REG

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

IPIF_MST_WR_SERR_INTRPT

IP2INTC_IRPT

{5 5 5 5 5 5 5 5 5 5 5 5 5}

0000 0008

0008

FFFFFFFF

F 0 7 0 F

FFFFFFFF C0000000 87654321 7291A8FC

00004008 12345678 28359183

UG241_11-03_041006




In Figure 11-3, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a burst write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target asserts DEVSEL_N and TRDY_N. SERR_N is active for one clock cycle. The SERR_N interrupt on IPIF_MST_WR_SERR_INTRPT occurs two clock cycles later, and IP2INTC_IRPT is one clock after.

In Figure 11-4, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a single write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target asserts DEVSEL_N and TRDY_N. SERR_N is active for one clock cycle. The SERR_N interrupt on IPIF_MST_WR_SERR_INTRPT occurs two clock cycles later.

In Figure 11-5, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a single write transaction. The

Figure 11-4: SERR_N Interrupt on Address Phase

Figure 11-5: PERR_N on Data Phase

C_IP_INTR_MODE

C_INCLUDE_DEV_PENCODER

C_INCLUDE_DEV_ISC

IP_IRPT_STATUS_REG

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

IPIF_MST_WR_SERR_INTRPT

{5 5 5 5 5 5 5 5 5 5 5 5 5}

0000 0008


0 7 0 F F

00004008

UG241_11-04_041006

UG241_11-05_041006

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

IPIF_MST_WR_PERR_INTRPT


0 7 0 F F

02000546




0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target asserts DEVSEL_N and TRDY_N. PERR_N is active for one clock cycle. The PERR_N interrupt on write IPIF_MST_WR_PERR_INTRPT occurs two clock cycles later.

In Figure 11-6, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted and de-asserted to designate a single write transaction. The 0xC0000000 address is written to AD[31:0]. IRDY_N is asserted, and 0x12345678 data is written to AD[31:0]. The target signals a Target Abort by asserting STOP_N but leaving DEVSEL_N and TRDY_N de-asserted. The Target Abort interrupt IPIF_MST_WR_TARGET_ABORT_INTRPT is generated for one clock cycle.

In Figure 11-7, the initiator writes CBE[3:0] = 0x7 to indicate a memory write, and FRAME_N is asserted for one clock cycle to indicate a single write transaction. The 0xC0000000 address is written to AD[31:0]. The initiator asserts IRDY_N and writes 0x12345678 data to AD[31:0]. The targets’ de-asserted state of DEVSEL_N, TRDY_N, and STOP_N indicates to the initiator that no target claims the transaction. The IPIF_MST_ABORT_WR_INTRPT is generated for one clock cycle.

Figure 11-6: Target Abort Interrupt

Figure 11-7: Master Abort Interrupt

IP_IRPT_STATUS_REG

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

WR_TARGET_ABORT_INTRPT

0000 0020

00004008 C0000000 12345678 FFFFFFFF FFFFFFFF

0 7 0 F F

UG241_11-06_041006

PCLK

AD

CBE

FRAME_N

IRDY_N

DEVSEL_N

TRDY_N

STOP_N

PERR_N

SERR_N

IPIF_MST_ABORT_WR_INTRPT

00004008 C0000000 12345678 FFFFFFFF

F 0 7 0 F

FFFFFFFF

UG241_11-07_041006




PCI Bus InterruptsBus2PCI_INTR is an active High signal. It allows asynchronous assertion of INTR_A on the PCI bus. The signal is driven by user supplied circuitry, e.g, an OPB GPIO. The signal is inverted in the OPB PCI Bridge and ANDed with the bridge interrupt signal (active Low) to drive the INTR_N input of the v3.0 core. This signal then asynchronously drives INTR_A on the PCI bus. See the v3.0 core specifications on INTR_A behavior relative to v3.0 input INTR_N. The v3.0 core command register interrupt disable bit controls the INTR_A operation.



R

Chapter 12

Design Constraints

This chapter describes how the OPB PCI Bridge uses location and timing constraints. The required PCI performance is guaranteed when the constraints file is used.

The following subjects are discussed:

• The function of the constraints in the user constraints file (*.ucf)

• The use of the Pin Assignment and Constraints Editor

Important: Do not modify or remove the constraints in the user constraints file. Customi-zation of this file is allowed, but the modifications must not change the functionality of the supplied constraints. Xilinx guarantees PCI-compliant timing only if the constraints file and guide file are used during processing.

While there are separate constraints files for every part and package combination, the constraints in each perform the same function. These functions are:

• Pinout definition and placement constraints

• Timing constraints

Pinout and Placement ConstraintsThe pinout of the PCI interface is constrained in the user constraints file to match the suggested pin ordering in the PCI Local Bus Specification as closely as possible. In addition, the user constraints file prohibits device pins which are reserved for configuration and boundary scan.

Absolute placement constraints are specified in the user constraints file. These group critical logic sections together. Additionally, the placement constraints align internal datapath registers and three-state buffers in columns which straddle the internal ADIO bus. The ADIO bus is formed by horizontal long lines in the FPGA.

Each device and package combination has unique timing constraints to ensure full PCI compliance. Do not remove any constraints.

UCF GeneratorThe UCF Generator enables users to create device and package specific User Constraint Files for all supported packages. Xilinx has tested these packages. A UCF with a custom pinout can be created with the UCF Generator.

To use the UCF Generator, select the core version, bus interface, device family, and bus width. Determine the side of the device to locate the PCI interface. Typically, the slot side is used. The device side is not the same as the side of the die. The side of the die corresponds to the side of the device for a cavity UP package. This is reversed for cavity DOWN



Chapter 12: Design ConstraintsR

packages. Select the frequency, target device, package, and speed grade. If a specific pinout is needed, select Customize.

Constraints Generated in EDKSome constraints are implemented automatically in the EDK tool flow The constraints are located in the implementation/<opb_pci_bridge> directory, and are used in the implementation process. This ucf-file is readable for verification of the constraints.

Alternatively, constraints can be provided in the top-level ucf-file. When the constraints are included in both the top-level ucf-file and the OPB PCI Bridge UCF, the top-level ucf-file has precedence.

IDelay Primitives in Virtex-4 FPGAsTo meet PCI specification setup and hold times with the Virtex-4 architecture, an IDELAY primitive is inserted between the pad and I/O buffer of most PCI signals. Additionally, IDELAYCTRL (idelay controllers) are required. A 200 MHz reference clock RCLK is required by the IDELAY and IDELAYCTRL primitives. RCLK must be driven by a global buffer. RCLK must be stable when OPB_RST is asserted. The clock source can be an external source or generated with a DCM in the FPGA.

IDELAY primitives are instantiated automatically when C_FAMILY = virtex4. The user must instantiate the IDELAYCTRL primitives and provide LOC constraints for each IDELAYCTRL. See the Virtex-4 User Guide for IDELAYCTRL usage. The PCI protocol requires at least two IDELAYCTRL primitives in the Virtex-4 architecture. The actual number depends on the pinout. The v3.0 core uses two IDELAYCTRL primitives. For the OPB PCI Bridge, C_NUM_IDELAYCTRL is used to specify the number of IDELAYCTRL primitives from two to six. Since timing is affected when the pinout uses three to six IDELAYCTRL primitives, the recommendation is to use two IDELAYCTRL primitives.

When more than one IDELAYCTRL is instantiated, locator (LOC) constraints are required on each IDELAYCTRL instantiation. A MAP failure occurs if the LOC constraints are not provided. The Pin and Constraints Editor (PACE) tool can help determine valid IDELAYCTRL LOC coordinates for the user's pinout.

The syntax for the UCF-file LOC constraints is given below. The instance name for each IDELAYCTRL is XPCI_IDC0 to XPCI_IDCN, with N the C_NUM_IDELAYCTRL-1. A LOC entry is required for each IDELAYCTRL used. In most cases, the LOC constraints from the v3.0 ucf-generator can be used.

INST *XPCI_IDC0 LOC=IDELAYCTRL_X2Y5;

INST *XPCI_IDC1 LOC=IDELAYCTRL_X2Y6;

An optional method for setting of LOC constraints is to use C_IDELAYCTRL_LOC in the MHS file. This parameter is generated in the OPB PCI core ucf-file. If the LOC constraints are set in the system top-level ucf-file, C_IDELAYCTRL_LOC is not used, since the system top-level UCF-file overrides all core-level UCF constraints.

The syntax for C_IDELAYCTRL_LOC is IDELAYCTRL_XNYM, in which N and M are coordinates and multiple entries are concatenated by - (i.e., dash). The order of entries correspond to IDELAYCNTRL instance names XPCI_IDC0, XPCI_IDC1, ... up to the



Pin and Constraints Editor (PACE)R

maximum index of IDELAY controller instances in the FPGA. The maximum index is C_NUM_IDELAYCTRL-1. The MHS file syntax is given below. The quotes are optional.

PARAMETER C_IDELAYCTRL_LOC="IDELAYCTRL_X2Y5-IDELAYCTRL_X2Y6"

Other constraints that are required include the IOBDELAY_TYPE, IOBDELAY_VALUE and IOB. These parameters are set in the normal EDK tool flow, but can be included in the system top-level ucf-file. For alternative tool flows, the constraints are given below.

INST "*XPCI_CBD*" IOBDELAY_TYPE=VARIABLE ;

INST "*XPCI_ADD*" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_PARD" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_FRAMED" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_TRDYD" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_IRDYD" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_STOPD" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_DEVSELD" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_PERRD" IOBDELAY_TYPE=VARIABLE ;

INST "*PCI_CORE/XPCI_SERRD" IOBDELAY_TYPE=VARIABLE ;

#Include next 2 if routed to pins

INST "*XPCI_IDSEL" IOBDELAY_TYPE=VARIABLE ;

INST "*XPCI_GNTD" IOBDELAY_TYPE=VARIABLE ;

INST "*XPCI_CBD*" IOBDELAY_VALUE=55 ;

INST "*XPCI_ADD*" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_PARD" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_FRAMED" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_TRDYD" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_IRDYD" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_STOPD" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_DEVSELD" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_PERRD" IOBDELAY_VALUE=55 ;

INST "*PCI_CORE/XPCI_SERRD" IOBDELAY_VALUE=55 ;

#Include next 2 if routed to pins

INST "*XPCI_IDSEL" IOBDELAY_VALUE=55 ;

INST "*XPCI_GNTD" IOBDELAY_VALUE=55 ;

Pin and Constraints Editor (PACE)MAP errors occur if the IDELAYCTRL has an incorrect location, or if IOSTANDARD constraints in the UCF violate banking rules, etc. It is usually time efficient to verify the location constraints in the UCF using PACE rather than verifying the constraints by implementing a design through MAP.




Figure 12-1 shows how to start PACE using the UCF, NGD file, and the part type.

Figure 12-2 shows using PACE to run the Design Rule Check (DRC). If DRC fails, icons for I/O banks - IOSTANDARDs, and IDELAYCTRLs are provided to quickly correct the design rule violations.

Timing ConstraintsTiming constraints are specified in three distinct steps. First, timename (TNM) attributes are attached to specific instances in the design. Next, timegroups (TIMEGRP) are created from timenames. Finally, timespecs (TIMESPEC) are formed by timing specifications between various timenames and timegroups.

Figure 12-1: PACE startup

Figure 12-2: PACE Design Rule Checks

UG241_12-01_041006

UG241_12-02_041006




The timing constraints are automatically generated. An example set of timing constraints is shown below.

##############################################################################

# I/O Time Names

###############################################################################NET “PCI_SERR_N” TNM = PADS:PCI_PADS_C ;NET “PCI_PERR_N” TNM = PADS:PCI_PADS_C ;NET “PCI_FRAME_N” TNM = PADS:PCI_PADS_C ;NET “PCI_IRDY_N” TNM = PADS:PCI_PADS_C ;NET “PCI_TRDY_N” TNM = PADS:PCI_PADS_C ;NET “PCI_DEVSEL_N” TNM = PADS:PCI_PADS_C ;NET “PCI_STOP_N” TNM = PADS:PCI_PADS_C ;NET “PCI_CBE(3)” TNM = PADS:PCI_PADS_B ;NET “PCI_CBE(2)” TNM = PADS:PCI_PADS_B ;NET “PCI_CBE(1)” TNM = PADS:PCI_PADS_B ;NET “PCI_CBE(0)” TNM = PADS:PCI_PADS_B ;NET “PCI_PAR” TNM = PADS:PCI_PADS_P ;NET “PCI_AD(31)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(30)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(29)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(28)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(27)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(26)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(25)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(24)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(23)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(22)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(21)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(20)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(19)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(18)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(17)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(16)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(15)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(14)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(13)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(12)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(11)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(10)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(9)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(8)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(7)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(6)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(5)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(4)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(3)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(2)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(1)” TNM = PADS:PCI_PADS_D ;NET “PCI_AD(0)” TNM = PADS:PCI_PADS_D ;#################################################################################




# Special I/O Time Names#################################################################################INST “*PCI_CORE/PCI_LC/PCI-CBE/IO3/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-CBE/IO2/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-CBE/IO1/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-CBE/IO0/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO31/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO30/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO29/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO28/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO27/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO26/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO25/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO24/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO23/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO22/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO21/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO20/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO19/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO18/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO17/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO16/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO15/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO14/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO13/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO12/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO11/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO10/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO9/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO8/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO7/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO6/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO5/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO4/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO3/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO2/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO1/OFD” TNM = FFS:PCI_FFS_OCE ;INST “*PCI_CORE/PCI_LC/PCI-AD/IO0/OFD” TNM = FFS:PCI_FFS_OCE ;#INST “*PCI_CORE/XPCI_CBQ3” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_CBQ2” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_CBQ1” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_CBQ0” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ31” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ30” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ29” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ28” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ27” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ26” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ25” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ24” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ23” TNM = FFS:PCI_FFS_ICE ;




INST “*PCI_CORE/XPCI_ADQ22” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ21” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ20” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ19” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ18” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ17” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ16” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ15” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ14” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ13” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ12” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ11” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ10” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ9” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ8” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ7” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ6” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ5” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ4” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ3” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ2” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ1” TNM = FFS:PCI_FFS_ICE ;INST “*PCI_CORE/XPCI_ADQ0” TNM = FFS:PCI_FFS_ICE ;

################################################################################# Time Groups###############################################################################

INST “*PCI_LC” TNM = FFS:PCIM_FFS ;TIMEGRP “ALL_FFS” = “PCIM_FFS” : “USER_FFS” ;TIMEGRP “FAST_FFS” = “PCI_FFS_ICE” : “PCI_FFS_OCE” ;TIMEGRP “SLOW_FFS” = “ALL_FFS” : EXCEPT : “FAST_FFS” ;

# 1) Clock to Output = 11.000 ns# 2) Setup = 7.000 ns# 3) Grant Setup = 10.000 ns# 4) Datapath Tristate = 28.000 ns# 5) Period = 30.000 ns

# The following timespecs are for setup.

TIMEGRP “PCI_PADS_D” OFFSET = IN 7.000 VALID 7.000 BEFORE “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;TIMEGRP “PCI_PADS_B” OFFSET = IN 7.000 VALID 7.000 BEFORE “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;TIMEGRP “PCI_PADS_P” OFFSET = IN 7.000 VALID 7.000 BEFORE “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;TIMEGRP “PCI_PADS_C” OFFSET = IN 7.000 VALID 7.000 BEFORE “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;//TIMEGRP “PCI_PADS_G” OFFSET = IN 10.000 VALID 10.000 BEFORE “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;# The following timespecs are for clock to out where stepping is not used.




TIMEGRP “PCI_PADS_D” OFFSET = OUT 11.000 AFTER “PCI_CLK5_FB” TIMEGRP “FAST_FFS” ;TIMEGRP “PCI_PADS_B” OFFSET = OUT 11.000 AFTER “PCI_CLK5_FB” TIMEGRP “FAST_FFS” ;TIMEGRP “PCI_PADS_P” OFFSET = OUT 11.000 AFTER “PCI_CLK5_FB” TIMEGRP “FAST_FFS” ;TIMEGRP “PCI_PADS_C” OFFSET = OUT 11.000 AFTER “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;//TIMEGRP “PCI_PADS_G” OFFSET = OUT 11.000 AFTER “PCI_CLK5_FB” TIMEGRP “ALL_FFS” ;# The following timespecs are for clock to out where stepping is used.TIMEGRP “PCI_PADS_D” OFFSET = OUT 28.000 AFTER “PCI_CLK5_FB” TIMEGRP “SLOW_FFS” ;TIMEGRP “PCI_PADS_B” OFFSET = OUT 28.000 AFTER “PCI_CLK5_FB” TIMEGRP “SLOW_FFS” ;TIMEGRP “PCI_PADS_P” OFFSET = OUT 28.000 AFTER “PCI_CLK5_FB” TIMEGRP “SLOW_FFS” ;



R

Chapter 13

Bus Functional Model Simulation

In this chapter, BFM simulations are provided for standard bus transactions between the OPB and PCI buses. The transactions are configuration, OPB to PCI read and write, PCI to OPB read and write, DMA, and reset operations. Simulation files are provided so that users can run BFM simulations without writing stimuli. Figures of the waveforms of bus transactions are provided so the user knows the expected behavior prior to running a simulation. The user can run the simulation to get better views of the waveforms and to add signals to get a more detailed understanding of the functionality.

The design files also include Waveform Log (wlf) and Value Change Dump (vcd) files for learning the functionality of the bus transactions without simulating. The wlf/vcd files are generated from the eight bus transactions simulated in this chapter.

In addition to the eight BFM testbenches for common bus transactions, a comprehensive testbench is provided for users needing to do a very detailed simulation. The eight basic testbenches and the comprehensive testbench use the same bus monitors and initiator and target Finite State Machines (FSMs). The comprehensive testbench provides more exhaustive testing and detailed simulation of error conditions. The general functionality of the testbench is described in the Comprehensive OPB PCI Testbench section.

To run the simulation, the user must compile the simulation library. This is typically done in EDK. The second part of this chapter provides the setup steps to develop BFM stimuli. This is intended to be used by users who need to generate different or more detailed stimuli.

Support files for simulation are in:


Simulating Bus TransactionsThe bus transactions simulated in the first section are given in Table 13-1.

Table 13-1: Procedures for General Bus Transactions

Bus Transaction VHDL Procedure Transaction Suffix

OPB Configuration Write configure_from_opb_bus cfg_opb

PCI Configuration Write configure_from_pci_bus cfg_pci

PCI to OPB Write p2o_write p2o_wr

PCI to OPB Read p2o_read p2o_rd

OPB to PCI Write o2p_write o2p_wr

OPB to PCI Read o2p_read o2p_rd



Chapter 13: Bus Functional Model SimulationR

In this section, each transaction is discussed briefly in terms of the waveform output. A more detailed description of the transaction is provided in the chapter defining the transaction (Chapters 5, 6, 7). In most cases, a figure of the complete transaction is given, followed by figures zoomed into sections of the OPB and PCI signals.

Analyzing Bus Transactions in the Waveform ViewerThe <transaction_suffix>.wlf|vcd files allow each of the eight bus transactions to be viewed in the Modeltech waveform viewer or SimVision. Signals are added and removed to/from the waveform viewer, and the user can zoom into/out of specific areas of the bus transaction. To analyze a transaction using a wlf file, follow the steps below.

1. Invoke ModelSim

2. File -> Open Data Set bfmsim/simulation/behavioral/dma_write.wlf

3. View ->Signals

4. Select my_core in ModelSim window

5. Highlight signals in Signals window

6. Add -> Wave -> Selected Signals

Figure 13-1 shows the setup to analyze bus transactions using the wlf files.

OPB to PCI DMA Write dma_write dma_wr

Reset Operation Reset_IPIF, Reset_PCI reset

Table 13-1: Procedures for General Bus Transactions (Continued)

Bus Transaction VHDL Procedure Transaction Suffix

Figure 13-1: Analyzing Transactions Using wlf files

UG241_13-1_041306



Running BFM SimulationR

Figure 13-2 shows the waveform viewer used to analyze wlf files.

Running BFM SimulationTo run a BFM simulation compile the EDK and ISE simulation libraries in EDK.

1. Download the design files in

www.xilinx.com/bvdocs/desfiles/xug241.zip

2. Unzip the design files from xug241.zip.

3. Change to the bfmsim/pcores/opb_pci_tb_v1_00_a/hdl/vhdl directory. Copy opb_pci_tb.vhd.<transaction_suffix> to opb_pci_tb.vhd.

Change to the bfmsim/scripts directory. Copy opb_pci.do.<transaction_prefix> to opb_pci.do.

Configuration from the On-chip Peripheral BusThe code in opb_pci_tb.vhd which invokes the configure_bridge_from_opb is in the Test_Process process on line 1380:

configure_bridge_from_opb_bus;

The procedure is defined in Test_Process. Since the configuration is from the OPB side, most of the stimuli is generated from bfmsim/scripts/m4/opb_pci.m4.cfg_opb. The opb_pci_tb.vhd.cfg_opb generates messages to the transcript window.

Figure 13-2: Waveform Viewer

UG241_13-2_041306




Figure 13-3 shows the configuration of the v3.0 core from the OPB. This is done by a series of writes to the Configuration Address Port and Configuration Data Port. The figure shows transitions on the OPB and PCI bus (AD, FRAME_N, etc). The Command Status Register, Latency Timer, and the PCI Base Address Registers are configured. The activity on the v3.0 signals (IDSEL_INT, CFG_HIT, CFG_SELF) indicate that the generation of IDSEL is correct.

Figure 13-3: Configuration from the OPB

04000080

00000000

0C000080

00000000

10000080

00000000

0000000030000114 3000010C 3000010C 3000010C

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

IDSEL_in

CFG_SELF

CFG_VLD

CFG_HIT

C_TERM

C_READY

IDSEL_INT

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

00000000 00000000 00000000

00000000 30000110 00000000 30000110

FFFFFFFF FFFFFFFF FFFFFFFFFFFFFFFF

FFFFFFFF

F 0 F 0 F 0 F 0 F

UG241_13-4_041306



Configuration from the On-chip Peripheral BusR

When configuring from the OPB, the microprocessor writes an address in the configuration header to the Configuration Address Port (CAP). The content of the register(s) in the configuration header is loaded by a write to the Configuration Data Port (CDP). Configuration of the v3.0 configuration header then consists of writes to the CAP/CDP pairs to configure the Command Status Register, Latency Timer, and the BARs.

Figure 13-4 shows the details of the writing of the Configuration Address Port. The OPB_ABus is C_BASEADDR + 10C, or 0x3000010C. The OPB_DBus is 0x04000080. The 04 is the offset of the Command Status Register within the Configuration Header. Writing to the CAP does not cause signal activity on the v3.0 configuration ports or the PCI bus.

Figure 13-4: Configuration Write of the Configuration Address Port

F

30000114

3000010C

F

UG241_13-5_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

IDSEL_in

CFG_SELF

CFG_VLD

CFG_HIT

C_TERM

C_READY

IDSEL_INT

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

00000000 04000080 00000000

00000000 3000010C 00000000

FFFFFFFF




Figure 13-5 shows a write to the Configuration Data Port. CBE[3:0] = B, specifying a configuration write.The address on OPB_ABus is C_BASEADDR + 0x110, or 0x30000110. The data on OPB_DBus is 0x46050002 is byte swapped to 0x02000546 on the AD bus.

Writing to the Configuration Data Port causes signal activity on the PCI bus (FRAME_N, AD, etc.) and the v3.0 configuration ports (CFG_SELF, CFG_VALID, IDSEL_int).

Figure 13-5: Writing the Configuration Data Port for the CSR

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus00000000

OPB_ABus

ADFFFFFFFF 00010004

FFFFFFFF

IDSEL_in

CFG_SELF

CFG_VLD

CFG_HIT

C_TERM

C_READY

IDSEL_INT

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_NUG241_13-6_041306

46050002 00000000

30000110 00000000

FFFFFFFF 02000546

F F B 0 F



Configuration from PCI busR

Figure 13-6 shows the write (CBE[3:0] = 0xB) and read (CBE[3:0] = 0xA) of the Latency Timer. The value on OPB_ABus is the value o the Configuration Data Port, 0x30000110. The 0x0000FF00 on OPB_DBus (and AD) indicates that FF is loaded into the Latency Timer.

Configuration from PCI busThe source in opb_pci_tb.vhd which invokes the configure_bridge_from_pci procedure is in the Test_Process process on line 1380:

configure_bridge_from_pci_bus;

The procedure is defined in Test_Process. Most of the stimuli is generated from opb_pci_tb.vhd.

Figure 13-6: Configuring the Latency Timer

0C000080

3000010C

02000546 0001000C

FFFFFFFF

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

IDSEL_in

CFG_SELF

CFG_VLD

CFG_HIT

C_TERM

C_READY

IDSEL_INT

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

00000000 00FF0000 00000000

3000010C 00000000 30000110 00000000

FFFFFFFF

00000000

0000FF00

F 0 B 0 F

UG241_13-7_041306




Figure 13-7 shows the complete configuration of the configuration header from the PCI side. The Command Status Register, Latency Timer, and three PCI BARs are written. The configuration transactions are initiated by a host driving the PCI AD bus. There is activity on IDSEL_INT, CFG_VLD, CFG_HIT, so configuration transactions are occurring at the v3.0 interface. There is no activity on OPB_ABus or OPB_DBus.

In Figure 13-8, the Command Status Register is written. The base address of the configuration header is 0x00010000. The CSR is offset 0x4, so AD = 0x00010004. Data written to the CSR is 0x2000546. A configuration write (0xB) is generated on CBE[3:0]

Figure 13-7: Configuration from PCI side

Figure 13-8: Configuring the Command Status Register from PCI side

ADFFFFFFFF

FFFFFFFF

CBE

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N

IDSEL_in

CFG_SELF

CFG_VLD

CFG_HIT

C_TERM

C_READY

IDSEL_INT

V3_CLK

FFFFFFFF

FFFFFFFF

FFFFFFFF

UG241_13-8_041306

FFFFFFFF

0 0 0 0 0 0 0 0 0 0F F F F F F F F F F F

UG241_13-9_041306

FFFFFFFF 00010004 02000546 FFFFFFFF

F B 0 F

AD

CBE

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N

IDSEL_in

CFG_SELF

CFG_VLD

CFG_HIT

C_TERM

C_READY

IDSEL_INT

V3_CLK



PCI to OPB Write TransactionR

Figure 13-9 shows configuring the latency timer from the PCI side. The 0x00010000C is written in the address phase to specify the 0xC offset of the latency timer from the beginning of the configuration header.

PCI to OPB Write TransactionThe BFM stimuli for the PCI to OPB Write transactions are given in opb_pci_tb.vhd.p2o_wr and opb_pci.m4.p2o_wr. The procedure to perform the transaction is defined in Test_Process in opb_pci_tb.vhd.p2o_wr and invoked in Test_Process by the following procedures.

pci_opb_single_writepci_opb_burst_write

Figure 13-9: Configuring Latency Timer from PCI side

AD

CBE

FRAME_N

IRDY_N

TRDY_N

STOP_N

DEVSEL_N

IDSEL_i

CFG_SELF

CFG_VLD

CFG_HI

C_TERM

C_READY

IDSEL_INT

V3_CLK

FFFFFFFF 0001000C 0000FF00 FFFFFFFF

F B 0 F

UG241_13-10_041306




Figure 13-10 shows the complete waveform for the PCI to OPB single write transaction. Figure 13-11 and Figure 13-12 zoom into the PCI and OPB signals respectively.

In Figure 13-11, the initiator asserts FRAME_N and sets CBE[3:0] = 0x7 to indicate a memory write. The address on AD = 0x00001000. In the data phase 0x78563412 is output AD. The transaction on the PCI bus occurs when DEVSEL_N, TRDY_N, and IRDY_N are asserted.

Figure 13-10: PCI to OPB Single Write

Figure 13-11: PCI to OPB Single Write - PCI Signals

PB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

PB_xferAck

OPB_DBus12345678

00000000

OPB_ABus00010000

ADFFFFFFFF

00001000

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

78563412 FFFFFFFF

F 7 0 F

UG241_13-11_0413

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF 00001000 78563412 FFFFFFFF

F 7 0 F

UG241_13-12_041306




Figure 13-12 shows the OPB signals for the PCI to OPB single write. OPB_RNW is low when OPB_Select is active to specify a write. The 0x00001000 on AD is translated to 0x00010000 on OPB_DBus using C_PCIBAR2IPIFBAR = 0x00010000. The data output OPB_DBus = 0x12345678 is the byte swapped data of the original 0x78563412 on AD.

Figure 13-13 shows the complete waveform of a PCI to OPB Burst write. The bus transaction begins on the PCI bus with a memory write (CBE = 0x7) when FRAME_N is asserted. The first word transmitted is 0xDF8CCA98. FRAME_N is held asserted during the burst on AD. The OPB transactions are shown on the right side of the waveform.

Figure 13-12: PCI to OPB Single Write - OPB Signals

Figure 13-13: PCI to OPB Burst Write

00000000 12345678 00000000

00000000 00010000 00000000

FFFFFFFF

F

UG241_13-13_041306

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF DF8CCA98 FFFFFFFF

F 7 0 F

00000000

920C6975

UG241_13-14_041306




OPB_Select and OPB_seqAddr are maintained high for the burst, with OPB_seqAddr ending one clock cycle before the end of the burst. The OPB_ABus and OPB_DBus transition on each clock cycle for the burst.

Figure 13-14 shows the PCI bus activity in the PCI to OPB memory burst. The burst length is defined by the duration FRAME_N is kept asserted. This is a burst of 8. During this interval, there is no activity on the OPB.

Figure 13-14: PCI to OPB Burst - PCI signals

Figure 13-15: PCI to OPB Burst - OPB Signals

k

00000000

00000000

FFFFFFFF DF8CCA98 920C6975

F 7 0 F

00001000 9D9C26E8

9B3D9210

8BAC39A8

10873239

FDECEDAB

D9508719

FFFFFFFF

OPB_seqAddr

OPB_Cl

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLKUG241_13-15_041306

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000 98CA8CDF

00000000

FFFFFFFF

E8269C9D 10923D9B A839AC8B 39328710 DABEDECF 198750D9 75690C92 00000000

00010000 00010004 00010008 0001000C 00010010 00010014 00010018 0001001C 00000000

UG241_13-16_041306

F




Figure 13-15 shows the OPB signals active during the PCI to OPB memory write. The OPB_Select defines when the eight dwords are provided to the OPB_DBus. The address on OPB_ABus is incremented 0x04 each clock cycle.

Figure 13-16 shows the complete waveform for a PCI to OPB Memory Write Invalidate (MWI) command.

Figure 13-16: PCI to OPB Memory Write Invalidate

Figure 13-17: PCI to OPB Memory Write Invalidate - PCI Signals

00001000

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

AD

00000000

00000000

8CAF2381 FFFFFFFF

F F 0 F

FFFFFFFF

8123AF8C

00000000

00010000

UG241_13-17_041306

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF 00001000 8CAF2381 FFFFFFFF

F F 0 F

UG241_13-18_041306




Figure 13-17 shows PCI bus signals in the MWI command. When FRAME_N is asserted, the initiator writes 0xF to CBE[3:0]. The address written is 0x00001000. The data on AD during the data phase is 0x8CAF2381.

Figure 13-18 shows OPB signals during a PCI to OPB Memory Write Invalidate. When OPB_select is active, data on OPB_DBus is 0x8123AF86.

PCI to OPB Read OperationThe BFM stimuli for the PCI to OPB Read transactions are given in opb_pci_tb.vhd.p2o_rd and opb_pci.m4.p2o_rd. The procedure to perform the transaction is defined in Test_Process in opb_pci_tb.vhd.p2o_rd and invoked in Test_Process by the following procedures.

pci_opb_single_readpci_opb_burst_read

Figure 13-18: PCI to OPB Memory Write Invalidate - OPB Signals

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000 8123AF8C 00000000

00000000 00010000 00000000

FFFFFFFF

F

UG241_13-19_041306



PCI to OPB Read OperationR

Figure 13-19 shows the complete PCI to OPB single memory read, starting with the address on the PCI bus, followed by the read data on the OPB, followed by the read data on the PCI bus.

Figure 13-20 shows the initiator generating the memory read transaction. When FRAME_N is asserted, a memory read (0x6) is written to CBE[3:0]. The 0x00001000 address is written to AD. There is no activity on the OPB at this time.

Figure 13-19: PCI to OPB Single Read

Figure 13-20: PCI to OPB Single Read - PCI Provides Read Address

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus7820CADF

OPB_ABus00010000

00001000

FFFFFFFF 00004008 DFCA2078

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLKUG241_13-20_041306

AD

00000000 00000000

00000000 00000000

FFFFFFFF FFFFFFFF FFFFFFFF

F 6 0 F

FFFFFFFF

UG241_13-21_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF 00001000 FFFFFFFF 00004008

F 6 0




Figure 13-21 shows the translated address 0x00010000 on OPB_ABus. The read is indicated with OPB_RNW = 1 when OPB_Select = 1. The OPB_DBus = 0x 7820CADF when OPB_xferAck is asserted.

Figure 13-22 shows the OPB data transferred on PCI AD, with byte swapping resulting in AD = 0xDFCA2078 when TRDY_N is asserted.

Figure 13-21: PCI to OPB Single Read - OPB Signals

Figure 13-22: PCI to OPB Single Read - PCI 2

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000 7820CADF 00000000

00000000 00010000 00000000

FFFFFFFF

0

UG241_13-22_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF DFCA2078 FFFFFFFF

0 F

UG241_13-23_041306



PCI to OPB Read OperationR

Figure 13-23 shows the complete PCI to OPB burst read, starting with PCI transactions, followed by OPB burst, followed by a PCI burst transaction.

Figure 13-24 shows the PCI initiator writing an address = 0x00001000 to AD and the memory read multiple (0xC) command on CBE when FRAME_N is asserted

Figure 13-23: PCI to OPB Burst Read

Figure 13-24: PCI to OPB Burst Read - PCI 1

FFFFFFFFFFFFFFFF

00001000 00000000

DFCA2078

329B3C98

AB58C3C0

DFDC2308

9D380278

6D8592AC

FEAD2398

CB82C0EA

UG241_13-24_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000 00000000

00000000 00000000

FFFFFFFF

F C 0 F

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF 00001000 FFFFFFFF 00000000 FFFFFFFF

F C 0

UG241_13-25_041306




Figure 13-25 shows the burst data from the OPB. OPB_Select is high for 8 words. OPB_seqAddr is asserted for the burst. OPB_ABus starts with 0x0001000 and is incremented by 0x4 each clock cycle. The first dword on OPB_DBus is 0x7820CADF. The second dword is 0x983C9B32. There is no PCI bus activity during this interval.

Figure 13-26 shows data read on AD occurring when DEVSEL_N, IRDY_N, and TRDY_N are asserted. As with the single read, AD data is byte swapped from the OPB_DBus.

Figure 13-25: PCI to OPB Burst Read - OPB

Figure 13-26: PCI to OPB Burst Read - PCI 2

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000 00000000

00000000 00010000 00010004 00010010 00010018 00000000

FFFFFFFF

0

7820CADF 983C9B32 C0C358AB 0823DCDF 7802389D AC92856D 9823ADFE EAC082CB

00010008 0001000C 00010014 0001001C

UG241_13-26_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF FFFFFFFF

0 F

DFCA2078 329B3C98 AB58C3C0 DFDC2308 9D380278 6D8592AC FEAD2398 CB82C0EA

UG241_13-27_041306




OPB to PCI Write TransactionsThe BFM stimuli for the OPB to PCI Write transactions are given in opb_pci_tb.vhd.o2p_wr and opb_pci.m4.o2p_wr. The procedure to perform the transaction is defined in Test_Process in opb_pci_tb.vhd.o2p_wr and invoked in Test_Process by the following procedures.

opb_pci_single_writeopb_pci_burst_write

Figure 13-27 shows a OPB to PCI single write transaction. The OPB master writes 0x12340000 address to OPB_ABus and 0x12345678 data to OPB_DBus. The OPB Bus master writes OPB_RNW = 0 and OPB_Select = 1. The transaction on the OPB ends when OPB_xferAck is asserted. Nine OPB_Clk cycles later, FRAME_N is asserted to identify the address phase of the PCI transaction. During the address phase, a memory write command (CBE[3:0] = 0x7) is generated. The address 0xC0000000 is output AD. FRAME_N is asserted for only one clock cycle to indicate a single write. The transaction on the PCI Bus occurs with data AD = 0x12345678 when IRDY_N, DEVSEL_N, and TRDY_N are asserted.

See Chapter 8 Address Translation for a description of the OPB ABus = 0x12340000 to PCI AD = 0xC0000000 translation.

Figure 13-27: OPB to PCI Single Write

00004008 C0000000 12345678 FFFFFFFF

UG241_13-28_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

12345678 00000000

12340000 00000000

FFFFFFFF

F 0 7 0 F




Figure 13-28 shows the complete OPB to PCI burst write transaction. The OPB master writes the 0x12340000 address to OPB_ABus and 0x12345678 to OPB_DBus. Address and data change on OPB_ABus and OPB_DBus in subsequent clock cycles. Nine OPB_Clk cycles later, FRAME_N is asserted to identify the address phase of the PCI transaction. During the address phase, a memory write command is generated with CBE[3:0] = 0x7. The address 0xC0000000 is output AD. FRAME_N is kept asserted for multiple clock cycles to indicate a burst write. The burst transaction on the PCI Bus begins with data AD = 0x12345678 when IRDY_N, DEVSEL_N, and TRDY_N are asserted.

Figure 13-28: OPB to PCI Burst Write

00000000

90ABCDEF

00000000

12340000

FFFFFFFF

UG241_13-29_041306

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF

F 0 7 0 F




Figure 13-29 shows the OPB signals in a OPB to PCI burst write operation. The OPB master writes OPB_RNW = 0, OPB_seqAddr = 1, and OPB_Select = 1. The transaction on the OPB ends when OPB_select and OPB_xferAck is de-asserted.

Figure 13-29: OPB to PCI Burst Write - OPB Signals

8 19C923DF FAC92CD5 92387CBE AC9238CF 018340C0 3298CAFC A9C8B2E2

12340020 12340024 12340028 1234002C 12340030 12340034 12340038

8 19C923D F 0 C

OPB_Cl

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

k

90ABCDEF

12340000

FFFFFFFF

F

87654321 28359183 AEC32FB8 7291A8FC B8D32950

12340004 12340008 1234000C 12340010 12340014

1039DF8A A398FDEC

12340018 1234001C

19C923DF FAC92CD5

12340020 12340024

92387CBE AC9238CF 018340CO

12340028 12340030 12340034

A9C8B2E2

12340038

00000000

000000001234002C

3298CAFC

87654321 28359183 AEC32FB 7291A8FC B8D32950 1039DF8A

12340004 12340008 1234000C 12340010 12340014 12340018

A398FDEC

1234001C

F FAC92CD5 92387CBE AC9238C 018340C 3298CAF A9C8B2E2 00000000

12340020 12340024 12340028 1234002C 12340030 12340034 12340038 00000000

00000000

See detail view of OPB_DBus/OPB_ABus clock periods below

00000000

UG241_6-30_041206Detail view of OPB_DBus/OPB_Abus signals clock periods




Figure 13-30 shows the PCI signals in a OPB to PCI burst write operation. FRAME_N is kept asserted for multiple clock cycles to indicate a burst write. The burst transaction on the PCI Bus begins with data AD = 0x12345678 when IRDY_N, DEVSEL_N, and TRDY_N are asserted.

Figure 13-31 shows the OPB to PCI single read transaction. On the OPB, OPB_ABus = 0x12340000, OPB_RNW = 1, and OPB_Select = 1 to start the transaction. On the PCI bus,

Figure 13-30: OPB to PCI Burst Write - PCI Signals

Figure 13-31: OPB to PCI Single Read

FFFFFFFF 12345678 C0000000 90ABCDEF 87654321 28359183 AEC32FB8 7291A8FC B8D32950 1039DF8A A398FDEC 19C923DF FAC92CD5 92387CBE AC9238CF 018340C0 3298CAFC A9C8B2E2FFFFFFFF 12345678 C0000000 90ABCDEF 87654321 28359183 AEC32FB8 7291A8FC B8D32950 1039DF8A A398FDEC 19C923DF FAC92CD5 92387CBE AC9238CF 018340C0 3298CAFC A9C8B2E2

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_seqAddr

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

00000000

FFFFFFFF

F 0 7 0 F

FFFFFFFF 12345678 C0000000 90ABCDEF 87654321 28359183 AEC32FB8 7291A8FC B8D32950 1039DF8A A398FDEC 19C923DF FAC92CD5 92387CBE AC9238CF 018340C0 3298CAFC A9C8B2E2

See detail view of AD signal clock periods section below

UG241_6-31_041206Detail view of AD signal clock periods

F

87654321

0000000000000000

00004008

C0000000

FFFFFFFF

87654321

UG241_6-32_041206

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

12340000

FFFFFFFF FFFFFFFF

F 0 6 0 F




when FRAME_N is asserted, a memory read is indicated with CBE = 0x6, and the address 0xC0000000 is generated on AD. The PCI transaction completes with IRDY_N, DEVSEL_N, and TRDY_N asserted, with data = 0x87654321 on AD.

Figure 13-32 shows the PCI signals responding to the OPB read. The one clock cycle FRAME_N indicates the read is a single. The PCI bus transaction completes with IRDY_N, DEVSEL_N, and TRDY_N asserted. At the right side of the figure, the OPB transaction is done.

Figure 13-32: OPB to PCI Single Read - PCI and OPB Data Signals

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

12340000

C0000000 FFFFFFFF 87654321 FFFFFFFF

0 6 0 F

UG241_6-33_041206

00000000

00004008

87654321




Figure 13-33 shows the OPB to PCI burst read transaction. The transaction begins with the generation of the read address on OPB_ABus = 0x12340000 with OPB_RNW, OPB_Select, and OPB_seqAddr asserted. Thirteen OPB_Clk cycles later, FRAME_N is asserted and a Memory Read Multiple (0x6) is generated on CBE, with 0x00001000 on AD. FRAME_N is held low to specify a burst.

Figure 13-33: OPB to PCI Burst Read

Figure 13-34: OPB to PCI Burst Read - PCI Signals

923C934F 8371C0BA EF9AC3CB 592831DF

00000000F

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

12340000

FFFFFFFF 00000000

F 0 C 0

FFFFFFFF C0000000 FFFFFFFF 12345678 A39C0F21 BCF9E203 7CD02A24 549CCEFA 923C934F 8371C0BA EF9AC3CB 592831DF

FFFFFFFF C0000000 FFFFFFFF 12345678 A39C0F21 BCF9E203 7CD02A24 549CCEFA 923C934F 8371C0BA EF9AC3CB 592831D

0000000012340008 12340010 12340018

12340020See detail view of AD signal clock periods below

Detail view of AD signal clock periods UG241_6-34_041306

7CD02A24

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000

12340000

FFFFFFFF FFFFFFFF C0000000 FFFFFFFF 12345678 A39C0F21 BCF9E203

F 0 C 0

UG241_6-35_041306



DMA OPB to PCI Write TransactionR

Figure 13-34 shows the OPB signals in the OPB to PCI burst read transaction. The transaction begins with the generation of the read address on OPB_ABus = 0x12340000 with OPB_RNW, OPB_Select, and OPB_seqAddr asserted. The first two words transferred on OPB_DBus with OPB_xferAck = 1 are 0x12345678 and 0xA39C0D21.

Figure 13-35 shows the PCI signals in the OPB to PCI burst read transaction. FRAME_N is asserted and a Memory Read Multiple (0x6) is generated on CBE, with 0x00001000 on AD. FRAME_N is held low on a burst.

DMA OPB to PCI Write TransactionThe BFM stimuli for the DMA OPB to PCI Write transactions are given in opb_pci_tb.vhd.dma_o2p_wr and opb_pci.m4.dma_o2p_wr. The procedure to perform the transaction is defined in Test_Process in opb_pci_tb.vhd.dma_o2p_wr and invoked in Test_Process by the following procedures.

dma_opb_pci_write

Figure 13-35: OPB to PCI Burst Read - OPB Signals

592831DF

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

0 F

FFFFFFFF

UG241_6-36_04130

0000000012340008

00000000

BCF9E203 7CD02A24 549CCEFA

12340004 1234000C12340000

549CCEFA 923C934F 8371C0BA EF9AC3CB 592831DF

12345678 00000000 00000000 923C934F 00000000 00000000A39C0F21 8371C0BA EF9AC3CB

12340010 12340014 12340018 1234001C 12340020

00000000

00000000

00000000

12340008

BCF9E203 7CD02A24 549CCEFA

12340004 1234000C12340000

549CCEFA 923C934F 8371C0BA EF9AC3CB 592831DF

1234567800000000 00000000 923C934F 00000000 00000000A39C0F21 8371C0BA EF9AC3CB

12340010 12340014 12340018 1234001C 12340020

00000000

See detail view of OPB_DBus, OPB_ABus, and AD signals clock periods below

Detail view of OPB_DBus. OPB_Abus, and AD signals clock periods

00000000




Figure 13-36 shows the setup for a DMA OPB to PCI write transaction. The DMA base address is C_DMA_BASEADDR = 0x31000000. The DMA control register, at OPB_ABus = 0x31000004, is written with OPB_DBus = 0xD8000000. The source address, at OPB_ABus = 0x31000008, is written with OPB_DBus = 0x20000000. The destination address, at OPB_ABus = 0x3100000C is written with OPB_DBus = 0x12340000.

Figure 13-37 shows the OPB signals in the DMA OPB to PCI write transaction. To start the DMA operation, the length of 40 (64 bytes) is written to OPB_ABus = 0x31000010. When OPB_RNW, OPB_Select, and OPB_seqAddr are high, the burst of 16 words (64 bytes) is generated.

Figure 13-36: DMA of OPB to PCI Write Setup

Figure 13-37: DMA OPB to PCI Write - OPB Signals

D8000000 20000000 12340000

31000004 31000008 3100000C

FFFFFFFF

F

UG241_6-37_041406

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

00000000 00000000 00000000

00000000

20000000

20000004

20000008

2000000C

20000010

20000014

20000018

2000001C20000020

20000024

20000028

2000002C20000030

2000003420000038

2000003C

00000000

UG241_6-38_041406

00000040 00000000

31000010 00000000

FFFFFFFF

F

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

AD

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK



Reset TransactionsR

Figure 13-38 shows the transactions on the PCI bus. When FRAME_N is asserted, a Memory Write (0x7) is generated on CBE. The address 0xC0000000 is output AD. The target is not present in this simulation, so the transaction results in a Master Abort.

Reset TransactionsThe BFM stimuli for reset transactions are given in opb_pci_tb.vhd.reset and opb_pci.m4.reset. The procedures to perform the transactions are defined in Test_Process in opb_pci_tb.vhd.reset and invoked in Test_Process by the following procedures.

• Reset_IPIF : generates a pulse on Reset

• Reset_PCI : generates a pulse on RST_N

• Reset_IPIF_PCI_Simultaneously : generates simultaneous pulses on Reset and RST_N

Table 13-2 shows the tests and active time of the reset tests done in opb_pci.m4.reset and opb_pci_tb.vhd.reset. Excerpts of these tests are given in the next figures. In the tests, a reset is done, and the registers are read to verify that the reset occurred. Chapter 4 Functionality provides the register names, abbreviations, and locations needed to understand the waveform output.

Figure 13-38: DMA OPB to PCI Write - PCI Signals

FFFFFFFF

00000000

00000000

00004008 C0000000 00000000 FFFFFFFF

F 0 7 F0

OPB_seqAddr

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

V3_CLK

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

PCLK

AD

UG241_6-39_041406

Table 13-2: Reset Tests

Test Active Time

Power On Reset 400 ns - 3400 ns

Register Write/Read 3400 ns - 21000 ns

Soft Reset 21000 ns - 26000 ns

Hard Reset 26000 ns - 4500 ns




Figure 13-39 shows the transcript window output identifying the reset operation and register read/write operations. If interested in a specific test or operation, double clicking on the test in the transcript window causes the cursor in the Waveform Viewer to move to the selected location.

Figure 13-39: Transcript Window Output when running Reset tests

UG241_6-40_041406



Reset TransactionsR

Figure 13-40 shows the complete 40 us run of the reset test. Only a few of the registers tested are included in this and the next figures. Additional registers can be added in either the simulation or waveform log files (wlf).

Figure 13-41 shows the start of the power on reset test. This verifies that the values of the registers are the same as indicated in the OPB PCI product specification. Only three registers are shown. All registers are tested, and visible if the waveform is scrolled left.

Figure 13-40: Full View of Reset Test

Figure 13-41: Power On Reset Test

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

IP_IRPT_STATUS_reg

IP_IRPT_ENABLE_reg

PIF_GLBL_IRPT_ENABLE

CAP_reg

SBN_reg

AD

00000000 00000000

00000000 30000080 30000000 30000004 30000008

0000000000000

0000000000000

00000000

00000000

FFFFFFFF

20097B01

00000000 00000000 00000000 00000000

UG241_6-42_041406




Figure 13-42 shows the start of the register write/read test.

Figure 13-43 shows the values of registers following a soft reset. A soft reset requires C_INCLUDE_RESET_MODULE = 1. A soft reset is done by a write of 0xA to the register located at C_BASEADDR + 0x80. This test includes a negative test, in which 0xF is written to the reset register, and the verification is that the reset operation does not occur.

Figure 13-42: Register Write/Read Test

Figure 13-43: Soft Reset

UG241_6-42_041406

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

IP_IRPT_STATUS_reg

IP_IRPT_ENABLE_reg

IPIF_GLBL_IRPT_ENABLE

CAP_reg

SBN_reg

AD

00000000 0000007D 00000000 00000000 000000FF

30000008 30000008 00000000 30000018 30000018

0000000000000

0000000000000

00000000

00000000

FFFFFFFF

0000007D

00000080

0000000030000008

00000000 00000000 00000000

OPB_Clk

OPB_Select

OPB_RNW

OPB_xferAck

OPB_DBus

OPB_ABus

IP_IRPT_STATUS_reg

IP_IRPT_ENABLE_reg

IPIF_GLBL_IRPT_ENABLE

CAP_reg

SBN_reg

AD

0000000F 00000000 00000000 00000000 00000000

30000080 30000000 30000004 30000008 30000018

1111111111111

1111111111111

80FFFFFC

11111111

FFFFFFFF

00000000 00000004 00000004

00000000 00000000 00000000 00000000

0000007D 00000002

00000000

UG241_6-44_041406



Comprehensive OPB PCI TestbenchR

Figure 13-44 shows some of the register values after a hard reset. In this test, RST_N is generated by the VHDL testbench.

Comprehensive OPB PCI TestbenchThe design files include an exhaustive testbench for the OPB PCI. It is divided into sections, and the sections run are enabled using a test control matrices located in the opb_pci_tb.vhd and opb_pci.m4 files. Table 13-3 shows the selection matrix used. The same test must be selected in both the opb_pci.m4 and opb_pci_tb.vhd files.

Figure 13-44: Hard Reset

UG241_6-45_041406

OPB_xferAck

OPB_DBus

OPB_ABus

OPB_Rst

IP_IRPT_STATUS_reg

IP_IRPT_ENABLE_reg

PIF_GLBL_IRPT_ENABLE

CAP_reg

SBN_reg

AD

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

RST_N

00000000

00000000

1111111111111

1111111111111

10000000111111111111111111111100

11111111

FFFFFFFF

F

00000000

30000000 30000008 3000001C

30000004 30000018

00000000

FFFFFFFF

00000000

FFFFFFFF 30000190

3000018C30000190

3000019430000194

Table 13-3: OPB PCI Bridge BFM Simulation Test Control Matrix

Test Control Matrix

Power On Reset

Register Write Read Reset

Configuration Test

Abnormal Configuration Test

System Error on Configuration Write

System Error on Configuration Read

Parity Error on Configuration Write

Parity Error on Configuration Read

System Error /Parity Error Configuration Read

Bridge Master Abort Configuration Write




PCI Retry on Configuration Write

Target Abort on Configuration Write

Target Abort on Configuration Read

Bridge Master Abort on Configuration Read

PCI Retry on Configuration Read

Target Disconnect with Data on Configuration Write

Target Disconnect with Data on Configuration Read

OPB PCI Write Test

Abnormal OPB PCI Write Test

System Error During Address Phase OPB2PCI Write

System Error During Data Phase OPB2PCI Write

Parity Error During Data Phase OPB2PCI Write

Bridge Master Abort During OPB2PCI Write

PCI Retry During OPB2PCI Write

Target Abort During Configuration Write

Target Disconnect with Data During Burst OPB2PCI Write

Target Disconnect without Data During Burst OPB2PCI Write

Latency Timer Expire During Burst OPB2PCI Write

FIFO Overrun During OPB2PCI Write

Target Disconnect with Data During Single Write

Invalid Address During Burst OPB2PCI Write

OPB2PCI Read Test

Abnormal OPB2PCI Read Test

System Error During Data Phase OPB2PCI Read

System Error / Parity Error During Address Phase OPB2PCI Read

Parity Error During Data Phase OPB2PCI Read

Target Abort During OPB2PCI Read

PCI Retry During OPB2PCI Read

Target Disconnect with Data During Single OPB2PCI Read

Bridge Master Abort During OPB2PCI Read

PCI2OPB Write Test

Abnormal PCI2OPB Write Test

Table 13-3: OPB PCI Bridge BFM Simulation Test Control Matrix (Continued)

Test Control Matrix



BFM Simulation SetupR

BFM Simulation SetupBFM simulation of the OPB PCI core is supported using the ModelSim™ simulator, running on Linux and Windows operating systems. BFM simulation is setup using the following steps. The bfm_8.1.exe and edk_bfm.zip files in the <opb_pci_proj>/bfmsim/install_files directory are used to set up BFM simulation in EDK. A license is available from

http://www.xilinx.com/ipcenter/processor_central/register_coreconnect.htm

1. Run the bfm_8.1.exe self extracting executable from the command prompt:

bfm_8_1.exe

2. Copy edk_bfm.zip to the $XILINX_EDK (%XILINX_EDK%) directory. Unzip edk_bfm.zip. (1) .

3. Add $XILINX_EDK/gnu/bin/nt to $PATH.

4. If the unisim, simprim, XilinxCoreLib, and Smartmodel libraries have not been compiled, compile them from EDK using

EDK Options → Project Options → HDL and Simulation

Enter the paths for EDK_Lib and ISE_Lib. Click Compile.

System Error During Data Phase PCI2OPB Write

Parity Error During Address Phase PCI2OPB Write

Parity Error During Data Phase PCI2OPB Write

PCI2OPB Read Test

Abnormal PCI2OPB Read Test

System Error During PCI2OPB Read

Parity Error During PCI2OPB Read

IPIF2PCI FIFO

Table 13-3: OPB PCI Bridge BFM Simulation Test Control Matrix (Continued)

Test Control Matrix

1. Verify the installation by checking that the <EDK_install_dir>\gnu directory contains proc_defs.m4, gen_bfl_do, and m4.exe files. Verify that the <EDK_install_dir\hw\XilinxBFM_interface\pcores contains the xil_bfm_v1_00_a library. Verify xilbfc.exe is in <EDK_install_dir>\bin\nt




Figure 13-45 shows the compilation of simulation libraries.

Running a BFM Simulation of the OPB PCIAn EDK BFM simulation of the OPB PCI core uses the opb_pci_tb.vhd testbench, located in the <opb_pci_proj>/bfmsim/pcores/opb_pci_tb_v1_02_a library, and BFM stimuli, located in the <opb_pci_proj>/bfmsim/scripts directory. The OPB PCI core interfaces to the BFM and VHDL testbench as shown in Figure 13-16. The BFM writes/reads to the OPB PCI registers to configure the OPB PCI. After configuration, OPB to PCI transactions are simulated by the BFM generating stimuli (OPB bus transactions) and the opb_pci_tb.vhd verifying the expected results. To verify PCI to OPB transactions, the opb_pci_tb.vhd generates stimuli (PCI bus transactions), and the BFM verifies the expected results on the OPB.

The steps to run a BFM simulation of the OPB PCI core are given below for ModelSim.

4. Change to the <opb_pci_proj>/bfmsim directory and run

simgen -f simgen.opt

Figure 13-45: Compiling EDK and ISE Simulation Libraries

UG241_13-3_041306

Figure 13-46: BFM Simulation of OPB PCI core

UG241_3-46_041406

BFMopb_pci.do

OPB PCI opb_pci_tb.vhd



Running a BFM Simulation of the OPB PCIR

The -E option in the bfm_sim_cmd.make or simgen.opt file must contain the correct path to the EDK simulation library.

5. Change to the <opb_pci_proj>/bfmsim/simulation/behavioral directory and read the bfm_system.do file. Verify that the libraries/files needed in simulation, including xil_bfm_v1_00_a, are either in the modelsim.ini / cds.lib file or are compiled in bfm_system.do / system.sh file. Optionally, remove all EDK libraries already mapped in the modelsim.ini / cds.lib file. If not present, add the following lines to bfm_system.do. (1)

vlib xil_bfm_v1_00_a

vmap xil_bfm_v1_00_a ./xil_bfm_v1_00_a

vcom -93 -work xil_bfm_v1_00_a$XILINX_EDK/hw/XilinxBFMinterface/pcores/xil_bfm_v1_00_a/hdl/vhdl/xil_bfm_pkg.vhd

6. The BFM stimuli is in the <opb_pci_proj>/bfmsim/scripts directory. The opb_pci.m4 and opb_pci_defs.m4 files are located in the <opb_pci_proj>/bfmsim/scripts/m4 directory. The flow to generate BFM stimuli is illustrated in Figure 13-47.

Optionally, regenerate <opb_pci_proj>/bfmsim/scripts/opb_pci.bfl / opb_pci.do files by running

gen_bfl_do opb_pci

from the <opb_pci_proj>/bfmsim/scripts/m4 directory. This script, located in $XILINX_EDK/gnu/m4/bin/nt, calls the m4 and xilbfc.exe executables, and generates the opb_pci.do / system.sh file. The m4 documentation is in the $XILINX_EDK/gnu/m4/doc directory.

7. From the <opb_pci_proj>/bfmsim/simulation/behavioral directory, run in ModelSim

do ../../scripts/run.do

The run.do file can be used to change the run parameters. The wave.do file is used to invoke the waveform viewer with the simulation results.

For a detailed understanding of the simulation, read the following files.

<opb_pci_proj>/bfmsim/scripts/m4/opb_pci.m4 (opb_pci_defs.m4)

<opb_pci_proj>/bfmsim/pcores/opb_pci_tb_v1_02_a/hdl/vhdl/opb_pci_tb.vhd

1. If the -X option is not included in simgen.opt, the ISE libraries are not listed in this file, which is generally desirable if they are already mapped in the modelsim.ini / cds.lib file. Currently, the -E option in simgen.opt cannot be removed from simgen.opt to avoid duplication of the EDK libraries.

Figure 13-47: Development of BFM stimuli to OPB PCI

UG241_3-47_041406

m4 xilbfcopb_pci.bfl opb_pci.do

opb_pci_defs.m4Simulatoropb_pci.m4



R

Chapter 14

System Simulation

In this chapter, a system simulation is done using a software project and a VHDL model of the system. The C code is compiled, and simulated with all the instances defined in the system.mhs file. A configuration transaction is simulated, with writes/reads of the Configuration Address Port/Configuration Data Port.

A completed project is provided in the sys_sim directory. This software contains simple microprocessor transactions. The flow for system simulation is provided to allow more complex simulations.

Support files are in:


Simulating with EDKThe code in the hello_world project is given in Figure 14-1. This generates a reset and writes/reads the Configuration Address Port and Configuration Data Port to configure the Command Status Register in the configuration header.

This chapter uses the sys_sim/Hello_World project. Other software projects in the sys_sim directory which can be developed are given below.

Simple_PCI_Config

PCI_interrogate

xpci_example_level_0

The source code is located in the sys_sim/code directory.



Chapter 14: System SimulationR

The software projects discussed in this chapter are loaded into BRAM. The size of BRAM is limited, and determined by C_BASEADDR/C_HIGHADDR of the plb_bram_if_cntlr. Large programs cannot be loaded into BRAM. In this project, the plb_bram_if_cntlr C_BASEADDR is set to 0xFFFF0000, which is 64K of BRAM.

Figure 14-1: Hello World Source Code

#include “xparameters.h”#include “xuartlite_l.h”#include “xpci_l.h”#include “stdio.h”#include “xutil.h”#define BASEADDR XPAR_PCI32_BRIDGE_BASEADDR

// Function prototypesvoid write_to_config_addr_reg(unsigned int value);unsigned int read_from_config_addr_reg(void);void write_to_config_data_reg(unsigned int value);unsigned int read_from_config_data_reg(void);

int main (void){

unsigned int i = 0;unsigned int temp = 0; XPci_mReset(BASEADDR); // Reset core

write_to_config_addr_reg(0x04400080); // Write CAPtemp = read_from_config_addr_reg(); // Read CAP

write_to_config_data_reg(0x86002002); // Write CDPtemp = read_from_config_data_reg(); // Read CDPreturn 0;

}

void write_to_config_addr_reg(unsigned int value){ XPci_mWriteReg(BASEADDR, XPCI_CAR_OFFSET, value);

unsigned int read_from_config_addr_reg(void)unsigned int temp = 0;temp = XPci_mReadReg(BASEADDR, XPCI_CAR_OFFSET);return (temp);

}

void write_to_config_data_reg(unsigned int value){XPci_mWriteReg(BASEADDR, XPCI_CDR_OFFSET, value);

unsigned int read_from_config_data_reg(void)unsigned int temp = 0;temp = XPci_mReadReg(BASEADDR, XPCI_CDR_OFFSET);return (temp);

}

UG241_14-1_041706



Running System SimulationsR

Running System SimulationsSince the completed project is provided, the simulation can be run without the setup steps described later in this chapter. The directories under sys_sim with simulation files are simulation/behavioral and scripts. To run the simulation, compile the simulation libraries, change to the sys_sim/simulation/behavioral directory, and enter


Figure 14-2 is the run.do file. Some simulations require changing the run time in this file.

Setup of a System SimulationSetup of a system simulation involves compiling libraries, build a software project, and generating the simulation HDL and do files. It is generally necessary to change the options in simgen.opt when generating simulation files. The testbench, system_tb.vhd, generated when generating simulation files requires minor editing. The same flow for setting up a system simulation is used for both the PowerPC and MicroBlaze microprocessors.

Figure 14-2: run.do file

do system.dovsim -t ps work.system_tb_confdo wave.dorun 20 us

UG241_14-02_041706

Figure 14-3: Compiling Simulation Libraries

UG241_14-03_041006




Figure 14-3 shows the compilation of the ISE and EDK simulation libraries. In EDK, enter Simulation -> Compile Simulation Libraries. Enter the locations of the libraries. The SmartModel is for the PPC405 used in this flow.

Figure 14-4 shows the selection of the hello world project. If code is added, build this project by selecting the project, right clicking, and selecting Build Project.

Figure 14-4: Software Project for Simulation

UG241_14-04_041006



Setup of a System SimulationR

Set the OPB PCI generics as needed. Figure 14-5 shows how to use the System Assembly View to set the generics. Right click on the OPB PCI bridge and select Configure IP. Select the values for the generics.

When simulating a OPB_Uartlite, changing the baud rate may help view results in the waveform viewer.

Figure 14-5: Setting OPB PCI Generics

Figure 14-6: Running simgen

UG241_14-05_041006

UG241_14-06_041006




Figure 14-6 shows how to run simgen from EDK. Enter

Simulation -> Generate Simulation HDL Files

This creates a simulation/behavioral directory with the simulation files. Edit simgen.opt in the project’s root directory. Remove the -X option so that the ISE Libraries are not re-generated. Add the -tb option to automatically generate a testbench. Rerun Generate Simulation HDL Files so that the new options in simgen.opt are used.

The simulation files in the simulation/behavioral directory which require editing are the system_tb.vhd and the system.do file. The system.do may work as is, but some cleanup is generally desired. Figure 14-7 is the system.do file in which EDK libraries already defined in modelsim.ini are removed.

The system_tb.vhd requires the edits provided in the following figures. The sys_sim/simulation/behavioral/system_tb.vhd contains the completed edits.

Comment the following lines in the simulation/behavioral/system_tb.vhd file.

-- library system;

-- use system.All;

Figure 14-7: Modified system.do File

vlib plb_bram_if_cntlr_1_bram_elaborate_v1_00_avmap plb_bram_if_cntlr_1_bram_elaborate_v1_00_a plb_bram_if_cntlr_1_bram_elaborate_v1_00_avlib util_inverter_v1_00_avmap util_inverter_v1_00_a util_inverter_v1_00_avlib workvmap work workvcom -93 -work plb_bram_if_cntlr_1_bram_elaborate_v1_00_a elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/plb_bram_if_cntlr_1_bram_elaborate.vhdvcom -93 -work util_inverter_v1_00_a H:/designs/sys_sim/pcores/util_inverter_v1_00_a/hdl/vhdl/util_inverter.vhdvcom -93 -work work ppc405_0_wrapper.vhdvcom -93 -work work ppc405_1_wrapper.vhdvcom -93 -work work jtagppc_0_wrapper.vhdvcom -93 -work work reset_block_wrapper.vhdvcom -93 -work work plb_wrapper.vhdvcom -93 -work work opb_wrapper.vhdvcom -93 -work work plb2opb_wrapper.vhdvcom -93 -work work rs232_wrapper.vhdvcom -93 -work work plb_bram_if_cntlr_1_wrapper.vhdvcom -93 -work work plb_bram_if_cntlr_1_bram_wrapper.vhdvcom -93 -work work opb_intc_0_wrapper.vhdvcom -93 -work work opb_pci_0_wrapper.vhdvcom -93 -work work pci_arb_0_wrapper.vhdvcom -93 -work work dcm_0_wrapper.vhdvcom -93 -work work dcm_pci_wrapper.vhdvcom -93 -work work pci_reset_inversion_wrapper.vhdvcom -93 -work work system.vhdvcom -93 -work work system_init.vhdvcom -93 -work work system_tb.vhd

UG241_14-07_041706




Add the reset and clock processes in Figure 14-8 to the system_tb.vhd.

Figure 14-9 shows the assignment of initial values to PCI signals which must be added to the testbench.

Figure 14-8: Reset and Clock Processes in Testbench

Figure 14-9: Assigning Initial Values to signals in system_tb.vhd

sys_rst_gen : process begin sys_rst_pin <= ‘0’; wait for 200 ns; sys_rst_pin <= ‘1’; wait for 200 ns; sys_rst_pin <= ‘0’; wait; end process;

sys_clk_gen : process begin sys_clk_pin <= ‘1’; wait for 5 ns; sys_clk_pin <= ‘0’; wait for 5 ns; end process;

UG241_14-1_041706

fpga_0_RS232_sin_pin <= ‘H’; fpga_0_RS232_ctsN_pin <= ‘L’;

PCI_INTA <= ‘0’;PCI_INTB <= ‘0’;PCI_INTC <= ‘0’;PCI_INTD <= ‘0’;

-- Check the polarity of all of these signals!!! PCI_PMC_REQ <= ‘H’;PCI_CB_REQ <= ‘H’; PCI_PERR_N <= ‘H’; PCI_SERR_N <= ‘H’; PCI_IRDY_N <= ‘H’; PCI_FRAME_N <= ‘H’; PCI_DEVSEL_N <= ‘H’; PCI_STOP_N <= ‘H’; PCI_TRDY_N <= ‘H’;

UG241_14-09_041706




Add the configuration statement shown in Figure 14-10 to the testbench.

Figure 14-11 shows the results from running the simulation, which is done by entering


from the simulation/behavioral directory.

The transcript window shows the values of the PPC405 general purpose registers.

Figure 14-10: Configuration statement in system_tb.vhd

Figure 14-11: System Simulation in Modeltech

configuration system_tb_conf of system_tb isfor behavior for dut:system for STRUCTURE for all : plb_bram_if_cntlr_1_bram_wrapper use configuration work.plb_bram_if_cntlr_1_bram_conf; end for; end for; end for;end for;end system_tb_conf;

UG241_14-10_041706

UG241_14-11_041006




Figure 14-12 shows the creation and addition of signals to the Waveform Viewer. Select

View -> Signals

to create the Signals window. Select an instance in the Design Browser tree, and highlight signals in the Signals window which should be exported to the Waveform Viewer. From the Signals window, enter

Add -> To Wave Window -> Selected Signals

Figure 14-12: Invoking the Signal Window

UG241_14-12_041006




Selecting different instances in the design hierarchy causes different signals to be displayed in the Signal window, from which they are added to the Waveform Viewer. Figure 14-13 is an example of how to add v3.0 configuration signals to the Waveform Viewer.

Select the PCI32_Bridge, and add cfg_self, cfg_vld, cfg_hit, c_term, and c_ready to the Wave window.

Figure 14-13: Browsing the Instances in the Design Hierarchy

UG241_14-13_041006




In configuration, the method used for IDSEL selection is important. Figure 14-14 shows how to add all IDSEL related signals.

After a simulation is run, if there is no activity on the v3.0 configuration signals added in the previous figure, a likely cause is that C_INCLUDE_PCI_CONFIG, C_INCLUDE_DEVNUM_REG, or C_BRIDGE_IDSEL_ADDR_BIT is not setup correctly.

The subsequent figures show the simulation output of system simulation.

Figure 14-14: Selecting the IDSEL Signals

UG241_14-14_041006




Figure 14-15 shows the reset operation. This requires that C_INCLUDE_RESET_MODULE = 1. The reset register is located at C_BASEADDR + 0x80, which is 0x3C000080. To reset the IPIF registers, OPB_DBus = 0x0000000A is written. As a result, the bus2ip_reset_i signal is asserted. There is no activity on the PCI RST_N pin.

Figure 14-15: Reset

UG241_14-15_041006

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_Clk

OPB_Rst

AD

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

IDSEL

RST_N

bus2ip_reset_i

00000000 3C000080 00000000

00000000 0000000A 00000000

FFFFFFFF

F




Figure 14-16 shows the start of configuration, which is a write to the Configuration Address Port (CAP). The CAP is located at C_BASEADDR + 0x10C, which is 0x3C00010C. The Command Status Register is located at offset 0x04 in the configuration header, so the value written to OPB_DBus is 0x04000080. The write to the CAP does not cause any signal activity on the v3.0 configuration signals.

Figure 14-16: Writing the Configuration Address Port for the CSR

k

d

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_Cl

OPB_Rst

AD

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

IDSEL

RST_N

bus2ip_reset_i

IDSEL_int

CFG_vl

CFG_hit

CFG_self

00000000 3C00010C 00000000

00000000 04400080 00000000

FFFFFFFF

F

UG241_14-16_041006




Figure 14-17 is a read of the value in the Configuration Address Port just written.

Figure 14-17: Reading the Configuration Address Port for the CSR

UG241_14-17_041006

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_Clk

OPB_Rst

AD

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

IDSEL

RST_N

bus2ip_reset_i

IDSEL_int

CFG_vld

CFG_hit

CFG_self

00000000 3C00010C 00000000

00000000

FFFFFFFF

F

00000000

04400080




Figure 14-18 shows a write to the Configuration Data Port to load the Command Status Register.

The signal activity on the v3.0’s configuration signals mean that the C_INCLUDE_PCI_CONFIG, C_INCLUDE_DEVNUM_REG, and C_BRIDGE_IDSEL_ADDR_BIT are set correctly.

Figure 14-18: Writing the Configuration Data Port for the CSR

01000004

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OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_Clk

OPB_Rst

AD

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

IDSEL

RST_N

bus2ip_reset_i

IDSEL_int

CFG_vld

CFG_hit

CFG_self

3C000110 00000000

86002002 00000000

FFFFFFFF 02200086

F B 0




Figure 14-19 is the reading of the Configuration Data Port just written.

Figure 14-19: Reading the Configuration Data Port (CSR)

01000004 FFFFFFFF 0200054601000004 FFFFFFFF 02000546

OPB_ABus

OPB_DBus

OPB_Select

OPB_RNW

OPB_Clk

OPB_Rst

AD

CBE

FRAME_N

TRDY_N

IRDY_N

STOP_N

DEVSEL_N

IDSEL

RST_N

bus2ip_reset_i

IDSEL_int

CFG_vld

CFG_hit

CFG_self

3C000110

0000000000000000

FFFFFFFF

0 A 0

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R

Chapter 15

Software Projects

Design FilesThe design files contain the following software projects to run with this reference system. In each software project directory, there are src and results sub-directories for the source code and Hyperterminal results, respectively.

SW ProjectsTestApp_Memory. This project tests the memory on the Xilinx development boards.

TestApp_Peripheral.This project verifies that the OPB Sysace (if used) is used correctly.

hello_pci. This code enables master transactions, sets the latency timer, defines the bus number/subordinate bus number, and scans the ML310 configuration registers.

xpci_tapp_example. This project contains two major functions which use level 0 drivers: PciInitLevel_0() and ShowPCI(). PciInitLevel reads and writes the bus and subordinate bus number, initializes the bridge device number if present, and performs configuration writes to the PCI header to setup the bridge. The latency timer is set to the maximum. The BAR registers are set, and interrupts are enabled.

xpci_example_level_0. This project uses level 0 drivers to initialize the PCI bridge. It then initializes a device on the PCI bus, and prints messages describing the bridge and memory mappings.

xpci_example_level_1. This project initializes the OPB PCI bridge and a device on the PCI bus. It then initializes Direct Memory Access (DMA) and runs local to DMA and DMA to local transfers. The PciIsr() function handles interrupts. The OPB PCI Bridge supports simple but not scatter gatter DMA. Simple DMA is enabled by setting C_DMA_CHAN_TYPE = 0. The Direct Memory Access and Scatter Gather product specification provides information on the use of the DMA function in the IPIF. The base address for DMA is C_DMA_BASEADDR = 0x3D000000. Figure 15-1 lists the registers used in DMA setup.

Table 15-1: DMA Registers

DMA Register Address

Control Register C_DMA_BASEADDR + 0x04

Source Address Register C_DMA_BASEADDR + 0x08

Destination Address Register C_DMA_BASEADDR + 0x0C

Length Address Register C_DMA_BASEADDR + 0x10



Chapter 15: Software ProjectsR

The code which transfers DMA data is given in Figure 15-1.

Figure 15-1: C Code for DMA Operation

* PciDmaTransfer - interrupt driven DMA to/from a device on the PCI bus * * Parameters: * LocalAddress - address of a local memory device such as SRAM, DDR, etc. * Address - address local to the processor that maps to the PCI bus * Bytes - bytes to transfer * Direction - direction to transfer, 0 = local to , 1 = to local *****************************************************************************/void PciDmaTransfer(Xuint32 LocalAddress, Xuint32 Address, Xuint32 Bytes, int Direction){ Xuint32 DmaSrc; Xuint32 DmaDest;

/* setup transfer direction */ if (Direction == 0) { /* local to PCI */ XDmaChannel_SetControl(&Bridge.Dma, XDC_DMACR_SOURCE_INCR_MASK | XDC_DMACR_DEST_INCR_MASK | XDC_DMACR_DEST_LOCAL_MASK); DmaSrc = LocalAddress; DmaDest = Address; } else if (Direction == 1) { /* PCI to local */ XDmaChannel_SetControl(&Bridge.Dma, XDC_DMACR_SOURCE_INCR_MASK | XDC_DMACR_DEST_INCR_MASK | XDC_DMACR_SOURCE_LOCAL_MASK); DmaSrc = Address; DmaDest = LocalAddress; } else { printf("Invalid direction argument. Must be 0 or 1\n"); return; }

/* begin transfer */ XDmaChannel_Transfer(&Bridge.Dma, (Xuint32*)DmaSrc, (Xuint32*)DmaDest, Bytes);

/* wait for completion */ SemaphoreTake(&Bridge.DmaSemaphore); printf("Dma Transfer complete\n");}

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Running the ApplicationsR

Running the ApplicationsIn EDK, select the Applications tab, Software Projects, Add SW Applications Projects. Name the software project (e.g. TestApp_Memory), and add the files from the software project src directory to the Source Files area. Figure 15-2 illustrates how to make the hello_pci project active and the remaining software projects inactive.

Select hello_pci and right click to build the project.

Connect a serial cable to the RS232C port on the board. Start up a HyperTerminal. Set the baud rate to 9600, number of data bits to 8, no parity, and no flow control, as shown in Figure 15-3. If a board other than the ML310 is used, a null modem may be required.

Figure 15-2: Selecting the hello_pci Software Project

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From XPS, start XMD and issue ppc and rst. Invoke GDB and select Run to start the application as shown in Figure 15-4. The Hyperterminal output should be similar to that in the <software_project>/results directory.

Figure 15-3: HyperTerminal Connections

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Running the ApplicationsR

Figure 15-4: hello.c

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R

Chapter 16

Monta Vista Linux

This chapter provides guidelines for building and booting a Monta Vista Linux kernal.

Building and Booting a Linux KernelThe steps to build and boot a linux kernel are given below. Steps 1-3, 7, 8 are run on a Linux machine with MontaVista Professional Edition© installed.

1. Add /opt/montavista/pro/host/bin and /opt/montavista/pro/devkit/ppc/405/bin to $PATH.

2. Create and change to the <opb_pci_proj>/linux_pci directory.

3. Run tar cf - -C /opt/montavista/pro/devkit/lsp/xilinx-ml300-ppc_405/linux-2.4.20_mv31/ . tar xf -.

4. To generate the Linux LSP in XPS, enter Project Software → Platform Settings and select Kernel and Operating Systems and select linux_mvl31 1.00.a for ppc405_0.

5. Under Library/OS Parameters, set the entries as shown in Figure 16-1.



Chapter 16: Monta Vista LinuxR

Verify that the target directory is the same as the directory containing the Linux source.

6. Click Connected_Periphs and add OPB_INTC, OPB_SYSACE, OPB_PCI, OPB_GPIO, OPB_IIC, and OPB 16550 entries as shown in Figure 16-2.

Click OK.

7. Select Tools → Generate Libraries and BSPs to generate LSP in <opb_pci_proj>/linux_pci.

8. The <opb_pci_proj>/linux_pci/.config is used to generate the Linux kernel. An alternative is to enter make menuconfig and generate a new .config.

9. Run make clean dep bzImage. Verify that the zImage.elf file is in <opb_pci_proj>/linux_pci/arch/ppc/boot/images directory.

Figure 16-1: BSP Settings

Figure 16-2: Connected Peripherals

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Building and Booting a Linux KernelR

10. Invoke Impact and download implementation/download.bit to xc2vp30. One method of doing this uses the command below.

11. impact -batch etc/download.cmd

12. Invoke XMD. From the <opb_pci_proj>/linux_pci directory, enter the following commands in the XMD window.

rst

dow arch/ppc/boot/imagest/zImage.elf

con

13. View the output in the HyperTerminal window. Login as root with 310ml as password. Enter cd / and ls -l to view the contents of the mounted Linux partition of the Compact Flash (CF).

14. Enter lspci to view the PCI devices. For each line of output, the first 2 digits represent the PCI bus number, followed by the device number and function number.

15. An alternative to downloading the Linux kernel executable is to load it into CompactFlash. The file used uses an ace file extension. To generate an ace file, run the command below from the <opb_pci_proj> directory.

xmd -tcl ../genace.tcl -jprog -hw ../implementation/system.bit -ace ../implemetation/ace_system_hw.ace -board ml310

Copy the ace file to the 64-512 MB CompactFlash card in a CompactFlash reader/writer. Remove the CF from the CF reader/writer and insert it into the CompactFlash slot (J22) on the ML310 board. Power up the board.



Chapter 16: Monta Vista LinuxR



R

Chapter 17

Chipscope

This chapter provides guidelines for inserting ChipsSoope to monitor OPB PCI Bridge signals. This is useful in debugging OPB PCI Bridge problems.

Using ChipScope with OPB PCITo facilitate the use of ChipScope to analyze OPB PCI hardware, opb_pci.cdc, opb_pci.ctc, and opb_pci.cpj files are included in the chipscope directory. The opb_pci.cdc is used to insert ChipScope ILA core into the opb_pci_1_wrapper core. Use the steps below to insert a core and to analyze problems with ChipScope.

1. Invoke XPS. Run Tools → Generate Netlist.

2. In the opb_pci.cdc file, change the path <design_directory> name to the directory in which the design files are installed. Three paths need to be changed.

3. Backup implementation/opb_pci_0_wrapper.ngc.

4. Start → Programs → ChipScope Pro → ChipScope Inserter

From ChipScope Inserter, File → Open Project opb_pci.cdc. Figure 17-1 shows the ChipScope Inserter setup GUI.



Chapter 17: ChipscopeR

5. 6. Click Next to move to the Modify Connections window. If there are any red data or trigger signals, correct them. The Filter Pattern can be used to find the correct net(s). As an example of using the Filter Pattern, enter *AD* in the dialog box to locate AD signals. Select the net and click Make Connections. Figure 17-2 shows net connections.

Figure 17-1: ChipScope Inserter Setup

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Using ChipScope with OPB PCIR

6. 7. Click Insert Core to insert the core. Copy the opb_pci_1_wrapper.ngo file to opb_pci_1_wrapper.ngc.

7. 8. In XPS, run Tools → Generate Bitstream and Tools → Download. Do not rerun Tools → Generate Netlist as this overwrites the implementation/opb_pci_1_wrapper.ngc just produced by Inserter. Verify that the filesize of the opb_pci_wrapper.ngc with the inserted core is significantly larger than the original version. Make certain that the opb_pci_1_wrapper.ngc located in the opb_pci_1_wrapper directory is being used rather than the one in the implementation directory.

8. 9. Invoke ChipScope Core Analyzer. Click on the Chain icon located at the top left of Analyzer GUI. Verify that the message in the transcript window indicates that an ICON is found.

9. 10. The ChipScope Analyzer waveform viewer displays signals named DATA*. To reload the waveform viewer with signal names specified in ChipScope Inserter, select File → Import and enter opb_pci.cdc in the dialog box.

10. 10. In the Trigger Setup window, select File → Import opb_write.ctj. Change Windows to N samples to a setting of 500. Arm the trigger by selecting Trigger Setup → Arm, or clicking on the Arm icon.

11. 11. Run XMD or GDB to activate the trigger patterns which cause ChipScope to display meaningful output. For example, invoke XMD, enter rst, and paste the contents of configure.xmd into the XMD window.

Figure 17-2: Making net connections in ChipScope Inserter

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12. 12. ChipScope results can be analyzed in the waveform window, as shown in Figure 17-3. To share the results with colleagues, save the results in the waveform window as a Value Change Dump (vcd) file. The vcd files can translated and viewed in most simulators. The vcd2wlf translator in Modeltech reads a vcd file and generates a wlf file for viewing in the Modeltech waveform viewer. The vcd file can be opened in the Cadence Design System, Inc. Simvision© design tool with File → Open Database.

After running ChipScope, it is sometimes necessary to revise the nets used in trigger operations and data in a debug operation. An efficient method to revise nets used by ChipScope Analyzer uses the following command.

fpga_editor <system>.ncd

From the FPGA Editor GUI, select Tools → ILA.

Select an existing net which isn’t needed in debugging, and click Change Net. The pattern filter box shown in Figure 17-4 facilitates the selection of the new net. Click Write CDC to generate an new opb_pci.cdc file. Click Bitgen to generate a new .bit file.

The FPGA Editor ILA flow is more efficient than re-doing the Chip Inserter flow listed above because the MAP and PAR implementation phases are not required.

Figure 17-3: ChipScope Analyzer Results

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Using ChipScope with OPB PCIR

Figure 17-4: Using FPGA Editor to Revise Nets used in ChipScope Analyzer

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OPB PCI v1.02a User Guide...OPB PCI v1.02a User Guide 5 UG241 July 26, 2006 R Chapter 1 About This...

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