ONCHIP- CAC

8/3/2019 ONCHIP- CAC

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EFFICIENT ON-CHIP CROSSTALKAVOIDANCE

CODEC DESIGN



Interconnect Delay has become a limiting factor for circuit performance in DeepSub-micrometer designs.

The Cross talk in an On-chip bus highly dependent on the data patterns transmittedon the bus.

There are so many Crosstalk avoidance code have been proposed to boost the busspeed and to reduce the overall power consumption.

But among them FPF-CAC advantageous, due to its nonlinear nature.

FPF-CAC = FORBIDDEN PATTERN FREE CROSS TALK AVOIDANCE CODES



The Cross talk Occurs due to

Radiation Effects,

Power Grid Fluctuations,

Interference between metal layers,..etc

Due to this cross talk, it leads to the cause of soft errors in side the chip.

So, that data flowing on the BUS will be corrupted.



SIMPLIFIED ON-CHIP BUS MODEL WITH CROSS TALK



CL Denotes the Load Capacitance,CI Denotes the Inter-wire coupling capacitance

The BUS Structure is Electrically Modeled using aDistributed Resistance- Capacitance (RC) network.

In Deep Submicron Tech, the C I >> CL

The Crosstalk is Dependent on the data transition patterns on the bus.

And These patterns can be classified based on the severity of the cross talk theyimpose on the bus.



The Crosstalk avoidance codes (CAC) can be further classifiedinto two categories. They are,

(i ) Memory Based CAC codes,(ii ) Memory less CAC codes.

The Memory Based Tech. Requires a separate look table for storing the codebook in Encoding as well as Decoding process.* so, occupies more area, fixed bus size & design is simple

where as Memory Less Tech. Doesn t need any table. It performs instantEncoding/ Decoding process.

* Occupies Less Area, Complex Design & less Power.

so, Memory Less Technique is preferable when compared with Memory BasedTechnique.



The Forbidden Patterns are Defined as 3-bit Patterns 101 and 010

A code is known as Forbidden Pattern Free (FPF) if there is no forbidden pattern in

any three consecutive bits.

i) 1101110 [ It is not Forbidden Pattern Free]

ii) 1100110 [ It is known as FPF]

The FPF patterns tabular form for 2, 3 & 4, 5-Bit data Bus s are shown below



FPF- CAC BUS CODEC DESIGN BLOCK DIAGRAM



ENCODING DIAGRAM {MEMORY LESS- CAC}:

INPUTS:A, B,C& D [4-BIT]

ENCODED OUTPUTS {FPF-CAC}:a, b, c, d, e& I [6-Bit]



ADVANTAGES:

Crosstalk preventionScalable ConstructionSystematic (Unencoded wires)

DRAWBACKS:

Encoding/ Decoding Logic OverheadWire Overhead

Errors may Cause due to invalid transitions.



FUTURE WORK:

Generalize for more accurate fault models

Evaluate using realistic simulations

Generalize to include other constraint (e.g.. Power),..etc

ONCHIP- CAC

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