ON LINE TEST GENERATION AND ANALYSIS

R. ŠeinauskasKaunas University of Technology

LITHUANIA

Tools

On line test generation and analysis tools are developed under project REASON

All tools have common frame and are accessible by conventional browser after registration

QUESTION

Why tools on high level of abstraction are necessary?

IntroductionIntroduction

Idea, Algorithm

RTL Description

Gate Level Netlist

Layout

Defect-Based Test Generation

Defects

Conventional Test Generation

Fault model of gates

High-Level Test Generation

Description distortion model

Test Generation for Algorithms

Black-box fault model

Test Generation TasksTest Generation Tasks

Conventional Test Generation

Fault model of gates

High-Level Test Generation

Description distortion model

Test Generation for Algorithms

Black-box fault model

Defect-Based Test Generation

Defects

Test generation for all possible realizations of circuit

description

Test generation for defects

Test generation for all possible realizations of cells

Test generation for all possible descriptions and all possible

realizations of circuit

ASIC Design Flow

In the standard ASIC design flow the designers mainly work on RT- (or higher) level descriptions.

Nowadays logic synthesis tools automatically generate gate-level descriptions.

However, most of the test activities (test structure insertion, test vector generation, fault coverage evaluation, etc,) are still performed on the gate-level netlists.

Time-to-Market

Time-to-Market depends on the duration of the logic and layout synthesis and on the duration of the design for test and test generation.

The design for test and test generation on the system level-level model can reduce time-to-market.

Starting test development at the end of the design process greatly prolongs the time-to-market.

System-level model

If a top-down design methodology is used, then a system-level model of the chip exists early in the design process.

This system-level model can be used during the development of the test program.

Thus, the test engineers can become involved with the project much earlier, and like the block designers, are given a working virtual prototype of the chip in the form of a system–level model.

Time-to-Market

System-level model

RT-level model

Gate-level model

Layout DFT and Test generation

DFT and Test generation

DFT and Test generation

DFT and Test generation

Design complexity

Design complexity drives the need to reuse legacy or IP ( intellectual Property) cores in Systems on a chip ( SoC).

High Level modules of SoC are often specified in terms of their behavior only.

SoC designs rely heavily on reusable and pre-designed cores or intellectual property ( IP) modules, whose gate-level implementation details are unavailable.

Test reuse

Systems designers become system architects reusing more and more proven components and their test processes.

Test reuse must follow the same path. Conventional single–at fault models associated

with internal logical gates or their inter connections are not applicable for test reuse.

Structural defect-based test involves no test reuse, as tests are usually generated after structural synthesis.

Reusable tests

The implementation depends on SoC manufacturing technologies and is permanently changing in SoC lifecycle.

Time-to-Market, reuse legacy or IP cores in Systems on a chip design drives the need to use realization-independent testing.

How core vendors can provide reusable tests for new implementations?

Important questions

Can a test based on functional fault model be effective in uncovering physical defects?

How is its effectiveness dependent on the synthesized structure?

These are important questions, not only for test reuse, but also due to fact that soft cores can be synthesized by different electronic design automation systems, and mapped in different cell libraries and manufacturing technologies.

Design Flow

System-level model

Gate-level model

SynthesisDFT and Test

generation

Time-To-Market

System-level

model

Synthesis

DFT and Test generation

Gate-level model

Test sequences

Test supplement on switch-level

model

Test supplement on

System-level model

Defect coverage analysis

Design Flow

In any case fault coverage analysis on gate level model is necessary, but it is not time consuming task.

The length of test sequences generated on system-level model can be compacted together with the fault coverage analysis. Therefore, the length of test sequences generated on system-level model is not a critical parameter.

On Line Tools

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