On Chip Bus
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Transcript of On Chip Bus
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SOC Consortium Course Material
On Chip BusOn Chip Bus
National Taiwan University
Adopted from National Taiwan University
SOC Course Material
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2SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus (ASB)– Advanced High-performance Bus (AHB)– Advanced Peripheral Bus (APB)
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3SOC Consortium Course Material
Bus Architecture
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4SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus
• High performance• Pipelined operation• Multiple bus master
– Advanced High-performance Bus– Advanced Peripheral Bus
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5SOC Consortium Course Material
Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus
• High performance• Pipelined operation• Multiple bus master• Burst transfers
Advanced Peripheral Bus
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6SOC Consortium Course Material
AHB simple Arch.
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AHB Components
AHB Components– AHB master is able to initiate read and write operations
by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16)
– AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer.
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AHB Components(ii)
AHB Components– AHB arbiter ensures that only one bus master at a time
is allowed to initiate data transfers. – AHB decoder is used to decode the address of each
transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.
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AHB Signals(i)
AHB Signals can be classified as– Clock (HCLK)– Address and read/write data (HADDR, HRDATA,
HWDATA)– Arbitration (HGRANTx, HMASTER, HMASTLOCK,…)– Control signal (HRESETn,…)– Response signal(HREADY, HRESP)
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AHB Signals(ii)
Transfer signals– HCLK
• bus clock. All signal timings are related to the rising edge.
– HADDR[31:0]• 32 bits system bus
– HWDATA/HRDATA [31:0]• 32 bits write/read data bus
– HWRITE• High: write data
• Low: read data
– HREADY• Transfer done
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AHB Signals(ii)Basic Transfer
Each transfer consists of– An address and control cycle– One or more cycles for the data
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12SOC Consortium Course Material
AHB Arch.
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AHB Signals(iii)
Control signals– HTRANS[1:0]
• Current transfer type
– HBURST[2:0]• When sequential transfer, control transfer relation
– HSIZE[2:0]• Control transfer size=2^HSIZE bytes(max=1024bits)
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AHB Signals(iii)-HTRANS
HTRANS[1:0]– IDLE: master don’t need data to be transfer.– BUSY: This transfer type indicates that the bus master is
continuing with a burst of transfers.– NONSEQ: The address and control signals are unrelated
to the previous transfer.– SEQ: the address is related to the previous transfer.
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Burst Operation
AMBA AHB burst operation– 4-beat, 8-beat, 16-beat, single transfer, and undefined-length
transfer.
– Both incrementing and wrapping bursts are supported.
Incrementing burst– Incrementing bursts access sequential locations and the address
of each transfer in the burst is just an increment of the previous address.
Wrapping burst– For wrapping bursts, if the start address of the transfer is not
aligned to the total number of bytes in the burst (size x beats), then the address of the transfer in the burst will wrap when the boundary is reached.
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AHB Signals (iii)-HBURST
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AHB Signals(iii)-HBURST
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AHB Signals(iv)
Response signals– HREADY
• Transfer done, ready for next transfer
– HRESP[1:0]• OKAY transfer complete• ERROR transfer failure(ex: write ROM)• RETRY higher priority master can access bus• SPLIT other master can access bus
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AHB Signals(v)
Arbiter signals– HGRANTx
• Select active bus master
– HMASTER[3:0]• Indicate which bus master is currently performing a transfer
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Master signal
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Arbiter signal
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Slave signal
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Outline
AMBA Bus– Advanced System Bus– Advanced High-performance Bus– Advanced Peripheral Bus
• Low power• Latched address and control• Simple interface• Suitable for many peripherals
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APB state diagram
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APB signals
APB character – Always two cycle transfer– No wait cycle and response signal
APB signals– PCLK Bus clock , rising edge is used to time all
transfers.– PRESETn APB reset 。 active Low.
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APB signals
PADDR[31:0] APB address bus.PSELx Indicates that the slave device is selected.
There is a PSELx signal for each slave.PENABLE Indicates the second cycle of an APB
transfer.PWRITE Transfer direction. High for write access,
Low for read access.PRDATA Read data busPWDATA Write data bus