SSI gates familiarization

INTERPRETATION OF RESULTS

The experiment basically asked the group to familiarize the given Integrated Circuits with their basic logic circuit components within. The group was provided 6 IC’s namely, 74LS00, 74LS02, 74LS04, 74LS08, 74LS32, and 74LS86, as NAND GATE, NOR GATE, HEX INVERTER(NOT GOT), AND GATE, OR GATE, and XOR GATE respectively. The group was instructed on set of procedure to do repeatedly IC by IC.

The VCC pin of each IC, pin 14 as shown in the previous documentation, was connected to the positive terminal of the source with 5 volts and GND pin, pin 7, to the negative terminal. Integrated Circuit input and output conditions were tested using logic probe and results were written down the table provided.

The 74LS00, Quad 2-input NAND Gate, gave “hang” as a result of testing each input pin of the IC, 1-2, 4-5, 9-10, 12-13 pins, and low state “0” to the output pins, 3-6-8-11 pins, (following pins needed to mentioned were visible with the ). The output of zero in this IC theoretically means that the inputs are both high (assumed) because the outputs of all NAND gates are high if any of the inputs are low.

The 74LS02, Quad 2-input NOR Gate, gave “hang” results through its inputs while low state “0” conditions were observed on its output pins. Theoretically speaking, the outputs of all NOR gates are low if any of the inputs are high therefore in the experiment either of the inputs are high (assumed).

The 74LS04, Hex INVERTER, gave “hang” results through its inputs while low state “0” conditions were observed on its output pins. Theoretically speaking, the NOT gate is an electronic circuit that produces an inverted version of the input at its output therefore inputs are in high state (assumed).

The 74LS08, Quad 2-input AND Gate, gave “hang” results through its inputs while high state “1” conditions were observed on its output pins. Theoretically speaking, the AND gate is an electronic circuit that gives a high output “1” only if all its inputs are high therefore all inputs are in high state(assumed).

The 74LS32, Quad 2-input OR Gate, gave “hang” results through its inputs while high state “1” conditions were observed on its output pins. Theoretically speaking, the OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high therefore either of the inputs are in high state(assumed).

The 74LS86, Quad 2-input XOR Gate, gave “hang” results through its inputs while low state “0” conditions were observed on its output pins. Theoretically speaking, the 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high therefore the inputs are either both high or both low state (assumed).

SSI gates familiarization

CONCLUSION

After conducting the experiment, the group might have actually performed it well enough to produce the following results given the objectives mentioned:

The six given SSI IC’s have the same pin for their supply and ground terminals. These are the pin 7 for the ground and pin 14 for the VCC.

The 74LS00, 74LS08, 74LS32, and 74LS86 have the same pin distribution for their input and output terminals. Their pins 1-2, 4-5, 9-10, and12-13 are for the input while 3-6-8-11 pins are for the outputs.

The input terminals of 74LS04 are pins 1-3-5-9-11-13 while the output terminals are pins 2-4-6-8-10-12.

The input terminals of 74LS02 are pins 2-3, 5-6, 8-9, and 11-12 while the output terminals are pins 1-4-10-13.

Every input of SSI IC’s given showed hang result using the logic probe. All SSI IC’s outputs showed low state “0” result except for 74LS08 and 74LS32 which resulted to

high states “1”.