Object Oriented HW/SW System Design with SystemC and OSSS
description
Transcript of Object Oriented HW/SW System Design with SystemC and OSSS
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Object Oriented HW/SW System Designwith SystemC and OSSS
Objective Systems Solutions
Christian Stehno
OFFIS – Institute for Information TechnologyHW/SW Design Methodology GroupOldenburg, Germany
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Outline
Motivation Why do we need improvements towards ESL/HLS
Introduction ESL/HLS SystemC
Design Process Design and Simulation Library OSSS
Features and Advantages Example on Communication exploration
Synthesis tool FOSSY Features and Advantages Example on IP core integration
Conclusion
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Motivation
Embedded Systems are ubiquitous, and so is their design
Today's design techniques have matured over decadesbut without major structural changes
Hence, highly specialized skills are required, costs and time are always too high
Compared to SW engineering advancements, HW design is far behind
But, new technologies and methodologies are arising
Electronic System Level lifts the abstraction level
High Level Synthesis closes the gap from abstraction to realization
SysML, System Verilog, and SystemC make use of SE techniques and provide means for enhanced design processes
New generations of design tools show up
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Introduction
Electronic System Level (ESL) Increase the level of abstraction of the initial models of a system Thereby improve the comprehensibility of the design Introduce new tools and modeling languages HLS, SysML, SystemC, …
High Level Synthesis (HLS) The missing link from models to hardware Automatic transformation from high-level languages into HDL Establish seamless development Distinction based on the performed steps
Behavioral synthesis Algorithmic synthesis
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SystemC
Modeling and simulation class library for system-level design Standardized as IEEE 1666-2005, promoted by the OSCI Historically derived from VHDL with emphasis on RTL Provides structures and hierarchy for system modeling Simulation kernel based on the executable semantics
Concurrency simulated via pseudo parallel delta-cycle semantics Foundations in C++ provide a rich data type pool and strong
expressiveness Communication is method based, using ports, interfaces, channels, and
signals Transaction-Level Modeling (TLM) improves simulation performance
and early explorations on the virtual prototype
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#include "systemc.h"
SC_MODULE(dff){
sc_in<bool> din;sc_in<bool> clock;sc_out<bool> dout;
void doit(){ dout = !din;}
SC_CTOR(dff){ SC_METHOD(doit); sensitive_pos << clock;
}};
SystemC Example
Inverting D FlipFlop example SC_MODULE defines structure,
encapsulates strongly related tasks sc_in and sc_out define ports for
connections into and out of this module Method doit is declared as
SC_METHOD with sensitivity on the clock portHence, on each clock high signal the doit method copies the in-signal to the out-port
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Design flow
The proposed design methodology resembles the typical ESL process:
Functional modeling in SystemC/C++
Refinement towards synthesizability
HLS into HDL Logic synthesis in the
backend System verification is
possible before and after synthesis in SystemC
SystemC/C++ Design
VHDL SystemCXilinxEDK
RTL Synthesis(e.g. Xilinx ISE)
RTL IP
Simulation &Verification
FOSSY
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Design process
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Design process
C++ (golden) model Algorithmic specification Fully functional implementation of the
reactive and/or computational part
Partitioned/refined into
SystemC based virtual system prototype
Partitioned into independent processes and communication links
As much as possible without any link to the actual platform
Abstractions of actual HW yield simulation performance and enable large exploration spaces
Application Layer
C++ Model
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Design process
Exploration and refinement yield Dedicated, yet technology-unaware
architecture Communication-driven optimization
towards final partition and HW/SW interfaces
Timing is refined by explicit clock boundaries
Mapping results in
Platform specific IP cores Pin-accurate communication interfaces Transactor introduction Fully synthesizable, cycle accurate
model
Virtual Target Architecture Layer
Bus
SWProcessor
HWBlock
HWBlock
HWBlock
HWBlock
Target Platform
Bus
µP/µC
RAM
BusIF
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Design process
Synthesis into simplified RTL code Removal of OO Optimization FSM synthesis Signal level interface generation
VHDL code generation for logic synthesis
Optimizations based on chosen platform
Actual IP core instantiation Backend script generation
SystemC code generation for post-synthesis simulation without co-simulation
SynthesizerFOSSY
SystemCVHDL
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Design and Simulation Library OSSS
Object-oriented extension for SystemC, developed at OFFIS Additional primitive blocks for convenience, simulation speed, and optimal synthesis
results FIFOs, RAMs, ROMs
Full C++ data type support including used-defined classes Requires serialization techniques for signal decomposition Provides inheritance, overloading, and polymorphism for increased re-use Templates allow for efficient and concise designs
SW tasks for processor executed processes Very similar to SystemC modules, but certain restrictions OS effects, such as scheduling, can be simulated Timing is abstracted for simulation performance by Estimated Execution Times
and Required ETs on the block level
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Design and Simulation Library OSSS
Shared Objects Very general communication and synchronization element Shared between multiple processes Allow for HW/HW, HW/SW and SW/SW communication Guarded methods for mutual exclusion measures,
e.g. as semaphore or monitor Useable as shared resource or high-level container Method calls can be mapped to arbitrary communication channels
OSSS library and simulator (SystemC) available for free http://www.system-synthesis.org
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Shared Object Example Producer-Consumer
osss_port<put_if<Packet>>
osss_shared<rendezvous_channel<Packet>, osss_round_robin>
osss_port<get_if<Packet>>
template<class ItemType>class put_if : public sc_interface{ public: virtual void put(ItemType item) = 0; virtual bool is_empty() = 0; virtual bool is_full() = 0; ... };
<<implements>> <<implements>>
template<class ItemType>class get_if : public sc_interface{ public: virtual ItemType get() = 0; virtual bool is_empty() = 0; virtual bool is_full() = 0; ... };
ProducerConsumer
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Communication Mapping Alternatives (VTA 1)
Virtual Target Architecture
SoftwareProcessor
ObjectSocket
HardwareBlock
HardwareBlock
Shared BusTopology
Point-to-PointTopology
OPB
ApplicationPort Interface
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Virtual Target Architecture
SoftwareProcessor
ObjectSocket
HardwareBlock
HardwareBlock
Shared BusTopology
OPB
ApplicationPort Interface
Implementation Model Simulation Time [s]
Packet Throughput[Packets/s]
Application Layer 0.2 12 512 512.5VTA 1: OPB & P2P Channel 6.4 1 853 705.6VTA 2: OPB Channel only 5.8 848 413.9
Communication Mapping Alternatives (VTA 2)
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Synthesis Flow
OSSS Flow OPB
XilinxMicroBlaze
ObjectSocket
HardwareBlock
HardwareBlock
Software Partition
Hardware Partition
DDRRAM
OPBIF
OPBArbiter
OPB
OPB DDRController
XilinxMicroBlaze
SynthesisedShared Object
SynthesisedConsumer
SynthesisedConsumer
FOSSY generated
from XilinxIP core library
e.g. Xilinx ML401 FPGA prototyping board
gcc
linker
3rd party tools
Xilinx IP LibXilinx EDK
Board SupportPackage
VHDLVHDLC++C++C++ VHDLdriver libXilinx EDK
project
OSSS Design
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High Level Synthesis
Translation of synthesizable models into target code VHDL for logic synthesis SystemC for post-synthesis simulation
Resolution of object-oriented features Implementation according to the language semantics Strong semantics equivalence
Implicit state machine synthesis Optimization
Loop unrolling Function inlining Code fragment recognition
Predictability and Traceability Synthesized code resembles the high-level model
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High Level Synthesis
HW/SW separation Cross compilation of SW modules SW processor implementation defines deployment Platform description generated for certain backend tools
Communication elements Transactor synthesis for module interfacing Channel synthesis via IP cores or user-defined synthesizable protocols
(Legacy) IP core integration SystemC wrapper for co-simulation Synthesis through replacement by HDL core Also happening for certain OSSS primitives depending on parameters and
platform type chosen
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Video Filter running on Xilinx FPGA prototyping boardIP core generation and integration
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Algorithmic Design
video_source
video_sinkfilter_top
top
chunk_buffer
filter_inner
test.bmp test_out.bmp
filter_golden.cc filter_synth.cc
010151010
H
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Integration into existing architecture
Line FieldDecoder
4:2:2 to 4:4:4Conversion
YCrCb to RGB Conversion
Line Buffer (BRAM)
Line Buffer (BRAM)
Buffer ControlLogic
Video Timing Generation Logic
VideoDAC
HsyncVsyncBlankingPixel Clock
24 Bit RGB Video Data
VideoDecoder
Analog INTERLACED Video Digital
Video
CCIR 601/656YCrCb DataFormat
Composite(YPrPb)
4:4:4 YCrCb
4:2:2 YCrCb
Create the missing Chroma data samples
Color Space Conversion
Video Timing Extraction
4:4:4 RGB
Select the ACTIVE LINE BUFFER for WRITES @ 13.5MHz
Select the ACTIVE LINE BUFFER for READS @ 27MHz
VDEC1 Board XUP-V2Pro Development System
DE-INTERLACE by LINE DOUBLING
filter_top
Analog PROGRESSIVE Video
720 x 480 @ 60Hz
filter_synth.vhd
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The whole design flow
filter.cpp
Xilinx XST,Synopsys Synplify Pro,
etc.
3rd party RTLsynthesis tools
SystemC Testbench
g++
run.xtest.bmp
test_out.bmp
SystemC
Simulation/Test
synthesised_filter.ccsynthesised_filter.vhd
systemc_synth.h
Synthesis
filter.hincludes
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Conclusion
The proposed OSSS design process shows major advantages Strict separation of application, architecture, and platform Flexible communication means Simple IP integration A seamless C++/SystemC design process with end-to-end
simulation, automatic synthesis, all in one IDE Available to all kinds of developers, from SW to HW engineers
The future tasks Broader support for transactor synthesis Enhanced simulation modes More behavioral synthesis elements
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Objective Systems Solutions
FOSSY Live Demo @
www.system-synthesis.org
SystemCC++