Nuvoton Sound Controller Series NSC · 2020. 12. 3. · Nuvoton Sound Controller Series NSC Data...

NSC Data Sheet

Release Date: July 2020

- 1 - Version A1.0

Nuvoton Sound Controller Series

NSC

Data Sheet

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of PowerSpeech® based system design. Nuvoton assumes no

responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

NSC Data Sheet


- 2 - Version A1.0

Table of Contents 1. General Description ......................................................................................................................... 4

2. Features ............................................................................................................................................ 5

3. Block Diagram ................................................................................................................................. 7

4. Pin Configuration ............................................................................................................................ 9

5. Memory Organization .................................................................................................................... 12

6. Special Function Register (SFR) ................................................................................................... 14

7. I/O Port Structure and Operation ................................................................................................... 46

8. Interrupt Controller ........................................................................................................................ 51

9. General Timer ................................................................................................................................ 53

10. Fixed-Frequency (FXF15/FXF13/FXF10) Interrupt Source ......................................................... 58

11. Watchdog Timer (WDT) ............................................................................................................... 59

12. Power Management ....................................................................................................................... 60

13. Low Speed RC (LRC) Oscillator ................................................................................................... 61

14. IR-Wakeup ..................................................................................................................................... 61

15. IR Communication ........................................................................................................................ 62

16. PWM Output Port .......................................................................................................................... 64

17. Serial Peripheral Interface (SPI) Module ....................................................................................... 70

18. Capacitive Touch Sensing ............................................................................................................. 73

19. Low Voltage Reset (LVR) ............................................................................................................. 74

20. Brown-Out Detection (BOD) ........................................................................................................ 74

21. Addressable LED Interface (For NSC768DF/1K0DF) .................................................................. 76

22. UART Interface (For NSC768DF/1K0DF) ................................................................................... 79

23. Mask Option .................................................................................................................................. 83

24. Electrical Characteristics ............................................................................................................... 84

24.1 Absolute Maximum Ratings .............................................................................................. 84

24.2 D.C. Characteristics ........................................................................................................... 84

24.3 A.C. Characteristics ........................................................................................................... 85

24.4 ESD Characteristics ........................................................................................................... 85

NSC Data Sheet


- 3 - Version A1.0

25. Typical Application Circuit ........................................................................................................... 85

26. Package Dimension ....................................................................................................................... 86

27. Revision History ............................................................................................................................ 88

NSC Data Sheet


- 4 - Version A1.0

1. General Description

The NSC is an 8-bit Sound Controller with up to 1M Byte embedded Flash. To program, the Flash

allows to be programmed and read electronically by In-Circuit-Programming (ICP). Once the code is

confirmed, user can lock the code for security.

The NSC has high resolution audio output and advance algorithm to playback single-channel voice with

high-performance sound quality.

The NSC series provides rich peripherals including 384~512 Bytes of SRAM, Up to 12 general purpose

I/O, one 8-bit auto-reload down-counters TimerA, one 12-bit auto-reload down counters TimerG,

Watchdog Timer (WDT), one UART, one SPI, one Addressable LED interface, 3~6 enhanced PWM

output channels, IR carrier, IR detection with IR wake-up and 4~10 Cap Touch input with touch wake-

up function.

The NSC series is equipped with 20MHz internal precise oscillator that is factory trimmed to ±1.5% at

room temperature. The NSC provides additional power monitoring detection such as Power-On Reset,

Low Voltage Reset and 5-level Brown-Out Detection, which stabilizes the power-on/off sequence for a

high reliability system design.

The NSC sound controller operation consumes a very low power with Power-down mode to stop the

whole system clock for minimum power consumption.

The NSC family contains several bodies built-in different size of embedded Flash, shown as below table:

8KHz 12KHz

NSC128DF 94 63 128

NSC192DF 155 103 192

NSC384DF 337 225 384

NSC512DF 458 305 512

NSC768DF 701 467 768

NSC1K0DF 944 629 1024

Duration (Sec)

@NSP Flash

(KByte)

VDD

(V)

PWM

OutputPart No.

LVR

(V)

Audio

Playback

Channel

RAM

(Byte)GPIO Interface

Cap

TouchBOD

Audio

Output

2.0~5.5 1.9 1 Yes

3 pin 4 pin

6 pin 10 pin

13-bit

384

512

12 I/O

SPI

SPI, UART,

Addr. LED

NSC Data Sheet


- 5 - Version A1.0

2. Features

CPU:

8-bit microcontroller.

Operating:

Wide supply voltage from 2.0V to 5.5V.

Wide system frequency up to 20MHz.

Temperature range: -20C ~ 85C

Memory:

Up to 1M Bytes of APROM for user code and contents.

Build-in In-System-Programming.

Code lock for security.

Up to 512 Bytes on-chip RAM.

Clock Sources:

20MHz high-speed internal oscillator trimmed to +/-1.5% @ VDD 5.0V.

System clock source: 20.48MHz, 10.24MHz, 6.83MHz, 5.12MHz.

LRCT 10KHz low-speed internal oscillator.

Peripherals:

Up to 12 general purpose I/O pins.

4 ~ 10 Cap Touch keys with touch wake up @ LRCT enabled.

Internal pull high/low resistor: 1M or 150K (@ 4.5V).

Fixed-Frequency Interrupt source by system clock divided by 32768, 8192 and 1024.

One 8-bit auto-reload down-counters TimerA.

One 12-bit auto-reload down-counters TimerG.

Watchdog Timer (WDT).

Addressable LED interface provides on NSC768DF and NSC1K0DF.

Full-duplex UART port provides on NSC768DF and NSC1K0DF with frame error detection.

One SPI port with master mode.

One output as addressable LED interface provides on NSC768DF and NSC1K0DF.

Up to six channels, 8-bit resolution of Pulse Width Modulation (PWM) output.

Provide IR carrier generation and IR wake up mode @ LRCT enabled.

Power management:

Power-down mode with typical 1uA power consumption.

NSC Data Sheet


- 6 - Version A1.0

Power monitor:

Brown-out detection (BOD) with 5-level selection: 2.1V, 2.4V, 2.7V, 3.0V, 3.3V, and external

level input (only for NSC128DF~512DF).

Power-on reset (POR).

Low voltage reset (LVR).

Audio Output:

13-bit audio resolution.

0.5W @5.0V.

Audio Algorithm:

High compression high quality: 1-bit NSP @SR 8KHz ~ 16KHz.

General compression: 4-bit NM4 @SR 6KHz ~ 32KHz.

Development Tools:

Nuvoton On-Chip-Debugger with CC65 C-compiler Software Development System (SDS).

Nuvoton In-Circuit-Programmer (ICP).

Nuvoton In-System-Programmer (ISP).

Part numbers and package:

Part Number Embedded Flash Package

NSC128DF 128KB TSSOP20




NSC768DF 768KB TSSOP20*

NSC1K0DF 1024KB TSSOP20*

*The TSSOP20 package pin assignment on NSC768DF and NSC1K0DF is different with NSC128DF~NSC512DF.

For detail please reference Package Pin Assignment.

NSC Data Sheet


- 7 - Version A1.0

3. Block Diagram

Figure 1 shows the NSC128DF/192DF/384DF/512DF function block diagram and gives the outline of

the device. User can find all the peripheral functions of the device in the diagram.

8-b

it Inte

rnal B

us

SCK (BP25)

PWM Port3

PWM0~PWM2 (BP0[0:2])

SPI

MOSI (BP27)

CS (BP24)

MISO (BP26)

IR Carrier

Generator

and

Wakeup

Control

IRC (BP14 or BP24)

IRD (BP16 or BP26)

IRP (BP15 or BP25)

PWM Driver

PWM+

VDD_SPK

VSS_SPK

PWM-

TimerG

TimerA

RAM

Flash

/RESET

VDD

VSS

Power-on Reset

and Brown-out

Detection

65C02

Core

WDT

BOD

LVR

(BP01) ICEDATA

(BP00) ICECLKICE Control

BP0

BP15

BP1[3:7]

BP24

BP2[4:7]

Power

Managment

Internal

Oscillator

LRC

10.24 KHz

System Clock

3BP0[0:2]

Figure 1. Block diagram of NSC128DF/192DF/384DF/512DF

NSC Data Sheet


- 8 - Version A1.0

Figure 2 shows the NSC768DF/1K0DF function block diagram and gives the outline of the device. User

can find all the peripheral functions of the device in the diagram.

8-b

it Inte

rnal B

us

SCK (BP03)

SPI

MOSI (BP05)

CS (BP02)

MISO (BP04)

IR Carrier

Generator

and

Wakeup

Control

IRC (BP01)

IRD (BP07)

IRP (BP06)

PWM Driver

PWM+

VDD_SPK

VSS_SPK

PWM-

TimerG

TimerA

RAM

Flash

/RESET

VDD

VSS

Power-on Reset

and Brown-out

Detection

65C02

Core

WDT

BOD

LVR

(BP01) ICEDATA

(BP00) ICECLKICE Control

BP08

BP0[0:7]

BP13

BP1[2:3], BP17

BP21

BP20

Addr. LED SDOUT (BP00 or BP20)

UARTTXD (BP12)

RXD (BP13)

PWM Port6

PWM0~PWM5 (BP0[0:7], BP1[2:3])

Power

Managment

Internal

Oscillator

LRC

10.24 KHz

System Clock

Figure 2. Block diagram of NSC768DF/1K0DF

NSC Data Sheet


- 9 - Version A1.0

4. Pin Configuration

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20PWM2/BODE/BP02

REG

VDD

/RESET

CAP2/IRP/BP15

CAP1/IRC/BP14

CAP0/BP13

PWM0/ICPCLK/BP00

BP24/IRC/CSPWM1/ICPDATA/BP01

VSS

BP17/RTP

PWM-

VSS_SPK

BP16/CAP3/IRD

PWM+

BP25/IRP/SCK

BP26/IRD/MISO

BP27/MOSI

VDD_SPK

NSC128DF

NSC192DF

NSC384DF

NSC512DF

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20PWM4/CAP8/TXD/BP12

VSS_SPK

PWM-

PWM+

VDD_SPK

PWM1/CAP7/IRD/BP07

RTP/BP17

PWM2/CAP2/CS/BP02

REGVDD

PWM3/CAP3/SCK/BP03

BP01/PWM1/CAP1/IRC/ICPDATA

BP05/PWM5/CAP5/MOSI

BP00/PWM0/CAP0/SDOUT/ICPCLK

BP13/PWM5/CAP9/RXD

BP06/PWM0/CAP6/IRP

VSS

/RESET

BP20/SDOUT

BP04/PWM4/CAP4/MISO

NSC768DF

NSC1K0DF

NSC Data Sheet


- 10 - Version A1.0

NSC128DF/192DF/384DF/512DF

Pin Number Symbol Multi-Function Description

3 VDD VDD[2]: Supply voltage for operation.

8 VSS VSS[2]: Ground potential.

15 VDD_SPK VDD_SPK[1]: Supply voltage for speaker driver.

18 VSS_SPK VSS_SPK: Ground potential for speaker driver.

2 REG REG: Internal regulator.

9 BP00/PWM0/ICPCK

BP00: Port 0 bit 0.

PWM0: PWM output channel 0.

ICPCLK[2]: Serial writer clock.

10 BP01/PWM1/ICPDATA

BP01: Port 0 bit 1.


ICPDATA[2]: Serial writer data.

1 BP02/PWM2/BODE

BP02: Port 0 bit 2.


BODE: BOD external input.

7 BP13/CAP0 BP13: Port 1 bit 3.

CAP0: Cap touch 0.

6 BP14/CAP1/IRC

BP14: Port 1 bit 4.

CAP1: Cap touch 1.

IRC: IR carrier output.

5 BP15/CAP2/IRP

BP15: Port 1 bit 5.

CAP2: Cap touch 2.

IRP: IR power control.

19 BP16/CAP3/IRD

BP16: Port 1 bit 6.

CAP3: Cap touch 3.

IRD: IR detect pin.

20 BP17/RTP

BP17: Port 1 bit 7.

RTP: If Capacitive touch sensing current source is enabled, BP17 will

be set to RTP pin and need to connect an external resistor to VSS to set

the charge and recharge current of CAP0 ~ CAP3 in capacitive touch

sensing.

11 BP24/IRC/CS

BP24: Port 2 bit 4.


CS: SPI chip select.

12 BP25/IRP/SCK

BP25: Port 2 bit 5.


SCK: SPI clock.

13 BP26/IRD/MISO

BP26: Port 2 bit 6.

IRD: IR detect pin.

MISO: SPI master input/slave output.

14 BP27/MOSI BP27: Port 2 bit 7.

MOSI: SPI master output/slave input.

16 PWM+ PWM+: PWM driver positive output to drive speaker directly.

17 PWM- PWM-: PWM driver negative output to drive speaker directly.

4 /RESET /RESET[2]: IC reset input, low active.

[1] VDD_SPK can have different voltage power input. VDD_SPK can be floating if PWM+ and PWM- pads unused.

[2] Program pad include BP00 (ICPCLK), BP01 (ICPDATA), /RESET, VDD and VSS.

NSC Data Sheet


- 11 - Version A1.0

NSC768DF/1K0DF


10 VDD VDD[2]: Supply voltage for operation.

12 VSS VSS[2]: Ground potential.

5 VDD_SPK VDD_SPK[1]: Supply voltage for speaker driver.

2 VSS_SPK VSS_SPK: Ground potential for speaker driver.

11 REG REG: Internal regulator.

18 BP00/PWM0/CAP0/SDOUT

/ICPCLK

BP00: Port 0 bit 0.


CAP0: Cap touch 0.

SDOUT: Addressable LED output pin.

ICPCLK[2]: Serial writer clock.

20 BP01/PWM1/CAP1/IRC

/ICPDATA

BP01: Port 0 bit 1.


CAP1: Cap touch 1.


ICPDATA[2]: Serial writer data.

9 BP02/PWM2/CAP2/CS

BP02: Port 0 bit 2.


CAP2: Cap touch 2.

CS: SPI chip select.

8 BP03/PWM3/CAP3/SCK

BP03: Port 0 bit 3.


CAP3: Cap touch 3.

SCK: SPI clock.

15 BP04/PWM4/CAP4/MISO

BP04: Port 0 bit 4.


CAP4: Cap touch 4.

MISO: SPI master input/slave output.

17 BP05/PWM5/CAP5/MOSI

BP05: Port 0 bit 5.


CAP5: Cap touch 5.

MOSI: SPI master output/slave input

16 BP06/PWM0/CAP6/IRP

BP06: Port 0 bit 6.


CAP6: Cap touch 6.


6 BP07/PWM1/CAP7/IRD

BP07: Port 0 bit 7.


CAP7: Cap touch 7.

IRD: IR detect pin.

1 BP12/PWM4/CAP8/TXD

BP12: Port 1 bit 2.


CAP8: Cap touch 8.

TXD: UART transmit data output.

19 BP13/PWM5/CAP9/RXD

BP13: Port 1 bit 3.


CAP9: Cap touch 9.

RXD: UART receive data input.

NSC Data Sheet


- 12 - Version A1.0

NSC768DF/1K0DF


7 BP17/RTP

BP17: Port 1 bit 7.

RTP: If Capacitive touch sensing current source is enabled, BP17 will

be set to RTP pin and need to connect an external resistor to VSS to set

the charge and recharge current of CAP0 ~ CAP9 in capacitive touch

sensing.

14 BP20/SDOUT BP20: Port 2 bit 0.

SDOUT: Addressable LED output pin.

4 PWM+ PWM+: PWM driver positive output to drive speaker directly.

3 PWM- PWM-: PWM driver negative output to drive speaker directly.

13 /RESET /RESET[2]: IC reset input, low active.

[1] VDD_SPK can have different voltage power input. VDD_SPK can be floating if PWM+ and PWM- pads unused.

[2] Program pad include BP00 (ICPCLK), BP01 (ICPDATA), /RESET, VDD and VSS.

5. Memory Organization

Users can access any data in a simple and easy way because the uP has built-in banking mechanism for

accessing data from different memory banks. Memory space allocation and its addressing mapping are as

below table.


Address Size Memory Mapping Comment

00:0000H ~ 00:0017FH 384 Bytes RAM Zero page, Stack

00:0180H ~ 00:0EFFH 3456 Bytes Reserved

00:0F00H ~ 00:0F1FH 32 Bytes DPD RAM Deep power down storage

00:0F20H ~ 00:0F6FH 80 Bytes Reserved

00:0F70H ~ 00:0FFFH 144 Bytes Special Function Registers I/O, Interrupt, Timers,…

00:1000H ~ 00:107FH 128 Bytes Reserved

00:1080H ~ 00:109FH 32 Bytes Interrupt Vector Bank 0

00:10A0H ~ 00: 7FFFH 28512 Bytes User Program & Data Bank 0

01:8000H ~ 01: FFFFH 32768 Bytes User Program & Data Bank 1



Table 5-1. The internal memory mapping table

NSC Data Sheet


- 13 - Version A1.0

NSC768DF/1K0DF

Address Size Memory Mapping Comment

00:0000H ~ 00:001FFH 512 Bytes RAM Zero page, Stack

00:0200H ~ 00:0EFFH 3328 Bytes Reserved

00:0F00H ~ 00:0F1FH 32 Bytes DPD RAM Deep power down storage

00:0F20H ~ 00:0F6FH 80 Bytes Reserved

00:0F70H ~ 00:0FFFH 144 Bytes Special Function Registers I/O, Interrupt, Timers,…

00:1000H ~ 00:107FH 128 Bytes Reserved

00:1080H ~ 00:109FH 32 Bytes Interrupt Vector Bank 0

00:10A0H ~ 00: 7FFFH 28512 Bytes User Program & Data Bank 0




Table 5-2. The internal memory mapping table

NSC Data Sheet


- 14 - Version A1.0

6. Special Function Register (SFR)

The NSC uses Special Function Registers (SFRs) to control and monitor peripherals and their modes.

The SFRs reside in the register locations F70H to FFFH, the SFR memory map is as below table.


Address 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

FF8 - - - - - - - -

FF0 - - - - - - - -

FE8 - - - - - - - -

FE0 - - - - - - - -

FD8 SPIC SPIB SPIBN - - - - -

FD0 - - - - - - - -

FC8 - - - - - - - -

FC0 PWMC - PWM0EN - - PWV00 PWV01 PWV02

FB8 - - - - - - - -

FB0 - - - - - PCMH VOL -

FA8 - TMGC TMGVL TMGVH TMGOL TMGOH - -

FA0 TMAC TMAV TMAO - - - - -

F98 BP0EN BP1EN BP2EN - - IRMF0 - -

F90 IEF0 IEF1 EVF0 EVF1 - - WDTC BODC

F88 BP0M BP1M BP2M - BANK WAKEF - RSTF

F80 BP0R BP1R BP2R - BP0D BP1D BP2D -

F78 - - - - - - - -

F70 - - - - - - - -

Table 6-1. SFR Memory Map

Unoccupied addresses in the SFR space marked in “-“ are reserved for future use. Accessing these areas will have an

indeterminate effect and should be avoided.

NSC Data Sheet


- 15 - Version A1.0

NSC768DF/1K0DF

Address 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

FF8 - - - - - - - -

FF0 - - - - - - - -

FE8 - - - - - - - -

FE0 - - - - - - - -

FD8 SPIC SPIB SPIBN - - - - -

FD0 - - - - - - - -

FC8 PWV3 PWV4 PWV5 - - - - -

FC0 PWMC PWMEN PWMOA PWMOB - PWV0 PWV1 PWV2

FB8 - - - - - - - -

FB0 - - - - - PCMH VOL -

FA8 - TMGC TMGVL TMGVH TMGOL TMGOH - -

FA0 TMAC TMAV TMAO - - - - -

F98 BP0EN BP1EN BP2EN - - - - -

F90 IEF0 IEF1 EVF0 EVF1 - - WDTC BODC

F88 BP0M BP1M BP2M - BANK WAKEF - RSTF

F80 BP0R BP1R BP2R - BP0D BP1D BP2D -

F78 UMODE TXSTS RXSTS BRDIVH BRDIVL URTHD URDATA TDLY

F70 SLDC0 SLDC1 HIDA1 LODA1 HIDA0 LODA0 SDTH SLDAT

Table 6-2. SFR Memory Map

Unoccupied addresses in the SFR space marked in “-“ are reserved for future use. Accessing these areas will have an

indeterminate effect and should be avoided.

NSC Data Sheet


- 16 - Version A1.0


Symbol Definition Address MSB LSB Reset

Value

SPIBN Pseudo register. FDAH SPIBN[7:0] xxxx

xxxxb

SPIB SPI data buffer for

transmit/receiver. FD9H SPIB[7:0]

xxxx

xxxxb

SPIC SPI control register. FD8H SPIC.

7 SPIC[6:5] - - - -

SPIC.

0

0xxx

xxx0b

PWV02 PWM output level width. FC7H PWV02[7:0] xxxx

xxxxb


xxxxb


xxxxb

PWM0E

N

PWM output control

register. FC2H - - - - - PWM0EN[2:0]

xxxx

x000b

PWMC PWM clock source

selection. FC0H - - - - - PWMC[2:0]

xxxx

xxxxb

VOL PWM driver volume

control register. FB6H - - - - - VOL[2:0]

xxxx

x111b

PCMH The PCM data of speaker

PWM. FB5H PCMH[7:0]

xxxx

xxxxb

TMGOH The counting value of

TimerG. FADH - - - - TMGOH[3:0]

xxxx

xxxxb

TMGOL The counting value of

TimerG. FACH TMGOL[7:0]

xxxx

xxxxb

TMGVH TimerG value. FABH - - - - TMGVH[3:0] xxxx

xxxxb

TMGVL TimerG value. FAAH TMGVL[7:0] xxxx

xxxxb

TMGC TimerG control register. FA9H - - - - TMGC[3:1] TMG

C.0

xxxx

xxx0b

TMAO The counting value of

TimerA. FA2H TMAO[7:0]

xxxx

xxxxb

TMAV TimerA value. FA1H TMAV[7:0] xxxx

xxxxb

TMAC TimerA control register. FA0H TMA

C.7 - - - TMAC[3:1]

TMA

C.0

0xxx

xxx0b

IRMF0 IR alternative function

register. F9DH - - - - - -

IRMF

0.1

IRMF

0.0

xxxx

xx00b

BP2EN Port 2 interrupt control

register. F9AH BP2EN[7:4] - - - -

0000

xxxxb


register. F99H BP1EN[7:3] - - -

0000

0xxxb


register. F98H - - - - - BP0EN[2:0]

xxxx

x000b

BODC BOD control register. F97H BOD

C.7 - - - BODC[3:1]

BOD

C.0

xxxx

xxxxb

WDTC WDT control register. F96H - - - - - - - WDT

C.0

0xxx

xxx0b

EVF1 Interrupt event register 1. F93H - - - - EVF - - - xxxx

NSC Data Sheet


- 17 - Version A1.0

1.3 xxxxb

EVF0 Interrupt event register 0. F92H EVF0.

7

EVF0.

6

EVF

0.5

EVF

0.4 - -

EVF0

.1

EVF0

.0

0000

xx00b

IEF1 Interrupt enable register 1. F91H - - - - IEF

1.3 - - -

xxxx

0xxxb

IEF0 Interrupt enable register 0. F90H IEF0.

7

IEF0.

6

IEF

0.5

IEF

0.4 - -

IEF0.

1

IEF0.

0

0000

xx00b

RSTF Chip reset source register. F8FH - - - - - - RSTF

.1

RSTF

.0

xxxx

xx00b

WAKEF Chip wakeup and reset

source register. F8DH

WAK

EF.7 -

WA

KEF

.5

WA

KEF

.4

WA

KEF

.3

WA

KEF

.2

WAK

EF.1

WAK

EF.0

0x00

0000b

BANK Bank register. F8CH - - - - - - - Bank.

0

0000

0001b

BP2M Port 2 mode control

register. F8AH BP2M[7:4] - - - -

0000

xxxxb


register. F89A BP1M[7:3] - - -

0000

0xxxb


register. F88A - - - - - BP0M[2:0]

xxxx

x000b

BP2D Port 2 input/output control

register. F86H BP2D[7:4] - - - -

1111

xxxxb


register. F85H BP1D[7:3] -- - -

1111

xxxxb


register. F84H - - - - - BP0D[2:0]

xxxx

x111b

BP2R Bi-directional port 2 data

register. F82H BP2R[7:4] - - - -

xxxx

xxxxb


register. F81H BP1R[7:3] - - -

xxxx

xxxxb


register. F80H - - - - - BP0R[2:0]

xxxx

xxxxb

Table 6-3. SFR Definitions and Reset Values

NSC Data Sheet


- 18 - Version A1.0

NSC768DF/1K0DF


Value

SPIBN Pseudo register. FDAH SPIBN[7:0] xxxx

xxxxb

SPIB SPI data buffer for

transmit/receiver. FD9H SPIB[7:0]

xxxx

xxxxb

SPIC SPI control register. FD8H SPIC.7 SPIC[6:5] - - - SPIC.

1

SPIC.

0

0xxx

xx00b

PWV5 PWM output level

width. FCAH PWV5[7:0]

xxxx

xxxxb


width. FC9H PWV5[7:0]

xxxx

xxxxb



xxxx

xxxxb



xxxx

xxxxb



xxxx

xxxxb



xxxx

xxxxb

PWMOB PWM output control

register. FC3H - - - - PWMOB[3:2] PWMOB[1:0]

xxxx

0000b

PWMOA PWM output control

register. FC2H PWMOA[7:6] PWMOA[5:4] PWMOA[3:2] PWMOA[1:0]

0000

0000b

PWMEN PWM enable control

register. FC1H - - PWMEN[5:0]

xx00

0000b

PWMC PWM clock source

selection. FC0H - - - - - PWMC[2:0]

xxxx

xxxxb

VOL PWM driver volume

control register. FB6H - - - - - VOL[2:0]

xxxx

x111b

PCMH The PCM data of

speaker PWM. FB5H PCMH[7:0]

xxxx

xxxxb

TMGOH The counting value of

TimerG. FADH - - - - TMGOH[3:0]

xxxx

xxxxb

TMGOL The counting value of

TimerG. FACH TMGOL[7:0]

xxxx

xxxxb

TMGVH TimerG value. FABH - - - - TMGVH[3:0] xxxx

xxxxb

TMGVL TimerG value. FAAH TMGVL[7:0] xxxx

xxxxb

TMGC TimerG control

register. FA9H - - - - TMGC[3:1]

TMG

C.0

xxxx

xxx0b

TMAO The counting value of

TimerA FA2H TMAO[7:0]

xxxx

xxxxb

TMAV TimerA value. FA1H TMAV[7:0] xxxx

xxxxb

TMAC TimerA control

register. FA0H

TMAC

.7

TMA

C.6 TMAC[5:4] TMAC[3:1]

TMA

C.0

00xx

xxx0b


register. F9AH - - - - - - -

BP2E

N.0

xxxx

xxx0b

BP1EN Port 1 interrupt control F99H BP1EN - - - BP1EN[3:2] - - 0xxx

NSC Data Sheet


- 19 - Version A1.0

register. .7 00xxb


register. F98H BP0EN[7:0]

0000

0000b

BODC BOD control register. F97H BODC.

7 - - - BODC[3:1]

BOD

C.0

0xxx

xxx0b

WDTC WDT control register. F96H - - - - - - - WDT

C.0

xxxx

xxxxb

EVF1 Interrupt event register

1. F93H -

EVF1

.6

EVF1

.5

EVF1

.4

EVF1

.3 - -

EVF1

.0

x000

0xx0b

EVF0 Interrupt event register

0. F92H

EVF0.

7

EVF0

.6

EVF0

.5

EVF0

.4 - -

EVF0

.1

EVF0

.0

0000

xx00b

IEF1 Interrupt enable

register 1. F91H -

IEF1.

6

IEF1.

5

IEF1.

4

IEF1.

3 - -

IEF1.

0

x000

0xx0

IEF0 Interrupt enable

register 0. F90H IEF0.7

IEF0.

6

IEF0.

5

IEF0.

4 - -

IEF0,

1

IEF0.

0

0000

xx00b

RSTF Chip reset source

register. F8FH - - - - - -

RSTF

.1

RSTF

.0

xxxx

xx00b

WAKEF Chip wakeup and reset

source register. F8DH

WAKE

F.7 -

WAK

EF.5

WAK

EF.4

WAK

EF.3

WAK

EF.2

WAK

EF.1

WAK

EF.0

0x00

0000b

BANK Bank register. F8CH - - - - - - - Bank.

0 0000

0001b


register. F8AH - - - - - - -

BP2

M.0 xxxx

xxx0b


register. F89A

BP1M.

7 - - - BP1M[3:2] - -

0xxx

00xxb


register. F88H BP0M[7:0]

0000

0000b

BP2D Port 2 input/output

control register. F86H - - - - - - -

BP2D

.0 xxxx

xxx1b

NSC Data Sheet


- 20 - Version A1.0

NSC768DF/1K0DF


Value


control register. F85H BP1D.7 - - - BP1D[3:2] - -

1xxx

11xxb


control register. F84H BP0D[7:0]

1111

1111b

BP2R Bi-directional port 2

data register. F82H - - - - - - -

BP2R

.0

xxxx

xxxxb


data register. F81H BP1R.7 - - - BP1R[3:2] - -

xxxx

xxxxb


data register. F80H BP0R[7:0]

xxxx

xxxxb

TDLY The transfer delay

time. F7FH - - - - TDLY[3:0]

xxxx

0000b

URDATA Data transfer

register. F7EH URDATA[7:0]

xxxx

xxxxb

URTHD FIFO threshold to

trigger interrupt. F7DH URTHD[7:4] URTHD[3:0]

1111

0000b

BRDIVL UART baud rate

divider register. F7CH BRDIVL[7:0]

xxxx

xxxxb

BRDIVH UART baud rate

divider register. F7BH - - - - - - -

BRDI

VH.0

xxxx

xxxxb

RXSTS

UART receiver

control and status

register.

F7AH RXSTS.

7

RXS

TS.6

RXS

TS.5

RXS

TS.4

RXS

TS.3

RXS

TS.2

RXS

TS.1

RXS

TS.0

10xx

xx0xb

TXSTS

UART transmitter

control and status

register.

F79H TXSTS.

7

TXS

TS.6 - - - -

TXST

S.1

TXST

S.0

10xx

xx0xb

UMODE UART control

register. F78H

UMOD

E.7

UM

ODE

.6

UMO

DE.5

UMO

DE.4 UMODE[3:1]

UMO

DE.0

0000

0000b

SLDAT

Pushes data onto the

FIFO and increments

the write point.

F77H SLDAT[7:0] xxxx

xxxxb

SDTH FIFO threshold. F76H - - - SDTH[4:0] xxxx

xxxxb

LOAD0 Low level period of

data bit “0”. F75H LOAD0[7:0]

xxxx

xxxxb

HIDA0 High level period of

data bit “0”. F74H HIDA0[7:0]

xxxx

xxxxb

LODA1 Low level period of

data bit “1”. F73H LOAD1[7:0]

xxxx

xxxxb

HIDA1 High level period of

data bit “1”. F72H HIDA1[7:0]

xxxx

xxxxb

SLDC1 Addressable LED

control register. F71H - - - - - -

SLD

C1.1

SLD

C1.0

xxxx

xx01b

SLDC0 Addressable LED

control register. F70H

SLDC0.

7

SLD

C0.6

SLD

C0.5 - -

SLD

C0.2 -

SLD

C0.0

100x

x0x0b

Table 6-4. SFR Definitions and Reset Values

NSC Data Sheet


- 21 - Version A1.0

Following list all SFR description. For each SFR define also list in function chapter.

SLDC0 – Addressable LED Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

SLDC0.7 SLDC0.6 SLDC0.5 - - SLDC0.2 - SLDC0.0

R R W - - R/W - R/W

Address: F70H Reset value: 100x x0x0b

Name Bit Description

SLDC0

7

FIFO empty flag.

0: FIFO in not empty.

1: FIFO is empty.

6

FIFO full flag.

0: FIFO is not full.

1: FIFO is full, 32 bytes FIFO all are filled with data.

5

Reset FIFO.

0: No operation.

1: Write 1 to this bit to reset FIFO, SLDC0.6 will be set as “0”, SLDC0.7

will be set as “1”.


SLDC0

2

Data output control.

0: Stop data output. SDOUT keep in idle output. EFV1.0 is cleared.

1: Start data output from FIFO and continue output until FIFO is empty or

SLDC0.1 is written 0. If FIFO is empty, SDOUT keep in idle output.

When FIFO is empty, user needs to decide to clear SLDC0.2 or not.

0

Enable 1-wire addressable LED controller.

0: Disable.

1: Enable. BP00 or BP20 is the shared function output pin SDOUT, keep

the level as BP0R.0 or BP2R.0 in idle state. In general, set BP0R.0 or

BP2R.0 as “0”.

SLDC1 – Addressable LED Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - - - - - SLDC1.1 SLDC1.0

- - - - - - R/W R/W

Address: F71H Reset value: xxxx xx01b


SLDC1

1

Defines 1-wire addressable LED output pin when SLDC0.0 = 1.

0: BP00 is the shared function output pin SDOUT.


0

Addressable LED data transmission method when addressable LED is

enabled.

0: Low bit data sent at first.

1: High bit data sent at first.

NSC Data Sheet


- 22 - Version A1.0

HIDA1 – High Level Period of Data Bit “1” (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

HIDA1[7:0]

R/W

Address: F72H Reset value: xxxx xxxxb


HIDA1 7:0 This register is used only in 1-wire mode.

High level period is HIDA1[7:0] * 0.05s.

LODA1 – Low Level Period of Data Bit “1” (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

LODA1[7:0]

R/W



LOAD1 7:0 This register is used only in 1-wire mode.

Low level period is LODA1[7:0] * 0.05s.

HIDA0 – High Level Period of Data Bit “0” (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

HIDA0[7:0]

R/W





LODA0 – Low Level Period of Data Bit “0” (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

LODA0[7:0]

R/W



LODA0 7:0 This register is used only in 1-wire mode.


NSC Data Sheet


- 23 - Version A1.0

SDTH – FIFO Threshold (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - - SDTH[4:0]

- - - R/W



SDTH 4:0

If SLDC0.0 is 1 and the valid data count of the FIFO buffer is less than or

equal to SDTH[4:0] threshold, the EVF1.0 bit will set to 1, else the EVF1.0

bit will be cleared to 0. If IEF1.0 is 1, EVF1.0=1 will generate an interrupt.

SLDAT – Pushes Data onto The FIFO and Increments The Write Point (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

SLDAT[7:0]

W



SLDAT 7:0 A write to this register pushes data onto the FIFO and increments the write

point.

UMODE – UART Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

UMODE.7 UMODE.6 UMODE.5 UMODE.4 UMODE[3:1] UMODE.0

R/W R/W R/W R/W R/W R/W

Address: F78H Reset value: 0000 0000b


UMODE 7

Enable UART TXD module.

0: TXD disable.

1: TXD enable. User must also set TXSTS.1 as 0.


UMODE

6

Enable UART RXD module.

0: RXD disable.

1: RXD enable. User must also set RXSTS.1 as 0.

5

Enable UART transmitter.

0: Disable.

1: Enable.

4

Enable UART receiver.

0: Disable.

1: Enable.

3:1

UART mode selection.

If UMODE[3:2] is 00, no parity, UMODE.1 don’t care.

Data format is (Start, D0, D1, D2, D3, D4, D5, D6, D7, Stop).

If UMODE[3:2] is not 00, with parity bit.

Data format is (Start, D0, D1, D2, D3, D4, D5, D6, D7, Parity, Stop).

UMODE[3:1] define parity bit.

010: Ignore data whose parity is 1 if receiver.

(stick 0 parity if transmitter)


NSC Data Sheet


- 24 - Version A1.0


100: Even parity.

101: Odd parity.

110: Stick 0 parity.


0 0: No operation.

1: Force TXD to 0 (force break).

TXSTS – UART Transmitter Control and Status Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

TXSTS.7 TXSTS.6 - - - - TXSTS.1 TXSTS.0

R R - - - - R/W W

Address: F79H Reset value: 10xx xx0xb


TXSTS

7

FIFO empty. Set/cleared by H/W.

0: Transmitter FIFO is not empty.

1: Transmitter FIFO is empty.

6

FIFO full. Set/cleared by H/W.

0: Transmitter FIFO is not full.

1: Transmitter FIFO is full.

1 When UART TX is enabled (UMODE.7 = 1), this bit must be set as 0.

0

Transmitter reset.

0: No operation.

1: Write 1 to this bit, all the byte in the transmit FIFO/transmit buffer and

TX internal state machine are cleared.

RXSTS – UART Receiver Control and Status Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

RXSTS.7 RXSTS.6 RXSTS.5 RXSTS.4 RXSTS.3 RXSTS.2 RXSTS.1 RXSTS.0

R R R/W R/W R/W R/W R/W W

Address: F7AH Reset value: 10xx xx0xb

Bit Name Description

RXSTS

7


0: Receiver FIFO is not empty.

1: Receiver FIFO is empty.

6


0: Receiver FIFO is not full.

1: Receiver FIFO is full.

5

Frame error. Set by H/W, cleared by F/W write 1.

0: No frame error.

1: Frame error (the receiver character has no valid stop bit).

If any bit of RXSTS[5:2] is set 1 by H/W, EVF1.6 will be set to 1. If

IEF1.6 is 1, EVF1.6 = 1 will generate an interrupt.

4

Parity error. Set by H/W, cleared by F/W write 1.

0: No parity error.

1: Parity error.

3

Break. Set by H/W, cleared by F/W write 1.

0: No break in.

1: The receiver character is “data bit = 0”, “parity bit = 0” and “no stop bit

NSC Data Sheet


- 25 - Version A1.0

(stop bit = 0)”.

2

Overrun. Set by H/W, clear by F/W write 1.

0: Receiver FIFO is not overflow.

1: Receiver FIFO is overflow.

1 When UART RX is enabled (UMODE.6 = 1), this bit must be set as 0

0

Receiver reset.

0: No operation.

1: Write 1 to this bit, all the byte in the receive FIFO/receive buffer and RX

internal state machine are cleared.

BRDIVH – UART Baud Rate Divider Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - - - - - - BRDIVH.0

- - - - - - - R/W

Address: F7BH Reset value: xxxx xxxxb


BRDIVH 0 The baud rate divider is controlled by BRDVIH.0 and BRDIVL[7:0].

BRDIVL – UART Baud Rate Divider Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BRDIVL[7:0]

R/W

Address: F7CH Reset value: xxxx xxxxb


BRDIVL 7:0 The baud rate divider is controlled by BRDVIH.0 and BRDIVL[7:0].

URTHD – FIFO Threshold to Trigger Interrupt (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

URTHD[7:4] URTHD[3:0]

R/W R/W

Address: F7DH Reset value: 1111 0000b


URTHD

7:4

Defines receiver FIFO threshold to trigger interrupt.

If the valid data count of Rx FIFO buffer is more than or equal to URTHD

[7:4] threshold, EVF1.5 bit will set to 1, else the EVF1.5 bit will be cleared

to 0. If IEF1.5 is 1, EVF1.5 = 1 will generate an interrupt.

3:0

Defines transmitter FIFO threshold to trigger interrupt.

If the valid data count of TX FIFO buffer is less than or equal to URTHD



NSC Data Sheet


- 26 - Version A1.0

URDATA – Data Transfer Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

URDATA[7:0]

R/W

Address: F7EH Reset value: xxxx xxxxb


URDATA 7:0

By writing one byte to this register, the data byte will be stored in UART

transmitter FIFO.

By reading this register, one data byte will returned from UART receiver

FIFO.

TDLY – The Transfer Delay Time (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - - - TDLY[3:0]

- - - - R/W

Address: F7FH Reset value: xxxx 0000b


TDLY 3:0 Defines the transfer delay time between the last Stop bit and next Start bit

in transmission. The unit is baud.

BP0R - Bi-Directional Port 0 Data Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - BP0R.2 BP0R.1 BP0R.0

- - - - - R/W R/W R/W



BP0R 2:0 Bi-directional (input/output) port 0 data register.

BP0R - Bi-Directional Port 0 Data Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BP0R.7 BP0R.6 BP0R.5 BP0R.4 BP0R.3 BP0R.2 BP0R.1 BP0R.0

R/W R/W R/W R/W R/W R/W R/W R/W




BP1R – Bi-Directional Port 1 Data Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

BP1R.7 BP1R.6 BP1R.5 BP1R.4 BP1R.3 - - -

R/W R/W R/W R/W R/W - - -




NSC Data Sheet


- 27 - Version A1.0

BP1R – Bi-Directional Port 1 Data Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BP1R.7 - - - BP1R.3 BP1R.2 - -

R/W - - - R/W R/W - -



BP1R 7

Bi-directional (input/output) port 1 data register. 3:2


7 6 5 4 3 2 1 0

BP2R.7 BP2R.6 BP2R.5 BP2R.4 - - - -

R/W R/W R/W R/W - - - -





7 6 5 4 3 2 1 0

- - - - - - - BP2R.0

- - - - - - - R/W



BP2R 0 Bi-directional (input/output) port 2 data register.

BP0D – Port 0 Input/Output Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - BP0D.2 BP0D.1 BP0D.0

- - - - - R/W R/W R/W

Address: F84H Reset value: xxxx x111b


BP0D 2:0 0: BP0n is output pin.

1: BP0n is input pin.

BP0D – Port 0 Input/Output Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BP0D.7 BP0D.6 BP0D.5 BP0D.4 BP0D.3 BP0D.2 BP0D.1 BP0D.0






NSC Data Sheet


- 28 - Version A1.0


7 6 5 4 3 2 1 0

BP1D.7 BP1D.6 BP1D.5 BP1D.4 BP1D.3 - - -


Address: F85H Reset value: 1111 1xxxb





7 6 5 4 3 2 1 0

BP1D.7 - - - BP1D.3 BP1D.2 - -

R/W - - - R/W R/W - -

Address: F85H Reset value: 1xxx 11xxb


BP1D 7 0: BP1n is output pin.

1: BP1n is input pin. 3:2


7 6 5 4 3 2 1 0

BP2D.7 BP2D.6 BP2D.5 BP2D.4 - - - -

R/W R/W R/W R/W - - - -

Address: F86H Reset value: 1111 xxxxb





7 6 5 4 3 2 1 0

- - - - - - - BP2D.0

- - - - - - - R/W

Address: F86H Reset value: xxxx xxx1b




NSC Data Sheet


- 29 - Version A1.0

BP0M – Port 0 Mode Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - BP0M.2 BP0M.1 BP0M.0

- - - - - R/W R/W R/W



BP0M 2:0

For BP0D.n = 0 (output pin):

BP0M.n

0: BP0n open-drain type output.

1: BP0n CMOS type output.

For BP0D.n = 1 (input pin):

BP0M.n

0: BP0n floating input.

1: BP0n pulled high or low by internal 150KΩ or 1MΩ. (by mask option)

BP0M – Port 0 Mode Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BP0M.7 BP0M.6 BP0M.5 BP0M.4 BP0M.3 BP0M.2 BP0M.1 BP0M.0




BP0M 7:0


BP0M.n




BP0M.n




7 6 5 4 3 2 1 0

BP1M.7 BP1M.6 BP1M.5 BP1M.4 BP1M.3 - - -




BP1M 7:3


BP1M.n




BP1M.n



NSC Data Sheet


- 30 - Version A1.0


7 6 5 4 3 2 1 0

BP1M.7 - - - BP1M.3 BP1M.2 - -

R/W - - - R/W R/W - -



BP1M

7


BP1M.n




BP1M.n



3:2


7 6 5 4 3 2 1 0

BP2M.7 BP2M.6 BP2M.5 BP2M.4 - - - -

R/W R/W R/W R/W - - - -

Address: F8AH Reset value: 0000 xxxxb


BP2M 7:4


BP2M.n




BP2M.n




7 6 5 4 3 2 1 0

- - - - - - - BP2M.0

- - - - - - - R/W

Address: F8AH Reset value: xxxx xxx0b


BP2M 0


BP2M.n




BP2M.n



NSC Data Sheet


- 31 - Version A1.0

BANK – Bank Register

7 6 5 4 3 2 1 0

- - - - - - - BANK.0

- - - - - - - R/W

Address: F8CH Reset value: 0000 0001b


BANK 0 For extending memory space.

WAKEF – Chip Wakeup and Reset Source Register

When chip releases from STOP mode, the corresponding bit will be set to reflect the reason

of wakeup reset. This register is designed to be cleared by user. Writing action will clear all

bits.

7 6 5 4 3 2 1 0

WAKEF.7 - WAKEF.5 WAKEF.4 WAKEF.3 WAKEF.2 WAKEF.1 WAKEF.0

R/W - R/W R/W R/W R/W R/W R/W

Address: F8DH Reset value: 0x00 0000b


WAKEF

7

Identify chip reset is from normal mode or STOP mode.

0: normal mode. F/W needs to check WAKEF.3, WAKEF.4, WAKEF.5 and

RSTF register to know the reset source.

1: STOP mode. F/W needs to check WAKEF.0, WAKEF.1, WAKEF.2 and

WAKEF.3 to know the wakeup reset source.

5 POR

4 LVR

3 RESET pin.

2 IR-Wakeup input condition matched.

1 LRCT time out.

0 Port input trigger.

RSTF – Chip Reset Source Register

When chip resets, the corresponding bit will be set to reflect the reason of reset.

This register is designed to be cleared by user. Writing “1” will clear the corresponding bit.

7 6 5 4 3 2 1 0

- - - - - - RSTF.1 RSTF.0

- - - - - - R/W R/W

Address: F8FH Reset value: xxxx xx00b


RSTF 1 WDT timeout.

0 No wake source and forces chip to STOP mode.

NSC Data Sheet


- 32 - Version A1.0

IEF0 – Interrupt Enable Register 0

0: Disable interrupt.

1: Enable interrupt.

7 6 5 4 3 2 1 0

IEF0.7 IEF0.6 IEF0.5 IEF0.4 - - IEF0.0 IEF0.0

R/W R/W R/W R/W - - R/W R/W

Address: F90H Reset value: 0000 xx00b


IEF0

7 FXF15 INT enable/disable.



4 TimerG INT enable/disable.


IEF0 1 TimerA INT enable/disable.

0 PORT INT enable/disable.

IEF1 – Interrupt Enable Register 1 (For NSC128DF/192DF/384DF/512DF)



7 6 5 4 3 2 1 0

- - - - IEF1.3 - - -

- - - - R/W - - -

Address: F91H Reset value: xxxx 0xxxb


IEF1 3 LRCT INT enable/disable.

IEF1 – Interrupt Enable Register 1 (For NSC768DF/1K0DF)



7 6 5 4 3 2 1 0

- IEF1.6 IEF1.5 IEF1.4 IEF1.3 - - IEF1.0

- R/W R/W R/W R/W - - R/W

Address: F91H Reset value: x000 0xx0b


IEF1

6 UART RX LN (line status) INT enable/disable.

5 UART RX INT enable/disable.

4 UART TX INT enable/disable.

3 LRCT INT enable/disable.

0 Addressable LED INT enable/disable.

NSC Data Sheet


- 33 - Version A1.0

EFV0 – Interrupt Event Register 0

0: Non-queuing.

1: Queuing.

Write “1” to bit EVF0.n will clear bit EVF0.n.

7 6 5 4 3 2 1 0

EVF0.7 EVF0.6 EVF0.5 EVF0.4 - - EVF0.1 EVF0.2




EVF0

7 FXF15 INT queuing/non-queuing.



4 TimerG INT queuing/non-queuing.

1 TimerA INT queuing/non-queuing.

0 PORT INT queuing/non-queuing.

EFV1 – Interrupt Event Register 1 (For NSC128DF/192DF/384DF/512DF)

0: Non-queuing.

1: Queuing.


7 6 5 4 3 2 1 0

- - - - EVF1.3 - - -

- - - - R/W - - -



EVF1 3 LRCT INT queuing/non-queuing.

EFV1 – Interrupt Event Register 1 (For NSC768DF/1K0DF)

0: Non-queuing.

1: Queuing.


7 6 5 4 3 2 1 0

- EVF1.6 EVF1.5 EVF1.4 EVF1.3 - - EVF1.0

- R/W R R R/W - - R



EVF1

6 UART RX LN (line status) flag. It is set or cleared by H/W according to bits

RXSTS[5:2].

5 UART RX FIFO event flag.

4 UART TX FIFO event flag.

3 LRCT INT queuing/non-queuing.

0 Addressable LED FIFO event flag.

NSC Data Sheet


- 34 - Version A1.0

WDTC – WDT Control Register

7 6 5 4 3 2 1 0

- - - - - - - WDTC.0

- - - - - - - R/W



WDTC 0 Write “1” to WDTC.0 register will clear the WDT.

BODC – BOD Control Register (For NSC128DF/192DF/384DF/512DF)

If BODC.0=1 and BODC[3:1]=101~111, BP02 is configured as BOD external input pin

automatically. But user needs to set BP02 as input floating.

7 6 5 4 3 2 1 0

BODC.7 - - - BODC[3:1] BODC.0

R - - - R/W R/W

Address: F97H Reset value: 0xxx xxx0b


BODC 7 0: BOD detect input voltage is not below BOD level.

1: BOD detect input voltage is below BOD level.


BODC

3:1

000: BOD level is 2.1V.





101~111: BOD level is external reference voltage.

0 0: Disable BOD.

1: Enable BOD.

BODC – BOD Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0


R - - - R/W R/W



BODC

7 0: BOD detect input voltage is not below BOD level.


3:1






101~111: Reserved.

0 0: Disable BOD.

1: Enable BOD.

NSC Data Sheet


- 35 - Version A1.0

BP0EN – Port 0 Interrupt Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - BP0EN.2 BP0EN.1 BP0EN.0

- - - - - R/W R/W R/W



BP0EN 2:0

0: Falling/rising edge on BP0n will NOT trigger PORT interrupt.

1: Falling/rising edge on BP0n can trigger PORT interrupt.

BP0EN.n is useful only when BP0D.n is “1”.

BP0EN – Port 0 Interrupt Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BP0EN.7 BP0EN.6 BP0EN.5 BP0EN.4 BP0EN.3 BP0EN.2 BP0EN.1 BP0EN.0




BP0EN 7:0



BP0EN.n is useful only whenBP0D.n is “1”.


7 6 5 4 3 2 1 0

BP1EN.7 BP1EN.6 BP1EN.5 BP1EN.4 BP1EN.3 - - -




BP1EN 7:3





7 6 5 4 3 2 1 0

BP1EN.7 - - - BP1EN.3 BP1EN.2 - -

R/W - - - R/W R/W - -



BP1EN 7 0: Falling/rising edge on BP1n will NOT trigger PORT interrupt.


BP1EN.n is useful only when BP1D.n is “1”. 3:2

NSC Data Sheet


- 36 - Version A1.0


7 6 5 4 3 2 1 0

BP2EN.7 BP2EN.6 BP2EN.5 BP2EN.4 - - - -

R/W R/W R/W R/W - - - -



BP2EN 7:4





7 6 5 4 3 2 1 0

- - - - - - - BP2EN.0

- - - - - - - R/W



BP2EN 0




IRMF0 – IR Alternative Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - - IRMF0.1 IRMF0.0

- - - - - - R/W R/W

Address: F9DH Reset value: xxxx xx00b


IRMF0

1 0: BP14 is shared as IR carrier output pin.

1: BP24 is shared as IR carrier output pin.

0 0: BP15 ~ BP16 are shared as IR wakeup pins.

1: BP25 ~ BP26 are shared as IR wakeup pins.

NSC Data Sheet


- 37 - Version A1.0

TMAC – TimerA Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

TMAC.7 - - - TMAC[3:1] TMAC.0

R/W - - - R/W R/W

Address: FA0H Reset value: 0xxx xxx0b


TMAC

7

Defines IR carrier output enable/disable.

0: Disable IR carrier output.

1: Enable IR carrier output.

3:1

000 or 11x: clock = Fsys/2.

001: clock = Fsys/4.




101: clock = Fsys/8192.

0 0: Disable the clock input of the TimerA counter.

1: Enable the clock input.

TMAC – TimerA Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

TMAC.7 TMAC.6 - - TMAC[3:1] TMAC.0

R/W R/W - - R/W R/W

Address: FA0H Reset value: 00xx xxx0b


TMAC

7




6 When IR carrier output is enabled (TMAC.7 = 1), this bit must be set as 0.

3:1






101: clock = Fsys/8192.



TMAV – TimerA Value

7 6 5 4 3 2 1 0

TMAV.7

R/W

Address: FA1H Reset value: xxxx xxxxb


TMAV 7:0 This register holds the reload-value of TimerA.

NSC Data Sheet


- 38 - Version A1.0

TMAO – The Counting Value of TimerA

7 6 5 4 3 2 1 0

TMAO.7

R/W



TMAO 7:0 The counting value of TimerA can be read out via this register.

TMGC – TimerG Control Register

7 6 5 4 3 2 1 0

- - - - TMGC[3:1] TMGC.0

- - - - R/W R/W

Address: FA9H Reset value: xxxx xxx0b


TMGC

3:1








0 0: Disable the clock input of the TimerG counter.


TMGVL – TimerG Value

7 6 5 4 3 2 1 0

TMGVL[7:0]

R/W

Address: FAAH Reset value: xxxx xxxxb


TMGVL 7:0

TMGVH[3:0] and TMGVL[7:0] hold the reload-value of TimerG.

Write TMGVH first and then write TMGVL if wants to change the counter

value.

TMGVH – TimerG Value

7 6 5 4 3 2 1 0

TMGVH[3:0]

R/W

Address: FABH Reset value: xxxx xxxxb


TMGVH 3:0



value.

NSC Data Sheet


- 39 - Version A1.0

TMGOL – The Counting Value of TimerG

7 6 5 4 3 2 1 0

TMGOL[7:0]

R/W

Address: FACH Reset value: xxxx xxxxb


TMGOL 7:0

The counting value of TimerG can be read out via these registers TMGOH

[3:0] and TMGOL[7:0]. Read TMGOL first and then read TMGOH to get the

counting value.

TMGOH – The Counting Value of TimerG

7 6 5 4 3 2 1 0

- - - - TMGOH[3:0]

- - - - R/W

Address: FADH Reset value: xxxx xxxxb


TMGOH 3:0



counting value.

PCMH – The PCM Data of Speaker PWM

7 6 5 4 3 2 1 0

PCMH[7:0]

R/W

Address: FB5H Reset value: xxxx xxxxb


PCMH 7:0 The MSB 8 bits of PCM data of speaker PWM data can read from PCMH

register. The data format is 2’s complement.

VOL – PWM Driver Volume Control Register

7 6 5 4 3 2 1 0

- - - - - VOL[2:0]

- - - - - R/W

Address: FB6H Reset value: xxxx x111b


VOL 2:0 111b is the max volume.

NSC Data Sheet


- 40 - Version A1.0

PWMC – PWM Clock Source Selection

7 6 5 4 3 2 1 0

- - - - - PWMC[2:0]

- - - - - R/W

Address: FC0H Reset value: xxxx xxxxb


PWMC 2:0

000: PWM clock is Fsys/1.








PWMEN – PWM Enable Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - PWMEN.5 PWMEN.4 PWMEN.3 PWMEN.2 PWMEN.1 PWMEN.0

- - R/W R/W R/W R/W R/W R/W

Address: FC1H Reset value: xx00 0000b


PWMEN 5:0

0: PWMn is disable.

1: PWMn is enable.

The output port depends on PWMOA or PWMOB. n = 0 ~ 5.

PWM0EN – PWM Output Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - PWM0EN.2 PWM0EN.1 PWM0EN.0

- - - - - R/W R/W R/W

Address: FC2H Reset value: xxxx x000b


PWM0EN 2:0

0: BP0n is GPIO.

1: BP0n is PWM output port.

User needs to set BP0D.n as “0”.

NSC Data Sheet


- 41 - Version A1.0

PWMOA – PWM Output Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

PWMOA[7:6] PWMOA[5:4] PWMOA[3:2] PWMOA[1:0]

R/W R/W R/W R/W

Address: FC2H Reset value: 0000 0000b


PWMOA

7:6

Define PWM3 output port.

00: PWM3 output port is BP03, need to set BP0D.3 as 0.

01/10/11: Reserved.

5:4


00: PWM2 output port is BP02, need to setBP0D.2 as 0.

01/10/11: Reserved.

3:2




10/11: Reserved.


PWMOA 1:0




10/11: Reserved.

PWMOB – PWM 0utput Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - - - PWMOB[3:2] PWMOB[1:0]

- - - - R/W R/W

Address: FC3H Reset value: xxxx 0000b


PWMOB

3:2




10/11: Reserved.

1:0




10/11: Reserved.

NSC Data Sheet


- 42 - Version A1.0

PWV00 – PWM Output Level Width (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

PWV00[7:0]

R/W



PWV00 7:0

If BP0R.0 = 0, PWV00 defines PWM output high-level width on BP00

output pin. If PWV00 is N, N/255 is high within a period. If PWV00 is 00, it

always output low.

If BP0R.0 = 1, PWV00 defines PWM output low-level width on BP00

output pin. If PWV00 is N, N/255 is low within a period. If PWV00 is 00, it

always output high.

PWV0 – PWM Output Level Width (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

PWV0[7:0]

R/W



PWV0 7:0

If BP0R.0/BP0R.6 = 0, PWV0 defines PWM output high-level width on

BP00/BP06 output pin. If PWV0 is N, N/255 is high within a period. If

PWV0 is 00, it always output low.

If BP0R.0/BP0R.6 = 1, PWV0 defines PWM output low-level width on

BP00/BP06 output pin. If PWV0 is N, N/255 is low within a period. If

PWV0 is 00, it always output high.


7 6 5 4 3 2 1 0

PWV01[7:0]

R/W



PWV01 7:0



always output low.



always output high.

NSC Data Sheet


- 43 - Version A1.0


7 6 5 4 3 2 1 0

PWV1[7:0]

R/W



PWV1 7:0








7 6 5 4 3 2 1 0

PWV02[7:0]

R/W



PWV02 7:0



always output low.



always output high.


7 6 5 4 3 2 1 0

PWV2[7:0]

R/W



PWV2 7:0

If BP0R.2 = 0, PWV2 defines PWM output high-level width on BP02 output

pin. If PWV2 is N, N/255 is high within a period. If PWV2 is 00, it always

output low.

If BP0R.2 = 1, PWV2 defines PWM output low-level width on BP02 output

pin. If PWV2 is N, N/255 is low within a period. If PWV2 is 00, it always

output high.

NSC Data Sheet


- 44 - Version A1.0


7 6 5 4 3 2 1 0

PWV3[7:0]

R/W



PWV3 7:0



output low.



output high.


7 6 5 4 3 2 1 0

PWV4[7:0]

R/W



PWV4 7:0








7 6 5 4 3 2 1 0

PWV5[7:0]

R/W

Address: FCAH Reset value: xxxx xxxxb


PWV5 7:0







NSC Data Sheet


- 45 - Version A1.0

SPIC – SPI Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

SPIC.7 SPIC[6:5] - - - - SPIC.0

R R/W - - - - R/W

Address: FD8H Reset value: 0xxx xxx0b


SPIC

7 0: Transmit/receive done.

1: Transmit/receive not complete.

6:5

00: SPI clock rate is Fsys/1.




0

0: Disable SPI circuit.

1: Enable SPI circuit.

If SPIC.0=1, BP24~BP27 are configured as SPI related pins automatically.

SPIC – SPI Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

SPIC.7 SPIC[6:5] - - - SPIC.1 SPIC.0

R R/W - - - R/W R/W



SPIC



6:5





1 When SPI circuit is enabled (SPIC.0 = 1), this bit must be set as 0.

0




SPIB – SPI Data Buffer for Transmit/Receive

7 6 5 4 3 2 1 0

SPIB[7:0]

R/W

Address: FD9H Reset value: xxxx xxxxb


SPIB 7:0 SPI data buffer for transmit/receive.

NSC Data Sheet


- 46 - Version A1.0

SPIBN – Pseudo Register

7 6 5 4 3 2 1 0

SPIBN[7:0]

R/W

Address: FDAH Reset value: xxxx xxxxb


SPIBN 7:0 Reading SPIBN will get the data in SPIB, but SPI clock (SCK) is not sent

out.

7. I/O Port Structure and Operation

NSC provides three bi-directional (I/O) ports, BP0/BP1/BP2. Each port is an 8-bit wide I/O configurable

port, and user can access it from BP0R/BP1R/BP2R respectively. The writing and reading of a port

control register have different meanings. A write to port control register sets the port output latch logic

value, whereas a read gets the port pin logic state. All I/O pins can be configured individually as one of

four I/O modes by software. These four modes are open-drain output, CMOS output, floating input and

pull high or low input. Each port spends two special function registers BPxD and BPxM to select the I/O

mode. The list below illustrates how to select the I/O mode.

BPxD BPxM I/O Type

0 0 Open-drain output

0 1 CMOS output

1 0 Floating input

1 1 Pull high or low input

Table 7-1. Configuration for Different I/O Modes

Each input pin can be selected to be trigger source by setting the PxEN. Moreover, if the IEF0[0] is set,

which enables the port interrupt, the rising or falling edge of input pin will generate a port interrupt.

For noise immunity, there is a Schmitt-Trigger circuit implemented on each pin of BP0, BP1 and BP2

ports when it is used as an input pin. When chip is in STOP mode, the status change of BP0, BP1 and

BP2 ports can wake up the chip if the pin is configured as input pin and is enabled.

NSC Data Sheet


- 47 - Version A1.0

The NSC has a lot of I/O control registers to provide flexibility in all kinds of application. All of SFRs

are listed as follow.

BP0R - Bi-Directional Port 0 Data Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - BP0R.2 BP0R.1 BP0R.0

- - - - - R/W R/W R/W




BP0R - Bi-Directional Port 0 Data Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

BP0R.7 BP0R.6 BP0R.5 BP0R.4 BP0R.3 BP0R.2 BP0R.1 BP0R.0






7 6 5 4 3 2 1 0

BP1R.7 BP1R.6 BP1R.5 BP1R.4 BP1R.3 - - -






7 6 5 4 3 2 1 0

BP1R.7 - - - BP1R.3 BP1R.2 - -

R/W - - - R/W R/W - -



BP1R 7

Bi-directional (input/output) port 1 data register. 3:2


7 6 5 4 3 2 1 0

BP2R.7 BP2R.6 BP2R.5 BP2R.4 - - - -

R/W R/W R/W R/W - - - -




NSC Data Sheet


- 48 - Version A1.0


7 6 5 4 3 2 1 0

- - - - - - - BP2R.0

- - - - - - - R/W



BP2R 0 Bi-directional (input/output) port 2 data register.


7 6 5 4 3 2 1 0

- - - - - BP0D.2 BP0D.1 BP0D.0

- - - - - R/W R/W R/W






7 6 5 4 3 2 1 0

BP0D.7 BP0D.6 BP0D.5 BP0D.4 BP0D.3 BP0D.2 BP0D.1 BP0D.0







7 6 5 4 3 2 1 0

BP1D.7 BP1D.6 BP1D.5 BP1D.4 BP1D.3 - - -







7 6 5 4 3 2 1 0

BP1D.7 - - - BP1D.3 BP1D.2 - -

R/W - - - R/W R/W - -




1: BP1n is input pin. 3:2

NSC Data Sheet


- 49 - Version A1.0


7 6 5 4 3 2 1 0

BP2D.7 BP2D.6 BP2D.5 BP2D.4 - - - -

R/W R/W R/W R/W - - - -

Address: F86H Reset value: 1111 xxxxb





7 6 5 4 3 2 1 0

- - - - - - - BP2D.0

- - - - - - - R/W

Address: F86H Reset value: xxxx xxx1b





7 6 5 4 3 2 1 0

- - - - - BP0M.2 BP0M.1 BP0M.0

- - - - - R/W R/W R/W



BP0M 2:0


BP0M.n




BP0M.n




7 6 5 4 3 2 1 0

BP0M.7 BP0M.6 BP0M.5 BP0M.4 BP0M.3 BP0M.2 BP0M.1 BP0M.0




BP0M 7:0


BP0M.n




BP0M.n



NSC Data Sheet


- 50 - Version A1.0


7 6 5 4 3 2 1 0

BP1M.7 BP1M.6 BP1M.5 BP1M.4 BP1M.3 - - -




BP1M 7:3


BP1M.n




BP1M.n




7 6 5 4 3 2 1 0

BP1M.7 - - - BP1M.3 BP1M.2 - -

R/W - - - R/W R/W - -



BP1M

7


BP1M.n




BP1M.n



3:2


7 6 5 4 3 2 1 0

BP2M.7 BP2M.6 BP2M.5 BP2M.4 - - - -

R/W R/W R/W R/W - - - -



BP2M 7:4


BP2M.n




BP2M.n



NSC Data Sheet


- 51 - Version A1.0


7 6 5 4 3 2 1 0

- - - - - - - BP2M.0

- - - - - - - R/W



BP2M 0


BP2M.n




BP2M.n



8. Interrupt Controller

The interrupt controller arbitrates among various kinds of interrupt sources, if conflict occurs. Interrupt

priority can be arranged among these interrupt sources. The priority of the interrupt sources is as the

following equation:

TimerA > TimerG > UART_RX > Addressable LED > UART_TX > FXF10 > FXF13 >

FXF15 > LRCT > PORT

The IEF0 and IEF1 registers control which interrupt source being enabled. No matter the corresponding

IEF bit being set or not, an interrupt event will set the corresponding bit of the EVF0 or EVF1 register.

For IEF-enabled interrupt events, the interrupt controller arbitrates the queuing events based on the

priority of the interrupt sources. F/W needs to clear the corresponding bit of EVF0 and EVF1 by writing

“1” to the corresponding bit of EVF0 and EVF1 registers after ISR is serviced.




7 6 5 4 3 2 1 0





IEF0





1 TimerA INT enable/disable.


NSC Data Sheet


- 52 - Version A1.0

EF1 – Interrupt Enable Register 1 (For NSC128DF/192DF/384DF/512DF)



7 6 5 4 3 2 1 0

- - - - IEF1.3 - - -

- - - - R/W - - -



IEF1 3 LRCT INT enable/disable.

IEF1 – Interrupt Enable Register 1 (For NSC768DF/1K0DF)



7 6 5 4 3 2 1 0

- IEF1.6 IEF1.5 IEF1.4 IEF1.3 - - IEF1.0

- R/W R/W R/W R/W - - R/W

Address: F91H Reset value: x000 0xx0b


IEF1

6 UART RX LN (line status) INT enable/disable.

5 UART RX INT enable/disable.

4 UART TX INT enable/disable.

3 LRCT INT enable/disable.

0 Addressable LED INT enable/disable.


0: Non-queuing.

1: Queuing.


7 6 5 4 3 2 1 0





EVF0







NSC Data Sheet


- 53 - Version A1.0

EFV1 – Interrupt Event Register 1 (For NSC128DF/192DF/384DF/512DF)

0: Non-queuing.

1: Queuing.


7 6 5 4 3 2 1 0

- - - - EVF1.3 - - -

- - - - R/W - - -



EVF1 3 LRCT INT queuing/non-queuing.

EFV1 – Interrupt Event Register 1 (For NSC768DF/1K0DF)

0: Non-queuing.

1: Queuing.


7 6 5 4 3 2 1 0

- EVF1.6 EVF1.5 EVF1.4 EVF1.3 - - EVF1.0

- R/W R R R/W - - R



EVF1 6

UART RX LN (line status) flag. It is set or cleared by H/W according to bits

RXSTS[5:2].

5 UART RX FIFO event flag.


EVF1

4 UART TX FIFO event flag.

3 LRCT INT queuing/non-queuing.

0 Addressable LED FIFO event flag.

9. General Timer

Two Timers are supported, TimerA and TimerG. TimerA is 8-bit auto-reload down-counters, and

TimerG is 12-bit auto-reload down-counter. Any of them can be used as a general-purpose timer for

program control.

TimerA

When TimerA is enabled, the counter is loaded with TMAV to start the down counting. Once counter

underflows, the counter is reloaded with TMAV and keeps counting. The time out period is

(TMAV+1)/timer_clock. The free running counting value of TimerA can be read out from register

TMAO at any time.

When TimerA counter underflows, the related bit of the EVF0 register, EVF0.1, will be set. If the

corresponding interrupt is enabled (IEF0.1=1), it will generate TimerA interrupt.

NSC Data Sheet


- 54 - Version A1.0

Figure 3. TimerA Structure of NSC128DF/192DF/384DF/512DF

Figure 4. TimerA Structure of NSC768DF/1K0DF

NSC Data Sheet


- 55 - Version A1.0


7 6 5 4 3 2 1 0


R/W - - - R/W R/W



TMAC

7




3:1






101: clock = Fsys/8192.




7 6 5 4 3 2 1 0


R/W R/W - - R/W R/W



TMAC 7






TMAC

3:1






101: clock = Fsys/8192.



TMAV – TimerA Value

7 6 5 4 3 2 1 0

TMAV.7

R/W



TMAV 7:0 This register holds the reload-value of TimerA.

NSC Data Sheet


- 56 - Version A1.0

TMAO – The Counting Value of TimerA

7 6 5 4 3 2 1 0

TMAO.7

R/W



TMAO 7:0 The counting value of TimerA can be read out via this register.

TimerG

TimerG is also designed with capacitive touch sensing with trigger source from BP0/BP1 pin. Both

falling and rising edges from input pin can trigger the counting value of TimerG to be captured

immediately.

The free running counting value of TimerG can be read out from registers of 4-bit TMGOH and 8-bit

TMGOL at any time regardless of touch sensing function is enabled or not. When capture event occurs,

TimerG is stopped and the captured counter value can be got from registers TMGOH and TMGOL.

The 12-bit counter of TimerG is consisted of 4-bit TMGVH and 8-bit TMGVL. When user wants to

change the TimerG counter, the TMGVH should be written first and then write the TMGVL, the counter

value will be loaded when the TMGVL is written. To read the running counting value of TimerG in

general-purpose of TimerG, the TMGOL should be read first and then read the TMGOH to get the

counting value.

The counter underflow or timer capture event will set the related bit of the EVF0 register, EVF0.4. If the

corresponding interrupt is enabled (IEF0.4=1), it will generate TimerG interrupt.

Figure 5. TimerG Structure

NSC Data Sheet


- 57 - Version A1.0

TMGC – TimerG Control Register

7 6 5 4 3 2 1 0

- - - - TMGC[3:1] TMGC.0

- - - - R/W R/W

Address: FA9H Reset value: xxxx xxx0b


TMGC

3:1








0 0: Disable the clock input of the TimerG counter.


TMGVL – TimerG Value

7 6 5 4 3 2 1 0

TMGVL[7:0]

R/W

Address: FAAH Reset value: xxxx xxxxb


TMGVL 7:0



value.

TMGVH – TimerG Value

7 6 5 4 3 2 1 0

TMGVH[3:0]

R/W

Address: FABH Reset value: xxxx xxxxb


TMGVH 3:0



value.

TMGOL – The Counting Value of TimerG

7 6 5 4 3 2 1 0

TMGOL[7:0]

R/W

Address: FACH Reset value: xxxx xxxxb


TMGOL 7:0



counting value.

NSC Data Sheet


- 58 - Version A1.0

TMGOH – The Counting Value of TimerG

7 6 5 4 3 2 1 0

- - - - TMGOH[3:0]

- - - - R/W

Address: FADH Reset value: xxxx xxxxb


TMGOH 3:0



counting value.

10. Fixed-Frequency (FXF15/FXF13/FXF10) Interrupt Source

The frequency of the FXF15 interrupt source is (Fsys/32768). The falling edge of the divided clock sets

the EVF0.7 flag. If the IEF0.7 is set “1”, the event flag will generate the FXF15 interrupt.


the EVF0.6 flag. If the IEF0.6 is set “1”, the event flag will generate the FXF13 interrupt


the EVF0.5 flag. If the IEF0.5 is set “1”, the event flag will generate the FXF10 interrupt.

The relationships between the period and Fsys are as follows.

Fsys FXF10 FXF13 FXF15

20.48 MHz 0.05ms 0.4ms 1.6ms

10.24 MHz 0.1ms 0.8ms 3.2ms

6.83 MHz 0.15ms 1.2ms 4.8ms

5.12 MHz 0.2ms 1.6ms 6.4ms




7 6 5 4 3 2 1 0





IEF0





1 TimerA INT enable/disable.


NSC Data Sheet


- 59 - Version A1.0


0: Non-queuing.

1: Queuing.


7 6 5 4 3 2 1 0





EVF0







11. Watchdog Timer (WDT)

The WDT is used to prevent the program from unknown errors. Once the WDT is configured as enable,

the WDT is free running and the application program must clear WDT before it overflows. When WDT

overflow occurs, the chip will be reset.

The WDT time-out period is fixed. The reference clear WDT cycles are as follows.

Fsys Clear WDT cycle

20.48 MHz < 41ms

10.24 MHz < 82ms

6.83 MHz < 123ms

5.12 MHz < 164ms

WDTC – WDT Control Register

7 6 5 4 3 2 1 0

- - - - - - - WDTC.0

- - - - - - - R/W



WDTC 0 Write “1” to WDTC.0 register will clear the WDT.

NSC Data Sheet


- 60 - Version A1.0

12. Power Management

There is an operating mode designed for power saving, STOP mode. In the STOP mode, the most

power-saving mode, main oscillator and LRCT oscillator are disabled, the whole chip is temporarily shut

down.

The STOP mode is implemented by additional hardware peripherals. During the STOP mode, both

oscillators and all peripherals are all stopped until the mode is released. To enter the STOP mode, user

should use “STOP” macro. Then, the whole chip is completely shut down temporarily.

The STOP mode can be released by the status changes of the pins BP0/BP1/BP2 provided that the pins

are configured as input ports, and the respective port-enable-registers BP0EN/BP1EN/BP2EN are

enabled. Besides port status change, the STOP mode can be released by LRCT-based timer time out and

be released by IR-Wakeup mode input detected. Once STOP mode is released, chip will start operation

from reset condition after wakeup. The WAKEF register records the STOP mode release source which

causes the chip wakeup and reset.

If none of BP0EN/BP1EN/BP2EN is enabled, LRCT oscillator is disabled, and STOP macro is used to

intend to enter STOP mode, chip will not enter the STOP mode but go to reset program.

There is another operating mode designed for power saving, IR-Wakeup mode. In the IR-Wakeup mode,

the main oscillator is disabled but the LRCT oscillator is enabled, besides the IR detect function, other

peripherals are disabled until the mode is released.

WAKEF – Chip Wakeup and Reset Source Register

When chip releases from STOP mode, the corresponding bit will be set to reflect the reason

of wakeup reset. This register is designed to be cleared by user. Writing action will clear all

bits.

7 6 5 4 3 2 1 0

WAKEF.7 - WAKEF.5 WAKEF.4 WAKEF.3 WAKEF.2 WAKEF.1 WAKEF.0

R/W - R/W R/W R/W R/W R/W R/W

Address: F8DH Reset value: 0x00 0000b


WAKEF

7

Identify chip reset is from normal mode or STOP mode.

0: normal mode. F/W needs to check WAKEF.3, WAKEF.4, WAKEF.5 and

RSTF register to know the reset source.

1: STOP mode. F/W needs to check WAKEF.0, WAKEF.1, WAKEF.2 and

WAKEF.3 to know the wakeup reset source.

5 POR

4 LVR

3 RESET pin.

2 IR-Wakeup input condition matched.

1 LRCT time out.

0 Port input trigger.

NSC Data Sheet


- 61 - Version A1.0

RSTF – Chip Reset Source Register

When chip resets, the corresponding bit will be set to reflect the reason of reset.

This register is designed to be cleared by user. Writing “1” will clear the corresponding bit.

7 6 5 4 3 2 1 0

- - - - - - RSTF.1 RSTF.0

- - - - - - R/W R/W

Address: F8FH Reset value: xxxx xx00b


RSTF 1 WDT timeout.

0 No wake source and forces chip to STOP mode.

13. Low Speed RC (LRC) Oscillator

The frequency of low-speed RC oscillator is designed as 10.24 KHz. LRC is a clock source of LRC-

based timer. The LRC-based timer can be used as a general-purpose timer for program control and a

wakeup timer from STOP mode.

There are 256 levels of time out frequency in LRC-based timer when LRC oscillator is enabled. In

normal mode, the timer is used for general-purpose. If the IEF1.3 is set “1”, the LRCT interrupt service

routine will be executed if the LRC-based timer is time out.

In STOP mode, the timer is used as IR-Wakeup timebase if IR-Wakeup is enabled, or is used for chip

wakeup timer if IR-Wakeup is disabled. Both cases can release chip from STOP mode. Once STOP

mode is released, chip will start operation from reset condition after wakeup.

14. IR-Wakeup

NSC provides H/W IR-Wakeup function when chip is in STOP mode, which is IR-Wakeup mode, the

clock source comes from low speed RC oscillator (LRC). In IR-Wakeup mode, main oscillator is

disabled. LRC oscillator and related control registers decide the IR-Wakeup standby period, stable

period, and detect period.

There are two I/O pins are shared as H/W IR-Wakeup, they are IR power control (IRP) and IR detection

(IRD). In IR-Wakeup mode, NSC H/W will control IRP automatically and sense the input from IRD to

wakeup chip. The Figure 4 is the IR-Wakeup application circuit.

Figure 6. Tx and Rx application circuit

NSC Data Sheet


- 62 - Version A1.0

The following table are the I/O configurations of different series of IRP, IRD and IRC.

Chip

IR Wakeup IR Carrier

I/O Pin

Alternate 1

I/O Pin

Alternate 2

I/O Pin

Alternate 1

I/O Pin

Alternate 2

IRP IRD IRP IRD IRC IRC

NSC128DF

NSC192DF

NSC384DF

NSC512DF

BP15 BP16 BP25 BP26 BP14 BP24

NSC768DF

NSC1K0DF BP06 BP07 X X BP01 X

15. IR Communication

TimerA can be used to generate the frequency of IR carrier. In order to achieve these approaches, some

hardware control registers should be properly settled before IR carrier generator is enabled.

The IR carrier is enabled/disabled by the TMAC.7 register. When the IRC is configured as an output pin

and the TMAC.7 is set, the IR carrier will be output from the IRC. When the TMAC.7 is cleared, the

IRC will output the content of the BP1R.4 or BP2R.4 or BP0R.1 output buffer.

The IR carrier generator of NSC128DF/192DF/384DF/512DF.

Control bit

Bit BP1R.4

or

Bit BP2R.4

IRC Comment

BP1D.4 or BP2D.4 = 0/1

TMAC.7 = 0 0/1

Normal output / input pin

BP1D.4 or BP2D.4 = 0

TMAC.7 = 0/1 1

TMAC.7=1 TMAC.7=1 TMAC.7=1TMAC.7=0 TMAC.7=0

BP1R.4=1or

BP2R.4=1

BP1R.4=1or

BP2R.4=1

IR output pin

BP1D.4 or BP2D.4 = 0

TMAC.7 = 0/1 0

TMAC.7=1TMAC.7=0

BP1R.4=0or

BP2R.4=0

TMAC.7=1 TMAC.7=1TMAC.7=0

BP1R.4=0or

BP2R.4=0

IR output pin

The IR carrier generator of NSC768DF/1K0DF.

Control bit Bit BP0R.1 IRC Comment

BP0D.1 = 0/1

TMAC.7 = 0 0/1

Normal output / input pin

BP0D.1 = 0

TMAC.7 = 0/1 1

TMAC.7=1 TMAC.7=1 TMAC.7=1TMAC.7=0 TMAC.7=0

BP0R.1=1 BP0R.1=1

IR output pin

BP0D.1 = 0

TMAC.7 = 0/1 0

TMAC.7=1TMAC.7=0BP0R.1=0

TMAC.7=1 TMAC.7=1TMAC.7=0BP0R.1=0

IR output pin

NSC Data Sheet


- 63 - Version A1.0


7 6 5 4 3 2 1 0


R/W - - - R/W R/W



TMAC

7




3:1






101: clock = Fsys/8192.




7 6 5 4 3 2 1 0


R/W R/W - - R/W R/W



TMAC

7





3:1






101: clock = Fsys/8192.



IRMF0 – IR Alternative Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - - IRMF0.1 IRMF0.0

- - - - - - R/W R/W

Address: F9DH Reset value: xxxx xx00b


IRMF0

1 0: BP14 is shared as IR carrier output pin.

1: BP24 is shared as IR carrier output pin.

0 0: BP15 ~ BP16 are shared as IR wakeup pins.

1: BP25 ~ BP26 are shared as IR wakeup pins.

NSC Data Sheet


- 64 - Version A1.0

16. PWM Output Port

Each pin of PWM output port can have 255 steps PWM output control. PWMC is used to select the

PWM clock source. The one whole PWM output frequency are as follows.

Fsys PWM Clock

Fsys/1 Fsys/2 Fsys/4 Fsys/32 Fsys/64 Fsys/128 Fsys/256 Fsys/512

20.48MHz 80 KHz 40 KHz 20 KHz 2.5 KHz 1250 Hz 625 Hz 312 Hz 156 Hz

10.24 MHz 40 KHz 20 KHz 10 KHz 1.25 KHz 625 Hz 312 Hz 156 Hz 78 Hz



Register PWV0n(n=0~2) of NSC128DF/192DF/384DF/512DF and PWVm(m=0~5) of NSC768DF/

1K0DF define the low or high periods of PWM output. For example, if PWV1 register of NSC768DF/

1K0DF is set as “FFH” and BP0R.1 is 1, the corresponding PWM output (PWM1) will be low within

whole PWM period. For Fsys = 10.24MHz and PWMC[2:0] = 011B, the min. resolution of output width

is 3.125s. One whole PWM output period is 796.87s.

NSC128DF/192DF/384DF/512DF PWM output port control bits.

Control bit Bit BP0R.n (n=0~2) PWMn (n=0~2) Comment

PWM0EN.n (n=0~2) = 0

BP0D.n (n=0~2) = 0/1 0/1 Output/Input mode Normal output/input pin

PWM0EN.n (n=0~2) = 1

BP0D.n (n=0~2) = 0

1 PWV0n

One PWM Period

PWM output pin

0 PWV0n

One PWM Period

PWM output pin

NSC768DF/1K0DF PWM output port control bits.

Control bit Bit BP0R.n (n=0~7)

Bit BP1R.p (p=2~3)

PWMn (n=0~7)

PWMp (p=2~3) Comment

PWMEN.m (m=0~5) = 0

BP0D.n (n=0~7) = 0/1

BP1D.p (p=2~3) = 0/1

0/1 Output/Input mode Normal output/input pin

PWMEN.m (n=0~5) = 1

BP0D.n (n=0~7) = 0

BP1D.p (p=2~3) = 0

1 PWV0n

One PWM Period

PWM output pin

0 PWV0n

One PWM Period

PWM output pin

NSC Data Sheet


- 65 - Version A1.0

PWV0n

8-bit Up-

Counteroverflow

BP0n*8

8

Reset to 01H

A

B

Y

PWM0EN.n

EN

enable

Y = EN ? (A>B) ? BP0R.n : ~BP0R.n : BP0R.n;

PWMC[2:0]

Note1 : * Only output mode is shown here.

Note2 : n=0~2

111

Fsys/1

Fsys/512110

101

100

011

010

001

000Fsys/2

Fsys/4

Fsys/32

Fsys/64

Fsys/128

Fsys/256

Figure 7. PWM output port of NSC128DF/192DF/384DF/512DF

PWV0n

8-bit Up-

Counteroverflow

BP0n*

BP1p*

8

8

Reset to 01H

A

B

Y

PWMEN.m

EN

enable

Y = EN ? (A>B) ? BP0R.n : ~BP0R.n : BP0R.n;

Y = EN ? (A>B) ? BP1R.p : ~BP1R.p : BP1R.p;

PWMC[2:0]

Note1 : * Only output mode is shown here.

Note2 : m=0~5, n=0~7, p=2~3

111

Fsys/1

Fsys/512110

101

100

011

010

001

000Fsys/2

Fsys/4

Fsys/32

Fsys/64

Fsys/128

Fsys/256

Figure 8. PWM output port of NSC768DF/1K0DF

NSC Data Sheet


- 66 - Version A1.0

PWMC – PWM Clock Source Selection

7 6 5 4 3 2 1 0

- - - - - PWMC[2:0]

- - - - - R/W



PWMC 2:0









PWMEN – PWM Enable Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - PWMEN.5 PWMEN.4 PWMEN.3 PWMEN.2 PWMEN.1 PWMEN.0

- - R/W R/W R/W R/W R/W R/W

Address: FC1H Reset value: xx00 0000b


PWMEN 5:0

0: PWMn is disable.

1: PWMn is enable.

The output port depends on PWMOA or PWMOB. n = 0 ~ 5.

PWM0EN – PWM Output Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

- - - - - PWM0EN.2 PWM0EN.1 PWM0EN.0

- - - - - R/W R/W R/W

Address: FC2H Reset value: xxxx x000b


PWM0EN 2:0

0: BP0n is GPIO.

1: BP0n is PWM output port.

User needs to set BP0D.n as “0”.

PWMOA – PWM Output Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

PWMOA[7:6] PWMOA[5:4] PWMOA[3:2] PWMOA[1:0]

R/W R/W R/W R/W

Address: FC2H Reset value: 0000 0000b


PWMOA 7:6



01/10/11: Reserved.

NSC Data Sheet


- 67 - Version A1.0

5:4


00: PWM2 output port is BP02, need to setBP0D.2 as 0.

01/10/11: Reserved.

3:2




10/11: Reserved.


PWMOA 1:0




10/11: Reserved.

PWMOB – PWM Output Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

- - - - PWMOB[3:2] PWMOB[1:0]

- - - - R/W R/W

Address: FC3H Reset value: xxxx 0000b


PWMOB

3:2




10/11: Reserved.

1:0




10/11: Reserved.


7 6 5 4 3 2 1 0

PWV00[7:0]

R/W



PWV00 7:0



always output low.



always output high.

NSC Data Sheet


- 68 - Version A1.0


7 6 5 4 3 2 1 0

PWV0[7:0]

R/W



PWV0 7:0








7 6 5 4 3 2 1 0

PWV01[7:0]

R/W



PWV01 7:0



always output low.



always output high.


7 6 5 4 3 2 1 0

PWV1[7:0]

R/W



PWV1 7:0







NSC Data Sheet


- 69 - Version A1.0


7 6 5 4 3 2 1 0

PWV02[7:0]

R/W



PWV02 7:0



always output low.



always output high.


7 6 5 4 3 2 1 0

PWV2[7:0]

R/W


Name Bit

Description

PWV2 7:0



output low.



output high.


7 6 5 4 3 2 1 0

PWV3[7:0]

R/W



PWV3 7:0



output low.



output high.

NSC Data Sheet


- 70 - Version A1.0


7 6 5 4 3 2 1 0

PWV4[7:0]

R/W



PWV4 7:0








7 6 5 4 3 2 1 0

PWV5[7:0]

R/W

Address: FCAH Reset value: xxxx xxxxb


PWV5 7:0







17. Serial Peripheral Interface (SPI) Module

NSC provides one SPI module and is used for external SPI device. SPI is the master mode only. The

serial to parallel interface supports a fast and flexible way to communicate with the standard SPI device.

When SPI is enabled, SPI drives CS and SCK signal for external slave devices. Once SPI is disable, SPI

pins are returned to GPIO. F/W has to set those GPIO to adequate status before SPI is disabled in order

to keep SPI pins in suitable state.

When F/W writes data to SPIB register, data are copied to internal shift register and SPIC.7 is set by

H/W automatically. The data in shift register will be shifted out to the MOSI pin with the selected SPI

clock rate. After eight bits data are shifted out, SPIC.7 is cleared by H/W. And then F/W can write next

byte data to SPIB. If SPIB is written while the shift register data have not been shifted out completely,

the newly written byte will be ignored.

When data are shifted out through MOSI, input data through MISO are also shifted into internal shift

register simultaneously. F/W can read the shift-in data in SPIB or SPIBN register after SPIC.7 is cleared.

Reading SPIB can also make SPI output 8 continued clocks on SCK. SPIC.7 is set while F/W reading

SPIB and is cleared after 8 bits data are shifted into shift register. The continuous data read from slave

NSC Data Sheet


- 71 - Version A1.0

device can be achieved by reading SPIB continuously. The last byte data is suggested to be read through

SPIBN which will not make SPI output 8 continued clocks on SCK.

Only SPI mode 0 is designed. The definition of mode 0 is: SCK will keep low when idle, MISO pin is

sampled on the rising edge of SCK and MOSI pin is clocked out on the falling edge of SCK.

Figure 9. SPI communication

SPIC – SPI Control Register (For NSC128DF/192DF/384DF/512DF)

7 6 5 4 3 2 1 0

SPIC.7 SPIC[6:5] - - - - SPIC.0

R R/W - - - - R/W



SPIC 7 0: Transmit/receive done.



SPIC

6:5





0




NSC Data Sheet


- 72 - Version A1.0

SPIC – SPI Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0

SPIC.7 SPIC[6:5] - - - SPIC.1 SPIC.0

R R/W - - - R/W R/W



SPIC



6:5





1 When SPI circuit is enabled (SPIC.0 = 1), this bit must be set as 0.

0




SPIB – SPI Data Buffer for Transmit/Receive

7 6 5 4 3 2 1 0

SPIB[7:0]

R/W

Address: FD9H Reset value: xxxx xxxxb


SPIB 7:0 SPI data buffer for transmit/receive.

SPIBN – Pseudo Register

7 6 5 4 3 2 1 0

SPIBN[7:0]

R/W

Address: FDAH Reset value: xxxx xxxxb


SPIBN 7:0 Reading SPIBN will get the data in SPIB, but SPI clock (SCK) is not sent

out.

NSC Data Sheet


- 73 - Version A1.0

18. Capacitive Touch Sensing

There is a capacitive touch sensing with trigger source from CAP0 ~ CAP3 of NSC128DF/192DF/

384DF/512DF and CAP0 ~ CAP9 of NSC768DF/1K0DF. The feature is the ability to drive/sink a

current source to/from pin.

Note that use capacitive touch sensing function, BP17 is shared with RTP. If capacitive touch sensing

current source is enabled, BP17 will be set to RTP pin and need to connect an external resistor to VSS to

set the charge and recharge current in capacitive touch sensing. The external resistor value is fixed. It

can’t change resistor value. The following is the capacitive touch sensing application circuit.

Figure 10. Capacitive touch sensor application circuit of NSC128DF/192DF/384DF/512DF

NSC Data Sheet


- 74 - Version A1.0

Figure 11. Capacitive touch sensor application circuit of NSC768DF/1K0DF

19. Low Voltage Reset (LVR)

LVR can be used to avoid the hang-up problem. Below the minimum power-supply voltage, the P will

become unstable and malfunction. LVR will reset all functions into the initial operational state if the

power-supply voltage drops below the reference voltage.

The LVR level Vref is 1.9V when LVR is enabled. The chip will be reset and WAKEF.4 bit will be set

to 1 when VDD drops to less than Vref. Note that LVR will be disabled in STOP mode.

20. Brown-Out Detection (BOD)

Six option detection voltages are designed in BOD. Register BODC.7, read-only, is the BOD status flag.

User can poll this bit to check if VDD voltage is below VBOD condition or not.

The debounce time for BOD t is TBOD = 100S @Fsys = 10.24 MHz. If VDD voltage falls below VBOD

for less than TBOD, flag BODC.7 will not set. If VDD voltage falls below VBOD for longer than 2*TBOD,

flag BODC.7 will be set. If VDD voltage falls below VBOD for longer than TBOD, but less than 2*TBOD,

BODC.7 may or may not be set.

BODC[3:1] 101~111 100 011 010 001 000

VBOD External

Voltage 3.3V 3.0V 2.7V 2.4V 2.1V

If BOD is enabled and select VBOD as external reference voltage, BODE will be set to BOD external

input pin. For example, use resistors to divide voltage. If input voltage of BODE is 0.8V, flag BODC.7

will be set.

Note that BOD will be disabled in STOP mode. NSC768DF/1K0DF does not support the BOD external

input. The reference circuit is as follows.

Figure 12. Reference circuit of NSC128DF/192DF/384DF/512DF

NSC Data Sheet


- 75 - Version A1.0

BODC – BOD Control Register (For NSC128DF/192DF/384DF/512DF)

If BODC.0=1 and BODC[3:1]=101~111, BP02 is configured as BOD external input pin

automatically. But user needs to set BP02 as input floating.

7 6 5 4 3 2 1 0


R - - - R/W R/W



BODC



3:1






101~111: BOD level is external reference voltage.

0 0: Disable BOD.

1: Enable BOD.

BODC – BOD Control Register (For NSC768DF/1K0DF)

7 6 5 4 3 2 1 0


R - - - R/W R/W



BODC



3:1






101~111: Reserved.

0 0: Disable BOD.

1: Enable BOD.

NSC Data Sheet


- 76 - Version A1.0

21. Addressable LED Interface (For NSC768DF/1K0DF)

NSC768DF/1K0DF provides one addressable LED interface, which supports 1-wire mode connection.

1-wire mode consists only the output pin SDOUT. “Data 0” and “Data 1” are represented by varying

pulse width or pulse distance. Registers HIDA0/LODA0 and HIDA1/LODA1 define the pulse

characteristic of “Data 0” and “Data 1” respectively.

HIDA0 LODA0

Data 0

HIDA1 LODA1

Data 1

There are 32 bytes FIFO data buffer. A threshold register for FIFO is designed. When data is output

through SDOUT pin and the valid data count of the FIFO buffer is less than or equal to threshold, an

interrupt may be generated.

SLDC0 – Addressable LED Control Register

7 6 5 4 3 2 1 0

SLDC0.7 SLDC0.6 SLDC0.5 - - SLDC0.2 - SLDC0.0

R R W - - R/W - R/W

Address: F70H Reset value: 100x x0x0b


SLDC0

7

FIFO empty flag.

0: FIFO in not empty.

1: FIFO is empty.

6

FIFO full flag.

0: FIFO is not full.

1: FIFO is full, 32 bytes FIFO all are filled with data.

5

Reset FIFO.

0: No operation.

1: Write 1 to this bit to reset FIFO, SLDC0.6 will be set as “0”, SLDC0.7

will be set as “1”.

2

Data output control.

0: Stop data output. SDOUT keep in idle output. EFV1.0 is cleared.

1: Start data output from FIFO and continue output until FIFO is empty or

SLDC0.1 is written 0. If FIFO is empty, SDOUT keep in idle output.

When FIFO is empty, user needs to decide to clear SLDC0.2 or not.

0

Enable 1-wire addressable LED controller.

0: Disable.

1: Enable. BP00 or BP20 is the shared function output pin SDOUT, keep

the level as BP0R.0 or BP2R.0 in idle state. In general, set BP0R.0 or

BP2R.0 as “0”.

NSC Data Sheet


- 77 - Version A1.0

SLDC1 – Addressable LED Control Register

7 6 5 4 3 2 1 0

- - - - - - SLDC1.1 SLDC1.0

- - - - - - R/W R/W

Address: F71H Reset value: xxxx xx01b


SLDC1

1

Defines 1-wire addressable LED output pin when SLDC0.0 = 1.



0

Addressable LED data transmission method when addressable LED is

enabled.

0: Low bit data sent at first.

1: High bit data sent at first.

HIDA1 – High Level Period of Data Bit “1”

7 6 5 4 3 2 1 0

HIDA1[7:0]

R/W





LODA1 – Low Level Period of Data Bit “1”

7 6 5 4 3 2 1 0

LODA1[7:0]

R/W





HIDA0 – High Level Period of Data Bit “0”

7 6 5 4 3 2 1 0

HIDA0[7:0]

R/W





NSC Data Sheet


- 78 - Version A1.0

LODA0 – Low Level Period of Data Bit “0”

7 6 5 4 3 2 1 0

LODA0[7:0]

R/W





SDTH – FIFO Threshold

7 6 5 4 3 2 1 0

- - - SDTH[4:0]

- - - R/W



SDTH 4:0

If SLDC0.0 is 1 and the valid data count of the FIFO buffer is less than or

equal to SDTH[4:0] threshold, the EVF1.0 bit will set to 1, else the EVF1.0

bit will be cleared to 0. If IEF1.0 is 1, EVF1.0=1 will generate an interrupt.

SLDAT – Pushes Data onto The FIFO and Increments The Write Point

7 6 5 4 3 2 1 0

SLDAT[7:0]

W



SLDAT 7:0 A write to this register pushes data onto the FIFO and increments the write

point.

NSC Data Sheet


- 79 - Version A1.0

22. UART Interface (For NSC768DF/1K0DF)

Universal Asynchronous Receiver Transmitter (UART) provides an interface between uP and a serial

communication device. Data is transferred via two pins, TXD and RXD. These data lines share the same

pins with BP12 and BP13. By setting UMODE.6 and UMODE.7 to “1”, these pins will become UART

interface. Note that TXD or RXD can be individually controlled. The transmitter or receiver can be

enabled /disabled individually. The same programmable 9-bit divider is used to generate the baud rate of

the transmitter or receiver. The baud rate are as follows.

Baud Rate Description

7200 BRDIVH[0] = 1, BRDIVL[7:0] = 01100011

9600 BRDIVH[0] = 1, BRDIVL[7:0] = 00001010

19200 BRDIVH[0] = 0, BRDIVL[7:0] = 10000100

38400 BRDIVH[0] = 0, BRDIVL[7:0] = 01000010

57600 BRDIVH[0] = 0, BRDIVL[7:0] = 00101011

115200 BRDIVH[0] = 0, BRDIVL[7:0] = 00010101

230400 BRDIVH[0] = 0, BRDIVL[7:0] = 00001010

Receiver and Transmitter have individual 16 bytes FIFO. Data can be transferred in “stick 0” parity,

“stick 1” parity, even parity, odd parity or no parity. The special register, TXSTS and RXSTS indicate

the status of UART. Receiver FIFO and Transmitter FIFO can generate interrupt according to the

defined threshold. In addition, Receiver line status interrupt can be generated by the status of break in,

overrun, parity error or frame error.

NSC Data Sheet


- 80 - Version A1.0

UMODE – UART Control Register

7 6 5 4 3 2 1 0

UMODE.7 UMODE.6 UMODE.5 UMODE.4 UMODE[3:1] UMODE.0

R/W R/W R/W R/W R/W R/W



UMODE

7

Enable UART TXD module.

0: TXD disable.

1: TXD enable. User must also set TXSTS.1 as 0.

6

Enable UART RXD module.

0: RXD disable.

1: RXD enable. User must also set RXSTS.1 as 0.

5

Enable UART transmitter.

0: Disable.

1: Enable.


UMODE

4

Enable UART receiver.

0: Disable.

1: Enable.

3:1

UART mode selection.

If UMODE[3:2] is 00, no parity, UMODE.1 don’t care.

Data format is (Start, D0, D1, D2, D3, D4, D5, D6, D7, Stop).

If UMODE[3:2] is not 00, with parity bit.

Data format is (Start, D0, D1, D2, D3, D4, D5, D6, D7, Parity, Stop).

UMODE[3:1] define parity bit.





100: Even parity.

101: Odd parity.



0 0: No operation.

1: Force TXD to 0 (force break).

TXSTS – UART Transmitter Control and Status Register

7 6 5 4 3 2 1 0

TXSTS.7 TXSTS.6 - - - - TXSTS.1 TXSTS.0

R R - - - - R/W W

Address: F79H Reset value: 10xx xx0xb


TXSTS

7


0: Transmitter FIFO is not empty.

1: Transmitter FIFO is empty.

6


0: Transmitter FIFO is not full.

1: Transmitter FIFO is full.

NSC Data Sheet


- 81 - Version A1.0

1 When UART TX is enabled (UMODE.7 = 1), this bit must be set as 0.

0

Transmitter reset.

0: No operation.

1: Write 1 to this bit, all the byte in the transmit FIFO/transmit buffer and

TX internal state machine are cleared.

RXSTS – UART Receiver Control and Status Register

7 6 5 4 3 2 1 0

RXSTS.7 RXSTS.6 RXSTS.5 RXSTS.4 RXSTS.3 RXSTS.2 RXSTS.1 RXSTS.0

R R R/W R/W R/W R/W R/W W

Address: F7AH Reset value: 10xx xx0xb


RXSTS 7


0: Receiver FIFO is not empty.

1: Receiver FIFO is empty.


RXSTS

6


0: Receiver FIFO is not full.

1: Receiver FIFO is full.

5

Frame error. Set by H/W, cleared by F/W write 1.

0: No frame error.

1: Frame error (the receiver character has no valid stop bit).

If any bit of RXSTS[5:2] is set 1 by H/W, EVF1.6 will be set to 1. If

IEF1.6 is 1, EVF1.6 = 1 will generate an interrupt.

4

Parity error. Set by H/W, cleared by F/W write 1.

0: No parity error.

1: Parity error.

3

Break. Set by H/W, cleared by F/W write 1.

0: No break in.

1: The receiver character is “data bit = 0”, “parity bit = 0” and “no stop bit

(stop bit = 0)”.

2

Overrun. Set by H/W, clear by F/W write 1.

0: Receiver FIFO is not overflow.

1: Receiver FIFO is overflow.

1 When UART RX is enabled (UMODE.6 = 1), this bit must be set as 0

0

Receiver reset.

0: No operation.

1: Write 1 to this bit, all the byte in the receive FIFO/receive buffer and RX

internal state machine are cleared.

NSC Data Sheet


- 82 - Version A1.0

BRDIVH – UART Baud Rate Divider Register

7 6 5 4 3 2 1 0

- - - - - - - BRDIVH.0

- - - - - - - R/W

Address: F7BH Reset value: xxxx xxxxb


BRDIVH 0 The baud rate divider is controlled by BRDVIH.0 and BRDIVL[7:0].

BRDIVL – UART Baud Rate Divider Register

7 6 5 4 3 2 1 0

BRDIVL[7:0]

R/W

Address: F7CH Reset value: xxxx xxxxb


BRDIVL 7:0 The baud rate divider is controlled by BRDVIH.0 and BRDIVL[7:0].

URTHD – FIFO Threshold to Trigger Interrupt

7 6 5 4 3 2 1 0

URTHD[7:4] URTHD[3:0]

R/W R/W

Address: F7DH Reset value: 1111 0000b


URTHD

7:4

Defines receiver FIFO threshold to trigger interrupt.

If the valid data count of Rx FIFO buffer is more than or equal to URTHD



3:0

Defines transmitter FIFO threshold to trigger interrupt.

If the valid data count of TX FIFO buffer is less than or equal to URTHD



URDATA – Data Transfer Register

7 6 5 4 3 2 1 0

URDATA[7:0]

R/W

Address: F7EH Reset value: xxxx xxxxb


URDATA 7:0

By writing one byte to this register, the data byte will be stored in UART

transmitter FIFO.

By reading this register, one data byte will returned from UART receiver

FIFO.

NSC Data Sheet


- 83 - Version A1.0

TDLY – The Transfer Delay Time

7 6 5 4 3 2 1 0

- - - - TDLY[3:0]

- - - - R/W

Address: F7FH Reset value: xxxx 0000b


TDLY 3:0 Defines the transfer delay time between the last Stop bit and next Start bit

in transmission. The unit is baud.

23. Mask Option

Mask options is as follows.

WDT Enable: Watchdog Timer

Enable / Disable

LVR Enable: Low Voltage Reset

Enable / Disable

Pull-high / Pull-low Resistor

Pull-Low Resistor 1M / Pull-Low Resistor 150K

Pull-High Resistor 1M / Pull-High Resistor 150K

Security Lock (LOCK bit): Protects chip data

Lock / Not Lock

Fcpu: 65C02 clock source

20 MHz / 10 MHz / 6.66 MHz / 5 MHz

Fsys: Peripherals device clock source

20 MHz / 10 MHz / 6.66 MHz / 5 MHz

Protection Page: Reserved for ISP macro use

Disable: User can use ISP macro to read or write arbitrary address, but be careful not to write to

the user’s program section.

512 bytes in total: User can use ISP macro address range 1200H ~ 13FFH.

NSC Data Sheet


- 84 - Version A1.0

24. Electrical Characteristics

24.1 Absolute Maximum Ratings

Parameter Symbol Conditions Rated Value Unit

Power Supply VDD-VSS - -0.3 to +7.0 V

Input Voltage VIN All Inputs VSS-0.3 to VDD+0.3 V

Storage Temp. TSTG - -55 to +150 C

Operating Temp. TOPR - -20 to +85 C

Note: Exposure to conditions beyond those listed under the Absolute Maximum Ratings table may adversely affect the life

and reliability of the device.

24.2 D.C. Characteristics

(VDD VSS = 4.5V, TA = 25C, No Load unless otherwise specified)

Parameter Sym Conditions Min Typ Max Unit

Operating Voltage VDD 2.0 - 5.5 V

Operating Current IOP1 No load - 4 6 mA

Standby Current (STOP) IDD1 No load - 1 2 A

Input Low Voltage VIL All input pins VSS - 0.3 VDD V

Input High Voltage VIH All input pins 0.7 VDD - VDD V

Pull High resistor

BP0, BP1, BP2 RPH VDD = 4.5V

90K

0.6M

150K

1M

210K

1.4M

Pull Low resistor

BP0, BP1, BP2 RPL VDD = 4.5V

90K

0.6M

150K

1M

210K

1.4M

Output Current

BP0, BP1, BP2

IOL VDD = 3V, VOUT = 0.4V 8 12 - mA

IOH VDD = 3V, VOUT = 2.6V -4 -6 - mA

IOL VDD = 4.5V, VOUT = 1.0V - 25 - mA

IOH VDD = 4.5V, VOUT = 3.5V - -12 - mA

Output Current IOL1 RL= 8Ω

[PWM+]---[RL]----[PWM-]

+250 - - mA

PWM+ / PWM- IOH1 -250 - - mA

BOD detect voltage VBOD -

2.1

2.4

2.7

3.0

3.3

- V

NSC Data Sheet


- 85 - Version A1.0

24.3 A.C. Characteristics

(VDD = 4.5V, TA = 25C, No Load unless otherwise specified)

Parameter Sym Conditions Min Typ Max Unit

Frequency Deviation of

Fosc by Voltage Drop F/F

(Fmax – Fmin)/Fmin

@VDD: 2.4 ~ 5.5V - 2 - %

24.4 ESD Characteristics

Symbol Ratings Condition Maximum Unit

VESD

Electrostatic discharge

(Human body mode) TA = 25C

2000 V

Charge discharge mode 500 V

25. Typical Application Circuit

4.7uF

VDD_SPK

VSS

PWM-

PWM+

VSS_SPK

VDD

BP00|BP07

BP12|BP17

/RESETBP20|BP27

Battery

C30.1uF

C1

NSC

REGC20.1uF

VDD

VDD

Note:

NSC128DF/192DF/384DF/512DF GPIO are BP00~BP02, BP13~BP17, BP24~BP27.

NSC768DF/1K0DF GPIO are BP00~BP07, BP12/13/17, BP20.

NSC Data Sheet


- 86 - Version A1.0

PCB Layout Notice

Please refer to the following description.

1. The 4.7uF for battery connected to the IC pad as near as possible.

2. The VSS_SPK and VSS should have its own path to connect with negative of battery.

3. The VDD_SPK and VDD should have its own path to connect with positive of battery.

26. Package Dimension

20-pin TSSOP-4.4 x 6.5 mm

NSC Data Sheet


- 87 - Version A1.0

NSC Data Sheet


- 88 - Version A1.0

27. Revision History

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which

may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments,

airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use,

traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of

customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.

Version Date Substantial Changes Page

A1.0 July 2020 Initial Release All

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