Conductivity modulation in the channel inversion layer

of very narrow mesa IGBT

Masahiro Tanaka

Nihon Synopsys G.K. 2-21-1 Tamagawa, Setagaya-ku, Tokyo, 158-0094, JAPAN.

E-mail: mtanaka@mem.iee.or.jp

Akio Nakagawa

Nakagawa Consulting Office, LLC. 3-8-74 Hamatake, Chigasaki-city, Kanagawa, 253-0021, JAPAN.

E-mail: akio.nakagawa.dr@ieee.org

Abstract—It was experimentally found that the short-circuit withstand capability of very narrow mesa IGBTs is degraded because of CIBL. In this paper, we report, for the first time, that conductivity modulation in the channel inversion layer of narrow mesa IGBT is the cause of CIBL. It is shown that the combination of the conductivity modulation and avalanche generation due to MOSFET-Mode operation causes short-circuit failure. We also propose a new cell design principle of narrow mesa IGBTs for low on-state voltage drop and good short-circuit withstand capability.

Keywords—Narrow mesa IGBT; Short circuit; Current filament.

I. INTRODUCTION

IGBT is still widely used in the middle to high power electronics field although the wide bandgap devices were commercialized, recently. It was predicted that the IGBTs with extremely narrow mesa realize theoretical silicon limit performance[1]. However, it was reported recently that the actually fabricated very narrow mesa IGBTs[5-9] have poor short-circuit withstand capability because of CIBL (Collector bias Induced Barrier Lowering) related current filamentation[2]. The failure mechanism has not been clarified yet.

In this paper, first, we closely analyze the mechanism of CIBL and its related current filamentation by TCAD simulations. We report, for the first time, that conductivity modulation occurs in the channel inversion layer of very narrow mesa IGBTs. This increases the conductivity in the channel and increases the collector current of narrow mesa IGBT. This is the cause of collector current increase by so-called “CIBL”. Second, we report that there are two reasons for the CIBL related current filamentation during the short-circuit operation. Third, we propose a new device design of the narrow mesa IGBT. The structure is characterized by an optimized mesa width and a cell pitch, uniformly doped P-base layer and a thinner gate oxide for 5V gate drive. The proposed structure realizes a lower on-state voltage drop and a practical saturation current by effectively suppressing CIBL. The device is expected to have good short-circuit withstand capability.

II. TCAD SIMULATION SETUP

The simulated IGBTs were 1.2kV rated and had the N-base thickness of 120um. The simulations included the IAL (Inversion and Accumulation Layer) mobility model to accurately reproduce the carrier distributions in the narrow mesa, as well as conventionally used mobility models and generation-recombination models. TCAD Sentaurus Device was used for all the simulations.

In order to analyze the mechanism of CIBL, the mesa width was varied from 20nm to 1.0um. The trench depth and the P-base depth were fixed at 2.0um and 1.0um respectively. The gate

oxide thickness is 100nm. The half cell pitch W was fixed at 10um, if not specified.

Fig. 1. Cross sectional view of simulated structures.

III. RESULTS AND DISCUSSION

A. CIBL mechanism

Fig. 2 shows the on-state carrier distributions in the center of the mesa region. If the mesa width is extremely narrow, the whole mesa becomes an inversion/accumulation layer. We found that conductivity modulation occurs in the inversion layers of the P-base in 20nm and 100nm mesa IGBTs, and both electron and hole densities become greater than the impurity density of the P-base. This is because the hole current flows into the inversion layer of the P-base. This effect does not occur in conventional IGBTs because the hole current flows into the neutral P-base and does not flow inside the channel.

Fig. 2. Carrier distributions in the center of the mesa region. Very high conductivity modulation occurs in the channel inversion layer of 20nm & 100 nm mesa IGBTs. Both the electron and hole densities far exceed the P-base impurity doping density in 20nm mesa IGBT.

Fig. 3 shows IC-VG curves of the narrow mesa IGBTs. If the mesa width is extremely narrow, less than 100nm, the threshold

W

(b) Conventional IGBT cell(a) Narrow mesa IGBT cell

20-400nm 1.0um

W1.0um

2.0um1.0um

2.0um

N-base N-base

Gat

e

Gat

e

Gat

e

Gat

e P-base

N-emitter

P-base

N-emitter

Emitter Emitter

1.0x1020

Ele

ctr

on

/Ho

le D

en

sity

(C

en

ter

of

the m

esa

)[cm

-3]

0.01.0x1013

2.0 4.0Distance from Emitter electrode[um]

Doping concentration

1.0x1019

1.0x1018

1.0x1017

1.0x1016

1.0x1015

1.0x1014

Trench depth

Mesa width=100nm

Mesa width=1.0um

(Conventional)

Mesa width=400nm

W=10um, TOX=100nm

JC=500A/cm2

e

e

h

h

P-Base

1.0 3.0

e

h

Mesa width=20nm

Center of the mesa

Mesa width

Proceedings of The 29th International Symposium on Power Semiconductor Devices & ICs, Sapporo

61

3-2

voltage becomes lower and the transconductance becomes higher because the conductivity modulation occurs in the inversion layer of the P-base. The combination of the CIBL and high transconductance may cause short-circuit failure because slight gate voltage instability may cause large variation of the collector current.

Fig. 3. IC-VG characteristics of the narrow mesa IGBTs. As a

consequence of the conductivity modulation, the threshold voltage becomes lower and the transconductance becomes higher in case that the mesa width is less than 100nm.

B. CIBL related short-circuit failure mechanism

We found two causes for CIBL related short-circuit failure. Both are induced by the MOSFET-Mode operation[3]. MOSFET-Mode is defined in such a way that the anode efficiency γ(= 𝐽𝑝/𝐽) is less than γ𝑀𝑂𝑆 , which represents 𝜇𝑝/(𝜇𝑝 + 𝜇𝑛) . γ and γ𝑀𝑂𝑆 are defined at the N-base N-buffer

junction.

The net charge ρ in the high field region can be calculated with the donor density 𝑁𝐷.

ρ = 𝑁𝐷 + 𝑝 − 𝑛 = 𝑁𝐷 + (𝛾

𝑣ℎ+𝛾 − 1

𝑣𝑒)𝐽

𝑞

= 𝑁𝐷 + (𝜈ℎ + 𝜈𝑒𝜈ℎ𝜈𝑒

) (𝛾 − 𝛾𝑀𝑂𝑆)𝐽

𝑞 (1)

𝛾𝑀𝑂𝑆 =𝜇𝑝

𝜇𝑝 + 𝜇𝑛=

𝜈ℎ𝜈ℎ + 𝜈𝑒

(2)

where 𝑣𝑒 and 𝑣ℎ are saturation velocities. For the high electric field case, γ𝑀𝑂𝑆 is given by Eq.(2). When the anode efficiency γ is less than γ𝑀𝑂𝑆 , the second term in Eq.(1) is negative, and the net charge ρ becomes negative for sufficiently large current density 𝐽. Once the net charge becomes negative, a high electric field region appears in the anode side of the N-base.

(i) Current filament formation by anode side avalanche

Fig. 4 shows that the electron injection efficiency of very narrow mesa IGBTs exceeds 0.9. This means that very narrow mesa IGBTs operates in the deep MOSFET-Mode. Thus, when a large collector voltage is applied to narrow mesa IGBTs, a high electric field appears at the N-base N-buffer junction, and induces a large avalanche generation, as shown in Fig. 5. The generated holes flow into the narrow mesa and enhances the conductivity modulation of the mesa as shown in Fig. 6. Thus,

the collector current of narrow mesa IGBTs significantly increases as the collector voltage increases, as shown in Fig. 5.

When the avalanche generation in the N-base N-buffer junction exceeds a critical value, current filaments appear even in the isothermal condition[4]. Because the hole current density is significantly large inside the filament, this enhances the conductivity modulation of the very narrow mesa and creates larger current density filaments, as shown in Fig. 7.

Fig. 4. Relationship between the injection efficiencies and the mesa

width. The electron injection efficiency exceeds 0.9 in very narrow mesa IGBTs.

Fig. 5. Current saturation characteristics are shown for 20nm and 1um mesa IGBTs. The different gate voltage is applied for each device so that the saturation current reaches 1000A/cm2 at VCE=600V. The collector current of the 20nm mesa IGBT significantly increases as the collector voltage increases. For both IGBTs, large avalanche generation occurs at the N-base N-buffer junctions when VCE > 200V.

Fig. 6. Carrier distributions in the mesa region for VCE=5V and 600V. The carrier densities in the mesa of the narrow mesa IGBT are increased by the avalanche induced holes.

Coll

ecto

r C

urr

ent

Den

sity

[A/c

m2]

0.01.0x10-8

10.0 15.0Gate Voltage[V]

1.0x104

1.0x102

1.0x100

1.0x10-2

1.0x10-4

1.0x10-6

Mesa width=40nm

Mesa width=100nm

Mesa width=200nm

Mesa width=400nm, 1.0um

W=10um

VCE=5V

5.0

Mesa width=20nm

0.0

0.1

0.2

0.3

0.4

0.5

0.6

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1.0

0.0 0.2 0.4 0.6 0.8 1.0

Inje

ctio

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ffic

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e,h/J

mesa width[um]

0.0

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e,h/J

mesa width[um]

An

od

e

Eff

icie

ncy

Jh/J

Cat

ho

de

Eff

icie

ncy

Je/

J

Electron injection efficiency

Hole injection efficiency

0

200

Co

llec

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urr

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ensi

ty[A

/cm

2]

0

2.0x1022

Max

imu

m A

vala

nch

e g

en

era

tio

n r

ate

[cm

-3/s

ec.]

400

600

800

1000

Collector Voltage[V]200 400 600

4.0x1022

6.0x1022

8.0x1022

1.0x1023

Mesa width=20nm

Mesa width=1.0um

(Conventional)

Jc

Avalanche

W=10um

1.0x1020

Hole

Den

sity

(C

ente

r of

the

mes

a)[c

m-3

]

0.01.0x1013

2.0 4.0Distance from Emitter electrode[um]

Mesa width=1.0um

(Conventional)

Mesa width=20nm

Doping concentration

VCE=600V

VCE=5V

VCE=600V

VCE=5V

1.0x1019

1.0x1018

1.0x1017

1.0x1016

1.0x1015

1.0x1014

Trench depth

1.0 3.0

P-Base W=10um

62

Fig. 7. Carrier distributions in the mesa region of the 20nm mesa IGBT are plotted along the line of Y=80um (center of the current filament) and Y=0um (outside the current filament). The conductivity modulation is enhanced inside the filament in spite of the isothermal simulation.

(ii) Temperature dependence of MOSFET-Mode operation

The saturation current of the narrow mesa IGBT increases as the lattice temperature rises as shown in Fig. 8. This phenomenon can be explained by the temperature dependence of the γ𝑀𝑂𝑆 value. As shown in Fig. 9, the γ𝑀𝑂𝑆 value dynamically changes as the electric field or the lattice temperature changes inside the device because the mobility 𝜇𝑝 and 𝜇𝑛 are functions of electric field and temperature.

Fig. 8. Temperature dependence of the current saturation

characteristics are shown for 20nm mesa IGBT. The gate voltage is adjusted so that the saturation current reaches 1000A/cm2 at VCE=600V and T=25C. The collector current significantly increases as VCE increases at T=150C due to avalanche generation.

Fig. 9. Analytically calculated γ𝑀𝑂𝑆 vs. lattice temperature with

electric field as a parameter.

In the high field condition, the γ𝑀𝑂𝑆 value increases as the lattice temperature rises over the room temperature. This further increases the electric field as well as the avalanche generation rate at the N-base N-buffer junction, resulting in more severe current filament formation because of the positive feedback between the increase in γ𝑀𝑂𝑆 and the temperature rise.

C. Minimization of the on-state voltage drop

Conventional IGBTs have an optimum ratio of mesa width over the cell pitch for a minimum on-state voltage drop and maximized IE effect, as seen in Fig. 10, where on-state voltage drop is shown as a function of half unit cell pitch W. Regarding the very narrow mesa IGBTs, it is found that the on-state voltage drop simply reduces as the unit cell pitch becomes narrower. This tendency comes from the fact that the whole mesa becomes an inversion/accumulation layer and increases the electron density under the trench bottom, directly enhancing the electron injection efficiency. This mechanism is quite different from conventional IE effect.

Fig. 10. On-state voltage drop as a function of half unit cell pitch W.

In the conventional IE effect, VCE(sat) takes a minimum depending on the ratio of mesa width over the cell pitch. In the narrow mesa IGBT, VCE(sat) simply decreases as cell pitch reduces because the whole mesa becomes an inversion/accumulation layer.

IV. SHORT-CIRCUIT SIMULATION AND PROPOSED STRUCTURE

In order to realize good short-circuit withstand capability, the conductivity modulation inside the channel has to be prevented. We executed short-circuit simulations using the two IGBT structures of 100nm and 200nm mesas. The 200nm mesa probably is a minimum mesa width, which is sufficient to prevent the conductivity modulation in the channel inversion layer. The half cell pitch W is set as 4um to realize a low on-state voltage drop and the positive temperature dependence of the saturation current. If much narrower W is chosen for 200nm IGBTs, the device saturation current increases as temperature increases over the room temperature. This may degrade the short-circuit withstand capability.

We found that, according to the well-known “long channel MOSFET theory:”

OX

THGsaturation

T

VVI

2)( ,

the IGBT saturation current Isaturation can be successfully reduced without sacrificing the low on-state voltage drop by simultaneously reducing both the thickness TOX of the gate oxide and the applied gate voltage VG with keeping the same magnitude of the applied gate electric field. The gate oxide thickness is set at 33nm and the gate voltage is, thus, set at 5V in place of 15V. The P-base impurity profile is set as uniform and the concentration is 6x1017/cm3 for 100nm IGBT and 4x1017/cm3 for

VCE=600V

VG=7.0V

1.0x1020

Ele

ctro

n/H

ole

den

sity

(ce

nte

r of

the

mes

a)[c

m-3

]

1.0x1013

1.0x1019

1.0x1018

1.0x1017

1.0x1016

1.0x1015

1.0x1014

0.0 2.0 4.0Distance from Emitter electrode[um]

Y=0um

Y=80um

(Filament Center)

Doping concentration

Y=0um Y=80um

Trench depth

1.0 3.0

P-Base

160um

(W=10um, 8cells)

0

Co

llec

tor C

urr

entD

ensi

ty[A

/cm

2]

0

1.0x1023

Max

imu

m A

vala

nch

e g

en

era

tio

n r

ate[c

m-3

/sec.]

500

1000

1500

Collector Voltage[V]200 400 600

2.0x1023

3.0x1023

4.0x1023

5.0x1023

T=150C

T=25CJc

Avalanche

W=10um

Mesa width=20nm

0.2

0.25

0.3

0.35

0.4

0.45

0.5

300 500 700 900 1100 1300Temperature[K]

γ𝑀𝑂𝑆

=

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2 4 6 8 10

VC

E(s

at)@

500A

/cm

2, V

G=

15V

Half Cell Pitch W[um]

Mesa width=100nmMesa width=40nm

Mesa width=400nm

Mesa width=1.0um

(Conventional)

Mesa width=200nm

63

200nm IGBT, respectively. The uniformly doped P-base is good to reduce the saturation current. A lightly doped N-buffer[10] is also applied to reduce the avalanche generation at the N-base N-buffer junction.

The on-state voltage drop of the 200nm mesa IGBT is 1.25V for 200A/cm2. Fig. 11 shows the current saturation characteristics of the two IGBTs. The saturation current decreases as the lattice temperature becomes higher.

Fig. 11. Current saturation characteristics of proposed IGBT. The

different P-base impurity concentration (4x1017/cm3 for 200nm and 6x1017/cm3 for 100nm mesa device) is applied for each device so that the saturation current reaches 1000A/cm2 at VCE=600V in T=25C. The saturation current has positive temperature dependence.

Fig. 12. Short-circuit waveforms for calculated IGBTs. The 200nm

mesa width device was successfully turned-off after 10us. In contrast, the 100nm mesa width device failed immediately when the device turned on. The maximum lattice temperature of the 200nm mesa width device was observed in the high electric field region in the N-base.

Fig. 12 compares the short-circuit waveforms of the two IGBTs. In this simulation, completely symmetric 16 cells structure was used and a 0.3cm2K/W of thermal resistance was added on the collector electrode. The 200nm mesa IGBTs successfully turned off after 10us whereas the 100nm IGBT failed immediately when the devices turned on. No current filamentations were observed in the 200nm IGBT during the short-circuit operation. The maximum lattice temperature was observed in the high electric field region in the N-base.

Fig. 13(a) compares the waveforms of the gate voltages and the collector currents of the two IGBTs from t=0us to t=2.0us. The gate voltage of the 100nm mesa IGBT shows an overshoot exceeding 5V, which significantly increases the collector current density throughout the device because of the high transconductance, as seen in Fig.13(b). The device finally latched-up after 1.3us. The large hole current density flowing in

the mesa rapidly increases the potential in the P-base and creates the gate voltage overshoot. Fig. 14 shows the transient electron distributions of various time steps in the mesa of the 100nm IGBT. The high electron densities were observed inside the mesa in the center of the device. The simulation results prove that at least 200nm width is required for the mesa to prevent the conductivity modulation in the channel by reducing the neutral P-base resistance.

Fig. 13. (a) Comparison of short-circuit waveforms of 100 and 200nm

mesa IGBTs from t=0us to t=2.0us. The gate voltage of the 100nm mesa IGBT shows slight overshoot exceeding 5V. It significantly increases the collector current density of 100nm IGBT. (b) Transient electron current density distributions of the 100nm mesa IGBT at Y=110um. Current density is increased almost uniformly throughout the device before 1.3us. Current filamentation is not the main cause of the present device destruction.

Fig. 14. Transient electron distributions in the mesa region of the

100nm mesa IGBT are plotted along the line of Y=64um (center of the current filament; red lines) and Y=0um (outside the current filament; black dashed lines).

REFERENCES

[1] A. Nakagawa, Proc. of ISPSD’06, pp. 5-8, 2006. [2] K. Eikyu, A. Sakai, H. Matsuura, Y. Nakazawa, Y. Akiyama, Y. Yamaguchi and M. Inuishi, Proc. of ISPSD’16, pp. 211-214, 2016. [3] A. Nakagawa, T. Matsudai, T. Matsuda, M. Yamaguchi and T. Ogura, Proceedings of ISPSD’04, pp.103- 106, 2004. [4] M. Tanaka and A. Nakagawa, Proc. of ISPSD’15, pp. 121-124, 2015. [5] M. Sumitomo, J. Asai, H. Sakane, K. Arakawa, Y. Higuchi, and M. Matsui, Proc. of ISPSD’12, pp.17-20, 2012. [6] M. Antoniou, N. Lophitis, F. Udrea, F. Bauer, I. Nistor, M. Bellini and M. Rahimo, Proc. of ISPSD’15, pp. 21-24, 2015. [7] H. Feng, W. Yang, Y. Onozawa, T. Yoshimura, A. Tamenori and J. K. O. Sin, Proc. of ISPSD’16, pp. 203-206, 2016. [8] M. Shiraishi, T. Furukawa, S. Watanabe, T. Arai and M. Mori, Proc. of ISPSD’16, pp. 199-202, 2016. [9] K. Kakushima, et. al. IEDM 2016 Technical Digest, pp. 10. 6. 1-4, 2016. [10] M. Tanaka and A. Nakagawa, Proc. of ISPSD’16, pp. 319-322, 2016.

0

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Collector Voltage[V]200 400 600

Mesa width=200nm

Mesa width=100nm

T=150C

W=4um, TOX=33nm

VG=5V

T=25C

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VCC=600V, VG=5V, tW=10us

IC

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atti

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emp

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=100nm

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TmaxIC

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V]

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Time[us]0.5 1.0 2.0

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[A/c

m2]

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=200nm

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IC0

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=100nm

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m2]

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Y[um]50 128100

5

t=1.0us

t=1.2us

t=1.3us

t=1.4us

0

(a) Short-Circuit waveforms (b) Electron current distribution transient

X=110um

Mesa width=100nm

1.0x1020

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ensi

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Cen

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the

mes

a)[c

m-3

]

0.01.0x1013

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Doping concentration

1.0x1019

1.0x1018

1.0x1017

1.0x1016

1.0x1015

1.0x1014

Trench depth

t=1.4us(center)

W=4um, TOX=33nm,Mesa width=100nm

P-Base

1.0 3.0

1.0x1021

t=1.4us(outside)

t=1.0us

t=1.2us

t=1.0us

128um

Y=64umY=0um

t=1.3us(center) t=1.3us

(outside)

64