Novel Wire Density Driven Full-Chip Routing for CMP Variation Control

Novel Wire Density Driven Full-Chip Routing for CMP Variation Control

Huang-Yu Chen†, Szu-Jui Chou†, Sheng-Lung Wang‡, and Yao-Wen Chang†

†National Taiwan University, Taiwan

‡Synopsys, Inc, Taiwan

2

Outline

CMP Introduction

Previous Work

Wire-Density Driven Two-Pass Top-Down Routing

Experimental Results

Conclusion

3

Outline

CMP IntroductionCMP Introduction

Previous Work



Conclusion

4

Cu Damascene Process

The Cu metallization (Damascene) contains two main steps: electroplating (ECP) and chemical-mechanical polishing (CMP) ECP: deposits Cu on the trenches CMP: removes Cu that overfills the trenches

Great interconnect performance and systematic yield loss are observed after CMP

ECP CMPOpen trenches

5

CMP Process

CMP contains both chemical and mechanical parts Chemically: abrasive slurry dissolves the wafer layer Mechanically: a dynamic polishing head presses pad and wafer

Schematic diagram of CMP polisher

Slurry

Polishing pad

Polishing head

Wafer

6

Post-CMP topography strongly depends on underlying layout pattern densitylayout pattern density

Uneven layout density leads to metal dishing and dielectric erosion after CMP

Layout-Dependent Thickness Variations

Oxide

polishing pad slurry

dielectricmetal

Post-CMPPre-CMP

metal

dielectricdishing erosion

7

Layout Pattern Density Control

wiredummy

Foundries have set density rulesdensity rules and filled dummy dummy featuresfeatures to improve CMP quality

Disadvantages of dummy fills:1. Changes coupling capacitance of interconnects

2. Leads to explosion of mask data, putting heavy burdens to following time-consuming RETs

RoutingRouting considering uniform wire density helps control the layout pattern density

Avoid aggressive post-routing dummy fills

8

Outline

CMP Introduction

Previous WorkPrevious Work



Conclusion

9

Minimum Pin Density Global Routing

Cho et al. [ICCAD’06] selected paths with minimum pin minimum pin density density to reduce maximum wire density in global tiles

Paths with lower pin density tend to have lower wire density and can get much benefit from optimization

p1

p2

2 possible 1-bend ST paths Path a with lower density

S

T

S

T

Select path p1 with lower pin density

p1

10

tdtc

[( / ) ]

1( / )

cost( ) 21 ( / )

t t t t

t t

c d d ct

d c

Wire Density-Driven Cost Function

Li et al. [TCAD’07] set the cost function of a global tile t to guide a wire density-driven global router:

: capacity of t

: demand of t

: parameter of target density (=4 for 25% target density)

cost( )t

1

tdtc

11

Both approaches only consider the wire density insideinside a routing tile

It may incur larger inter-tileinter-tile density difference results in irregular post-CMP thickness variations

Limitations

Post-CMP Thickness

Density = 0.4 Density = 0.1

Need to minimize the density Need to minimize the density difference among global tilesdifference among global tiles

12

Outline

CMP Introduction

Previous Work

Wire-Density Driven Two-Pass Top-Down RoutingWire-Density Driven Two-Pass Top-Down Routing


Conclusion

13

Multilevel Routing

A modern chip may contain billions of transistors and millions of nets

Multilevel routingMultilevel routing has been proposed to handle large-scale designs

Already-routed netTo-be-routed net

coarsening uncoarsening

‧global routing ‧detailed routing

‧failed nets rerouting‧refinement

Λ-shaped multilevel routing

14

high

low

Two-Pass Top-Down Routing Framework

G0

G1

G2

Planarization-aware top-down global routing

11stst Pass Stage Pass Stage

Top-down detailed routing and refinement

22ndnd Pass Stage Pass Stage

Voronoi-diagram based density critical area analysis (CAA)

Prerouting StagePrerouting Stage

uncoarsening

G0

G1

G2

uncoarsening

Density-driven layer assignment and Delaunay-triangulation track assignment

Intermediate StageIntermediate Stage

To-be-routed net Already-routed net

15

Top-Down Routing Approach

1. Planarity is a long-range effect

2. Longer nets shall be planned first greater impacts/determination for density usually hard to predict paths

3. Bottom-up routing easily falls into local optima over density may occur among subregions

?

?

?

Bottom-up routing Over density among subregions

G0

G1

G2

?

16

Density Analysis Prerouting

G0

G1

G2





uncoarsening

G0

G1

G2

uncoarsening




high

low



17

Density Critical Area Analysis (CAA)

Performs density analysis to guide following routing Given a routing instance, we predict density hot spots

based on the pin distributionpin distribution by Voronoi diagramsVoronoi diagrams

18

Voronoi Diagram

The Voronoi diagramVoronoi diagram of a point set decomposes space into non-overlapping Voronoi cellsVoronoi cells

If a point q lies in the Voronoi cell of p, then q would be close to p than other points

qp

19

Observation of Voronoi Diagrams

Non-uniform distribution leads to large area variation among Voronoi cells

Non-uniform distribution Uniform distribution

20

Density Hot Spots Identification

If the Voronoi cell of a pin has more adjacent cells, density hot spots may occur around it

Define pin densitypin density of a pin p as # of adjacent Voronoi cells completely sitting inside a range from p

p

pin density = 3

21

Global Tile Predicted Density

3

2

1

1 2

1

2

21

1

1

Map pin density to global tiles to guide global routing The predicted density of a global tile t:

1 2 2

0 3 1

0 1 0

Pin density Predicted density of global tile

= max{ pin density | pin locates within t }

22

high

low



1st Pass Top-Down Global Routing



uncoarsening

G0

G1

G2

uncoarsening




G0

G1

G2



23

Objectives:

1. Encourage each global tile to satisfy density upper- and lower-bound rules

2. Minimize the density difference among global tiles

Planarization-Aware Global Routing

Post-CMP Thickness

Density = 0.5 Density = 0.1

0.5 0.1

0.1 0.3 0.2

0.4 0.2 0.3

Wire density map

Density = 0.2

0.2

24

td

2

if upper bound

if lower bound upper bound

if lower bound

(2 1) ( )t

t

t

t

ttd

t

d

d

d

dd d

: predicted density of t (prerouting density CAA)

Planarization-Aware Cost Function

Planarization-aware cost of global tile t with density dt:

: positive penalty (> 0)

: average density of tiles around t

: user-define parameter

: negative reward (< 0)

25

G0

G1

G2



high

low



Intermediate Layer/Track Assignment



uncoarsening

G0

G1

G2

uncoarsening




26

Density-Driven Layer Assignment

Goal: to evenly distribute segments to layers Minimizes the panel densitypanel density while balancing the local local

densitydensity of each layer local density: # of segments and obstacles in a column panel density: maximum local density among all columns

Chip layout(aerial view)

Segment

Layer 1 obstacle

Layer 3 obstacle

1234

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2

c1 c3 c4 c5 c6 c7 c8 c9 c10 c11c2Column

Segment

Layer 1 obstacle

Layer 3 obstacle

SegmentSegment

Layer 1 obstacleLayer 1 obstacle


1234

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


1234

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


27

s6

o1

3

3

2

33

4

4

44

4

4

s1 s2

s3

s4s5

o23

11

1

1

33

3

3

s1 s2

s4s5

s6 o2

o1 s3

3

3

2

34

4 4

Density-Driven Layer Partitioning

Builds horizontal constraint graphhorizontal constraint graph HCG(V,E) Node: segment and obstacle Cost of an edge (vi, vj): maximum local density of overlapping

columns between vi and vj

Partitions layer groups by max-cut, k-coloringmax-cut, k-coloring algorithms

123

4

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


123

4

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


28

11

1

1

33

3

3

s1 s2

s4s5

s6 o2

o1 s3

3

3

2

34

4 4

Minimum-Impact Repair Procedure

For the fixed-layer obstacle which is not assigned to the correct layer

Exchanges its layer with the layer of a connected segment whose edge cost is the maximum

11

11

33

33

s1 s2

s4s5

s6 o2

o1 s3

Exchange layer of obstacle O1 with that of S6

29

Density-Driven Layer Assignment Result

Segment

Layer 1 obstacle

Layer 3 obstacle

123

4

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


Segment

Layer 1 obstacle

Layer 3 obstacle

SegmentSegment



123

4

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


123

4

s1

s2

o2

o1

s3

s4

s5

s6

Local density 1 2 3 2 2 2 3 2 4 4 2


Layer 1

1234

s1

s2

o1

s3

Local density 1 1 2 1 1 1 1 1 2 2 0


Segment

Layer 1 obstacle

1234

s1

s2

o1

s3

Local density 1 1 2 1 1 1 1 1 2 2 0


1234

s1

s2

o1

s3

Local density 1 1 2 1 1 1 1 1 2 2 0


Segment

Layer 1 obstacle

SegmentSegment


Layer 3

1234

o2

s4

s5

s6

Local density 0 1 1 1 1 1 2 1 2 2 2


Segment

Layer 3 obstacle

1234

o2

s4

s5

s6

Local density 0 1 1 1 1 1 2 1 2 2 2


1234

o2

s4

s5

s6

Local density 0 1 1 1 1 1 2 1 2 2 2


Segment

Layer 3 obstacle

SegmentSegment


30

Density-Driven Track Assignment

Goal: to keep segments spatially separated in a panel Uses good properties of Delaunay TriangulationDelaunay Triangulation (DT)

Represents each segment by three points, two end points and one center point, and analyzes the DT

Non-uniform segment distribution large area difference among triangles in DT

Non-uniform distribution Uniform distribution

31

u2

u1 u3

b3

b1

s3

s1

Au

A

Ab

1234

1234

1234

u4

b2

o1s2

u2

u1 u3

b3

b1

s3

s1

Au

A

Ab

1234

1234

1234

u4

b2

o1s2

Artificial Segment

Model the density distribution of each neighboring panel into an artificial segmentartificial segment lying on the boundary

Length: the average occupied length per track Center: the center of gravity of all segments and obstacles

Layer 1 obstacleArtificial segmentSegment

u2

u1 u3

b3

b1

s3

s1

Au

A

Ab

1234

1234

1234

u4

b2

o1s2

u2

u1 u3

b3

b1

s3

s1

Au

A

Ab

1234

1234

1234

u4

b2

o1s2

su

sb

32

1( )i i

i

s tl

Delaunay-Triangulation Track Assignment

Define flexibilityflexibility of a segment si, ti: number of assignable tracks for si

li: length of si

Insert segments in the non-decreasing order of flexibility Each segment is assigned to the track that minimizes the

area difference among all triangles of DTs2

1234

o1

sb

su

ξ(s3) = 3+1/8 = 3.125

ξ(s2) = 4+1/1 = 5

ξ(s1) = 4+1/2 = 4.5

s3

s1

33

A Density-Driven Track Assignment Example

1234

o1

s3

ξ(s2) = 4

ξ(s1) = 4.5

s2

1234

o1

s3

ξ(s1) = 4.5

s2

1234

o1

s3s1

sb

su Segment

Artificial segment

Layer 1 obstacle

34

Outline

CMP Introduction

Previous Work


Experimental ResultsExperimental Results

Conclusion

35

Experimental Setting

C++ language with LEDA library on a 1.2 GHz Sun Blade-2000 with 8GB memory

Compared our two-pass, top-down routing system (TTR) with MROR [Li et al., TCAD’07]

Λ-shaped multilevel router considering balanced density

Compared the density-CAA guided global routing of TTR with CMP-aware minimum pin-density global routing [Cho et al., ICCAD’06]

Minimum pin-density global routing + TTR detailed routing

36

Routing Benchmarks

Academic: eleven MCNC benchmarks Industrial: five Faraday benchmarks

Circuit #Layer #Connection #Pin

Mcc1 4 1693 3101

Mcc2 4 7541 25024

Struct 3 3551 5471

Primary1 3 2037 2941

Primary2 3 8197 11226

S5378 3 3124 4818

S9234 3 2774 4260

S13207 3 6995 10776

S15850 3 8321 12793

S38417 3 21035 32344

S38584 3 28177 42931

Circuit #Layer #Connection #Pin

DMA 6 36162 73982

DSP1 6 63495 144872

DSP2 6 36686 144703

RISC1 6 95106 196677

RISC2 6 95099 196670

MCNC benchmarks

Faraday benchmarks

37

Comparison Metric

Comparison is based on the same metric used in the work of MROR [TCAD’07]

#Netmax: maximum # of nets crossing a tile

#Netavg_h: average # of nets horizontally crossing a tile

#Netavg_v: average # of nets vertically crossing a tile

σh: standard deviation of # of nets horizontally crossing a tile

σv: standard deviation of # of nets vertically crossing a tile

Reflects the wire density distribution for a routing result

38

Experimental Results (MCNC)

Time Time Time

(sec) (sec) (sec)

Mcc1 45 9.9 11.3 77.4 41 10.3 11.1 36.1 30 10.3 11.0 33.4

Mcc2 96 18.7 20.9 2714.9 119 20.6 22.2 798.0 87 20.5 22.2 645.0

Struct 7 1.4 1.4 61.4 5 1.2 0.8 66.8 6 1.1 0.8 58.2

Primary1 15 0.7 0.6 69.1 12 0.8 0.7 27.0 6 0.7 0.3 24.3

Primary2 25 2.1 1.9 322.2 22 2.5 1.9 144.0 8 1.8 0.9 131.0

S5378 15 4.4 3.5 4.5 8 2.5 2.4 8.1 9 2.5 2.4 8.2

S9234 14 4.0 2.6 3.2 7 1.7 1.6 5.2 9 1.7 1.6 5.4

S13207 27 9.3 5.9 15.8 13 3.4 3.0 24.8 11 3.3 3.0 24.2

S15850 26 10.3 7.4 23.8 12 4.0 3.8 34.2 13 3.9 3.8 33.5

S38417 23 7.3 4.3 54.2 10 3.0 2.4 62.5 11 2.9 2.4 62.4

S38584 29 9.1 5.8 137.7 16 3.3 3.1 112.0 15 3.3 3.1 112.0

Comp. 1.00 1.00 1.00 1.00 0.68 0.71 0.75 1.01 0.57 0.66 0.64 0.98

TTR (Ours)MROR (TCAD'07)

#Netavg_h#Netmax #Netavg_v

GR (ICCAD'06) + TTR framework

#Netmax #Netavg_v #Netavg_h

Circuit#Netmax #Netavg_v #Netavg_h

All three routers achieved 100% routability TTR reduced

#Netmax by 43% than TCAD’07 and 11% than ICCAD’06

#Netavg_v by 34% than TCAD’07 and 5% than ICCAD’06

#Netavg_h by 36% than TCAD’07 and 11% than ICCAD’06

39

Vertical Wire Crossing of S13207

30

25

20

15

10

5

0

MROR [TCAD’07]

GR [ICCAD’06]+TTR framework

TTR (Ours)

30

25

20

15

10

5

0

30

25

20

15

10

5

0

40

Experimental Results (Faraday)

Time Time

(sec) (sec)

DMA 99.19% 14 3.14 2.77 1.70 1.77 48.8 99.29% 10 3.08 2.70 1.75 1.64 47.0

DSP1 99.11% 11 2.91 2.50 1.95 1.89 124.2 99.18% 10 2.85 2.44 2.24 1.95 117.3

DSP2 99.10% 14 2.78 2.78 1.71 1.92 87.2 99.06% 10 2.72 2.70 1.90 1.91 82.3

RISC1 99.16% 21 3.63 3.79 2.95 3.78 355.3 99.16% 17 3.59 3.73 3.08 3.29 333.4

RISC2 99.23% 21 3.64 3.70 2.55 3.08 297.4 99.19% 13 3.59 3.62 2.77 2.89 280.0

Comp. 99.16% 1.00 1.00 1.00 1.00 1.00 1.00 99.16% 0.75 0.98 0.98 1.08 0.95 0.95

σhRout. σv σh σv

GR (ICCAD'06) + TTR framework

Circuit

TTR (Ours)

#Netavg_hRout. #Netavg_v#Netmax #Netmax#Netavg_h#Netavg_v

MROR [TCAD’07] cannot run designs where pins are distributed between layers 1 and 3

TTR reduced #Netmax by 25% than ICCAD’06

#Netavg_v by 2% than ICCAD’06

#Netavg_h by 2% than ICCAD’06

41

Horizontal Wire Crossing of RISC1

GR [ICCAD’06]+TTR detailed routing

TTR (Ours)

42

Outline

CMP Introduction

Previous Work



ConclusionConclusion

43

Conclusion

Proposed a new full-chip density-driven routing system for CMP variation control1. Voronoi-diagram based density CAA prerouting

2. Planarization-aware top-down global routing

3. Density-driven layer assignment + Delaunay-triangulation based track assignment

4. Top-down detailed routing

Reduced 43% and 11% maximum wire crossing on density tiles and achieved more balanced wire distribution than state-of-the-art previous works

44

Q & A

Thanks for your attention!

Novel Wire Density Driven Full-Chip Routing for CMP Variation Control

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