Nov. 29, 2005 ELEC6970-001 Class Presentation 1 Logic Redesign for Low Power ELEC 6970 Project...

Nov. 29, 2005Nov. 29, 2005 ELEC6970-001 Class PresentationELEC6970-001 Class Presentation 11

Logic Redesign for Logic Redesign for Low PowerLow Power

ELEC 6970 Project PresentationELEC 6970 Project Presentation

By Nitin YogiBy Nitin Yogi


OutlineOutline

Low Power Logic SynthesisLow Power Logic Synthesis Low Power Optimization TechniquesLow Power Optimization Techniques Redundancy InsertionRedundancy Insertion Logic TransformationLogic Transformation Multiplier Cell OptimizationMultiplier Cell Optimization Experimental ResultsExperimental Results Summary and ConclusionSummary and Conclusion What I learnt !What I learnt !


Low Power Logic SynthesisLow Power Logic Synthesis Sources of PowerSources of Power

Dynamic powerDynamic power Signal transitionsSignal transitions

Logic activityLogic activity GlitchesGlitches

Short-circuitShort-circuit StaticStatic

LeakageLeakage Power Power αα Area Area

Method : Area optimized logic synthesisMethod : Area optimized logic synthesis Power Power αα Transistor Leakage and Short-circuit current Transistor Leakage and Short-circuit current

Method : Optimized transistor level design for gatesMethod : Optimized transistor level design for gates Power Power αα Signal Activity of Circuit Signal Activity of Circuit

Method : Low Power Logic SynthesisMethod : Low Power Logic Synthesis


Low Power Optimization techniquesLow Power Optimization techniques

Technology Independent OptimizationTechnology Independent Optimization Algebraic Logic RestructuringAlgebraic Logic Restructuring

Kernel and Cube ExtractionKernel and Cube Extraction Iterative extraction and re-substitution of sub-Iterative extraction and re-substitution of sub-

expressionsexpressions

Post Mapping Structural OptimizationPost Mapping Structural Optimization Redundancy InsertionRedundancy Insertion Logic TransformationsLogic Transformations


Post-mapping Structural OptimizationPost-mapping Structural Optimization Redundancy InsertionRedundancy Insertion

Redundancy is inserted into the circuit to minimize a Redundancy is inserted into the circuit to minimize a cost function. cost function.

3 elements required in the process3 elements required in the process Suitable circuit location for redundancy insertionSuitable circuit location for redundancy insertion Candidate type of redundancyCandidate type of redundancy Cost functionCost function

3 steps involved3 steps involved Identifying candidates for redundancy insertion at a suitable Identifying candidates for redundancy insertion at a suitable

circuit location for minimum cost function.circuit location for minimum cost function. Applying logic transformation to insert redundancyApplying logic transformation to insert redundancy Reducing the circuit by removing other generated Reducing the circuit by removing other generated

redundancies by logic transformation.redundancies by logic transformation.


Post-mapping Structural OptimizationPost-mapping Structural Optimization Finding Circuit Locations for Redundancy InsertionFinding Circuit Locations for Redundancy Insertion

Identify Source and Target locations using don’t care implicationsIdentify Source and Target locations using don’t care implications

A

C

Y

0

0B x

xx

D

x

x

Source location

Possible target location


Candidate Redundancy insertionsCandidate Redundancy insertions Redundancy insertions to input of gates Redundancy insertions to input of gates

Used to reduce signal activity at the output of a Used to reduce signal activity at the output of a gate using another signal.gate using another signal.

Post-mapping Structural OptimizationPost-mapping Structural Optimization

0 1

xx

‘0’ implication don’t care ‘1’ implication don’t care


Post-mapping Structural OptimizationPost-mapping Structural Optimization Gate Insertion:Gate Insertion:


Post-mapping Structural OptimizationPost-mapping Structural Optimization

Circuit Reduction to eliminate unwanted Circuit Reduction to eliminate unwanted redundanciesredundancies

Redundancy identification methods:Redundancy identification methods: ATPG basedATPG based

Use of exhaustive ATPG to find redundant faultsUse of exhaustive ATPG to find redundant faults Redundant faults signify redundant logic Redundant faults signify redundant logic

Fault independentFault independent Controllability and Observability analysis Controllability and Observability analysis


Post-mapping Structural OptimizationPost-mapping Structural Optimization Logic TransformationsLogic Transformations

Permissible function:Permissible function: If all the network primary output If all the network primary output

functions do not change after the functions do not change after the function realized at a signal line function realized at a signal line Li Li is replaced by a function is replaced by a function f f , then the , then the function function f f is called a permissible is called a permissible function for the signal line function for the signal line Li Li ..

Gate SubstitutionGate Substitution Replace a target signal line with the Replace a target signal line with the

candidate signal line having the candidate signal line having the same function.same function.

Inverter InsertionInverter Insertion Replace a target signal line with the Replace a target signal line with the

inverted candidate signal line inverted candidate signal line having the same function.having the same function.


Post-mapping Structural OptimizationPost-mapping Structural Optimization Logic TransformationsLogic Transformations

Eliminate inverters on signals with high activityEliminate inverters on signals with high activity Discourage the implementation of EX-OR gatesDiscourage the implementation of EX-OR gates EX-OR gate example:EX-OR gate example:

Y = AY = A••B + AB + A••BB

= (A= (A••B) B) + (A•B)+ (A•B)

= (A + B) + A= (A + B) + A••BB


Multiplier CellMultiplier Cell

0

0

0

0

0 0 0 0

A0

A1

A2

A3

B3 B2 B1 B0

Y0

Y1

Y2

Y3Y4Y5Y6Y7

Fulladder

B

A

Carry in

Sum output

Sum input

Carry out

Array Cell

Full Adder


Multiplier CellMultiplier Cell

EX-OR

EX-OR


Multiplier Cell Multiplier Cell ModifiedModified

EX-OR

EX-OR


Multiplier Cell Multiplier Cell Modified - 2Modified - 2


Multiplier Cell Multiplier Cell Leonardo (delay optimized)Leonardo (delay optimized)


Multiplier Cell Multiplier Cell Leonardo (area optimized)Leonardo (area optimized)


Experimental ResultsExperimental ResultsMultiplier CellMultiplier Cell

Design and simulation detailsDesign and simulation details Design Entry tool: Design ArchitectDesign Entry tool: Design Architect Simulation tool : EldoSimulation tool : Eldo

(timing and power analysis) (timing and power analysis) Technology library: tsmc 0.18um (VTechnology library: tsmc 0.18um (VDDDD = 1.8V) = 1.8V)

Input Vectors: Input Vectors: Inputs: frequencies in multiples of 2Inputs: frequencies in multiples of 2 Output transitions generated:Output transitions generated:

Sum Out (Sout) : 25Sum Out (Sout) : 25 Carry Out (Cout) : 12 Carry Out (Cout) : 12


Multiplier Cell ResultsMultiplier Cell Results

Unopt.Unopt. Opt.Opt. Leo_AreaLeo_Area Leo_DelayLeo_Delay

Static PowerStatic Power 367.04 pW367.04 pW 201.93 pW201.93 pW 168.94 pW168.94 pW 194.28 pW194.28 pW

Dyn. PowerDyn. Power 27.08 uW27.08 uW 17.39 uW17.39 uW 20.83 uW20.83 uW 21.28 uW21.28 uW

TTdelaydelay

(A/B=>Sout)(A/B=>Sout)

Avg.Avg. 276.13 ps276.13 ps 287.77 ps287.77 ps 225.85 ps225.85 ps 189.16 ps189.16 ps

PeakPeak 328.45 ps328.45 ps 345.74 ps345.74 ps 257.23 ps257.23 ps 255.17 ps255.17 ps

TTdelaydelay

(A/B=>Cout)(A/B=>Cout)

Avg.Avg. 226.08 ps226.08 ps 173.77 ps173.77 ps 80.59 ps80.59 ps 90.16 ps90.16 ps

PeakPeak 237.07 ps237.07 ps 177.02 ps177.02 ps 108.62 ps108.62 ps 96.60 ps96.60 ps


Summary and ConclusionSummary and Conclusion Post Mapped Structural Optimization techniques for Low Post Mapped Structural Optimization techniques for Low

Power prove to be effective.Power prove to be effective. Percentage reduction in power consumption of optimized Percentage reduction in power consumption of optimized

Multiplier Cell as compared to:Multiplier Cell as compared to: Unoptimized cell: Unoptimized cell: ~35.7%~35.7% Leonardo generated: ~15%Leonardo generated: ~15%

Percentage increase in critical path delay of optimized Percentage increase in critical path delay of optimized Multiplier Cell as compared to:Multiplier Cell as compared to: Unoptimized cell: Unoptimized cell: ~35.7%~35.7% Leonardo generated: ~50%Leonardo generated: ~50%

Effective cost functions to include delay constraints will Effective cost functions to include delay constraints will enhance the quality of the circuits.enhance the quality of the circuits.

Effective algorithms for structural optimization.Effective algorithms for structural optimization. 32 x 32 bit Multiplier power optimization.32 x 32 bit Multiplier power optimization.


What I learnt !What I learnt !

Low Power Logic SynthesisLow Power Logic Synthesis Logic synthesisLogic synthesis Logic optimizationLogic optimization Redundancy insertion, identification and Redundancy insertion, identification and

eliminationelimination Use of EDA tools for timing and power analysisUse of EDA tools for timing and power analysis Start your projects early! (wish I would have)Start your projects early! (wish I would have) Large patience required with EDA tools!Large patience required with EDA tools!


ReferencesReferences1.1. S. Devadas, S. Malik, “A Survey of Optimization Techniques Targeting Low Power S. Devadas, S. Malik, “A Survey of Optimization Techniques Targeting Low Power

VLSI Circuits,” Annual ACM IEEE Design Automation Conference, Proceedings VLSI Circuits,” Annual ACM IEEE Design Automation Conference, Proceedings of the 32nd ACM/IEEE conference on Design automation, San Francisco, of the 32nd ACM/IEEE conference on Design automation, San Francisco, California, United States, pp. 242 – 247, 1995California, United States, pp. 242 – 247, 1995

2.2. Pradhan D.K., Chatterjee M., Swarna M.V., Kunz W, “Gate-level synthesis for low-Pradhan D.K., Chatterjee M., Swarna M.V., Kunz W, “Gate-level synthesis for low-power using new transformations,” power using new transformations,” Low Power Electronics and Design, 1996, Low Power Electronics and Design, 1996, International Symposium on, International Symposium on, pp 297-300pp 297-300, , Aug 1996Aug 1996

3.3. Wang Q., Vrudhula S.B.K.,Wang Q., Vrudhula S.B.K., “Multi-level logic optimization for low power using “Multi-level logic optimization for low power using local logic transformations,” local logic transformations,” Computer-Aided Design, 1996. ICCAD-96., 1996 Computer-Aided Design, 1996. ICCAD-96., 1996 IEEE/ACM International Conference onIEEE/ACM International Conference on10-14 Nov. 1996 Page(s):270 – 27710-14 Nov. 1996 Page(s):270 – 277

4.4. Shih-Chieh Chang, Marek-Sadowska M,Shih-Chieh Chang, Marek-Sadowska M, “Perturb And Simplify: Multi-level “Perturb And Simplify: Multi-level Boolean Network Optimizer,” Boolean Network Optimizer,” Computer-Aided Design, 1994., IEEE/ACM Computer-Aided Design, 1994., IEEE/ACM International Conference on November 6-10, 1994 Page(s):2 - 5 International Conference on November 6-10, 1994 Page(s):2 - 5

5.5. R. V. Menon, S. Chennupati, N. K. Samala, D. Radhakrishnan and B. Izadi, “Power R. V. Menon, S. Chennupati, N. K. Samala, D. Radhakrishnan and B. Izadi, “Power Optimized Combinational Logic Design,” Optimized Combinational Logic Design,” Proceedings of the International Proceedings of the International Conference on Embedded Systems and ApplicationsConference on Embedded Systems and Applications, pp. 223 - 227, June 2003. , pp. 223 - 227, June 2003.

6.6. W. Kunz, “W. Kunz, “Multi-level Logic Optimization By Implication Analysis,” Multi-level Logic Optimization By Implication Analysis,” Computer-Computer-Aided Design, 1994., IEEE/ACM International Conference on November 6-10, Aided Design, 1994., IEEE/ACM International Conference on November 6-10, 1994 Page(s):6 - 13 1994 Page(s):6 - 13


ReferencesReferences7.7. Roy K., Prasad S.C., “Roy K., Prasad S.C., “Circuit activity based logic synthesis for low power Circuit activity based logic synthesis for low power

reliable operations,” reliable operations,” Very Large Scale Integration (VLSI) Systems, IEEE Very Large Scale Integration (VLSI) Systems, IEEE Transactions onTransactions onVolume 1, Issue 4, Dec. 1993, pp 503 – 513Volume 1, Issue 4, Dec. 1993, pp 503 – 513

8.8. Ki-Wook Kim, Ting Ting Hwang, Liu C.L., Sung-Mo Kang, “Ki-Wook Kim, Ting Ting Hwang, Liu C.L., Sung-Mo Kang, “Logic Logic transformation for low power synthesis,” transformation for low power synthesis,” Design, Automation and Test in Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings, pp158 – 162, March 1999Europe Conference and Exhibition 1999. Proceedings, pp158 – 162, March 1999

9.9. Brzozowski I., Kos A.,Brzozowski I., Kos A., “Minimisation of power consumption in digital “Minimisation of power consumption in digital integrated circuits by reduction of switching activity,” integrated circuits by reduction of switching activity,” EUROMICRO EUROMICRO Conference, 1999. Proceedings. 25Conference, 1999. Proceedings. 25thth Volume 1, 8-10 Sept. 1999 Page(s):376 - 380 Volume 1, 8-10 Sept. 1999 Page(s):376 - 380 vol.1 M. A. Iyer and M. Abramovici, “Low-Cost Redundancy Identification for vol.1 M. A. Iyer and M. Abramovici, “Low-Cost Redundancy Identification for Combinational Circuits,” in Combinational Circuits,” in Proc. 7th International Conf. on VLSI design, Proc. 7th International Conf. on VLSI design, pp. 315-pp. 315-317, January 1994.317, January 1994.

10.10. V.D. Agrawal; M.L. Bushnell, Qing Lin, “Redundancy identification using V.D. Agrawal; M.L. Bushnell, Qing Lin, “Redundancy identification using transitive closure,” Test Symposium, 1996., Proceedings of the Fifth Asian 20-22 transitive closure,” Test Symposium, 1996., Proceedings of the Fifth Asian 20-22 Nov. 1996 Page(s):4 – 9Nov. 1996 Page(s):4 – 9

11.11. Abramovici M., Iyer M.A., “One-Pass Redundancy Identification and Removal,” Abramovici M., Iyer M.A., “One-Pass Redundancy Identification and Removal,” Test Conference, 1992. Proceedings., InternationalTest Conference, 1992. Proceedings., InternationalSept. 20-24 1992 Page(s):807 Sept. 20-24 1992 Page(s):807


Thank You!Thank You!

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Nov. 29, 2005 ELEC6970-001 Class Presentation 1 Logic Redesign for Low Power ELEC 6970 Project...

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