Notes4_1

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1 of 13 ECE 357Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum,

Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Chapter 4, The Microarchitecture Level

4.1 An Example Microarchitecture 203

4.2 An Example ISA: Ijvm 2184.3 An Example Implementation 227

4.4 Design Of The Microarchitecture Level 243

4.5 Improving Performance 264

4.6 Examples Of The Microarchitecture Level 283

4.7 Summary 298

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Integer JAVA Virtual Machine

Processor Block Diagram

This is a limited version of a hardware implementation to execute the JAVA programminglanguage.

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Overview

THE IJVM hardware architecture follows JAVA language implementation features that result in

a very distinct implementation. Once you understand the philosophy of how a JAVA executes,

then the implementation hardware becomes more logical.

The initial architecture uses multiple clock cycles to execute each JAVA OPCODE instruction.For each instruction, there is a machine fetch to get the instruction followed by a sequence of

microinstructions that perform the operation (decode and access operands, execute, and write

back the result).

The Data Path

PC Program Counter: Access Data

in Method Area

MBR Memory Branch Register:

Instruction and InstructionParameter 8-bit register

MAR Memory Address Register:Address for external data

memory space

MDR Memory Data Register: Data

input and output to external

memory

SP Stack Pointer: Address pointer

to the top of the system stack

LV Local Variable: Address pointer

to the bottom of the localvariable frame

CPP Constant Pool Pointer: Pointer

to the bottom of the constant

pool

TOS Top Of Stack: The data value at

the top of the stack

OPC Old PC: A scratch or temporary

register typically used for

branching and the temporarystorage of old PC values in

computations

H Holding: A temporary register

for holding one of the two ALU

operands

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Data Movement using Registers

Loading a Register

1) MAR provide an address to receive data

2) MDR inputs data3) MDR data is placed on the B bus

4) B Bus Data passed through ALU to the C Bus

5) C Bus Data is written into a register

Saving a Register1) Register data is placed on the B bus


3) C Bus Data is written into the MDR

4) MDR data is written at the MAR memory addressNote: The MAR must hold the correct address value

Executing a one operand instruction

1) Register data is placed on the B bus2) B Bus Data is modified by the ALU based on the ALU control and output to the C Bus3) C Bus Data is written into the appropriate register

Executing a two operand instruction1) Register data is placed on the B bus


3) C Bus Data is written into the H register4) Register data is placed on the B bus

5) A & B Bus Data is modified by the ALU based on the ALU control

6) C Bus Data is written into the appropriate register

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Arithmetic Logic Units (ALU)

Cascadeable 1-Bit ALU:AND, OR, INV, Binary Added with Cin and Cout

Ripple ALU

An 8-bit ALU based on 1-bit ALU building blocks

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Ripple ALU Functions (Your extra homework assignment)

Number of possible functions: 5 control bits (2^5) plus a carry bit (x2 for adder functions)

One-operand instructions do not enable the A Bus input:

B, NOT(B), B+1, B-1, 0, 1, -1

Two-operand instructions enable both the A and B Bus inputs:

A+B, A+B+1, B-A, A AND B, A OR B

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Data Path Timing

Text Book Latch Based Concept

Alternate Super-Synchronous Design Timing Cycle

w x y z

Possible Super-Synchronous Operation

w Control signal propagation to the components in the CPU

x A and B Bus propagation times

y ALU and Shifter input to output propagation times

z C Bus propagation time and register set-up time

The subcycles are asynchronous propagation times (if something can complete faster it does, but

time is allocated to operate slower or at the worst case timing)

The subcycles are implicit in how signals have to flow not explicit clock or gate periods

The super-synchronous operation is consistent with our previous mux-register design!

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Data Path Propagation

w

x

y

z

Clock rising edge

w

x

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Memory Operation (Two ports, one for data and one for instructions)

Data Memory Port

MAR Memory Address Register: Address for external data memory space

MDR Memory Data Register: Data input and output to external memory

32-bit Registers internal word access and word addressing

MAR addressing of 32-bit words using an external Byte wide Memory Addressing Bus

Note: all external data memory is assumed to be perfectly aligned on 4-Byte boundaries.

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Instruction Memory Port

PC Program Counter: Access Data in Method Area (32-bit register)

MBR Memory Branch Register: Instruction and Instruction Parameter (8-bit register)

Byte can be read with or without sign extension ( a signed or unsigned integer).

The instructions consist of 8-bit pieces that are addresses by the PC and loaded into the MBR.

Reading memories (Cycle latency delays)

RD#

Add Bus

CPU CLK

Mem Data

MDR

MAR

Data Bus

@MAR Available

External Memory Read Latency

Notice that the data isnt available during the first cycle.

For writing, data can be written on the same cycle as a write command.

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Reading followed by write memories (Cycle latency delays)

RD#

Add Bus

CPU CLK

Mem Data

MDR

MAR

Data Bus

@MAR Available

WR#

MDR

Read Latency Write Latency

MAR

Data Bus

RD#

Add Bus

CPU CLK

Mem Data

MDR

MAR1

@MAR1

WR#

Read Latency

MAR2

@MAR2

MAR3

@MAR2

MAR4

MDR1

MDR1

MAR5

@MAR1 @MAR2 @MAR5

@MAR5

can only write

what was read

Write

Latency

Write

Latency

Read Latency

Read Latency

MDR1 must be the value @MAR2 or else the read at MAR2 con not be used!

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Microinstructions

Now that the functions have been defined, what about the control.

Multiple clock cycles execute each instruction, what occurs on each and every clock cycle is

defined by a microcontroller with a microPC and a microinstruction!

Additional Register Definitions

MPC orPC MicroProgram Counter: Internal microcode address register

MIR orIR Microinstruction Register: Internal instruction used to control the IJVM

IJVM Block Diagram

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Elements of the microinstructions:

Operands what is the operand that goes on the B Bus Execution what ALU and shift operation is to occur Results where are the execution results to be stored from the C Bus

and does it involve memory operations

Program Control where is the next instruction determinedMIR Content

The MIR Fields: B Bus, ALU & Shift, C Bus and Ext. Mem., Next MPC

MIR bit width is: 9+3 = 12-bit next instruction with 8+9+3+4 = 24-bits data paths. Total 36-bits!

Encoded B-Bus Selection with a 4:16 Decoder

B-Bus Instruction

Field

B-Bus Register Selected

0000 MDR

0001 PC0010 MBR (signed)

0011 MBRU (unsigned)

0100 SP

0101 LV

0110 CPP

0111 TOS

1000 OPC

1001 Unassigned

1010 Unassigned

1011 Unassigned

1100 Unassigned

1101 Unassigned

1110 Unassigned

1111 Unassigned

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