note7

Electronics III

- Power Dissipation in CMOS digital circuits- Optimization of Chain of InvertersOpt at o o C a o e te s

1

CMOS Power Dissipation

Trade offs

Power Timing Area

CMOS power includes static and dynamic components

g

p y p

dynamicstatictotal

DDDD

PPPVIP

+==

CMOS Dynamic Power DissipationDynamic Switching CurrentsDynamic Switching Currents

1. Dynamic Capacitive charging currentT

avg dttitvTP

0)()(1

= ( ) outLT

Tout

outLoutDD

Tavg dtdt

dVCVdtdt

dVCVVT

P

22

2/

2/

0

1

+

+= V

outVoutoutDD

Lavg

VVVVTCP DD

DD

22

02

0

2

1

|2

|2

=

VDD+

avgDDDclkDDLDDLavg IVfVCVCTP ,

221 ===

lkDDLswingL

LD fVCVCdVCI === PD

VoutPU

Vout

+

-+ +

-clkDDLLavgD fVCtdtCI ===,

I design factorsPull up: Pull down:

-

Iswitch design factors

Reduce CL Vswing VDD fclkt= 0 T/2 Vout =0 VDD

t = T/2 T Vout = VDD 0

CMOS Dynamic Power DissipationSwitching Activity FactorSwitching Activity Factor

Activity factor

HOWEVER Most gates do not switch (toggle) at each clock edge

102 = fVCP DDLdynamic

Pdynamic = 01 CL VDD2 fclkWhere 0 1 is the activity factor


Activity factor

= probability that an output transition 0 1 takes place = p0p1 p0 = probability output = 0

p1 = probability output switches to 1

Determined from to truth table of specific gateDetermined from to truth table of specific gateAssuming equal probability for each combination of inputExample: 2 input NOR/NANDgates

A B A + B A . B

0 0 1 10 1 0 11 0 0 1

NOR2: p0=3/4, p1=1/4, = 3/16NAND2: p0=1/4, p1=3/4, = 3/16 1 0 0 1

1 1 0 0 p0 , p1 ,


Activity factorAssuming equal probability for each input combination

E l 2 i t XOR t Example: 3 input NOR gate:Example: 2 input XOR gate: p0=0.5, p1=0.5 = 0.25

Example: 3 input NOR gate: p0=7/8, p1=1/8 = 7/64A B C A B CA B XOR

0 0 00 1 1

A B C A+B+C

0 0 0 10 0 1 00 1 1

1 0 11 1 0

0 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 0 1 01 1 0 01 1 1 0

3 input NAND gate: p0 = 1/8, p1=7/8 = 7/64

CMOS Dynamic Power DissipationShort Circuit (Crowbar)Short Circuit (Crowbar)

Short circuit current when at No load PDN and PUN are both conducting PDN and PUN are both conducting during HL and LH transitions

Duration depends on input rise and fall fallscavgscf

risescavgscr

tIA

tIA

,,

,,

==

times

tsc = time for VDD-IVtpI > VI > Vtnf lli

avgscfallscrisesc

sc

ttt

IT

ttI ,

,,

+=+=

avgscsc

sc

fallscrisescsc

ITtI

ttt

,

,,

=+=

T

clkDDavgscscDDavgscsc

sc

VCtIdVCI

fVItVITtP ,,

== IscIsc

AfAr ISC,av

DDscavgscsc

fC

VCItAssume

VCtIdt

CI

2, =

==ttsc.rise tsc.fall

clkDDscsc fVCP2= where CSC is an equivalent short circuit capacitance

defined for analogy with dynamic power

CMOS Dynamic Power DissipationShort Circuit (Crowbar Contd )Short Circuit (Crowbar, Contd..)

VIP

L

clkDDscsc

DDscsc

CCfVCP

VIP2

===

Another activity factor

clkDDLclkDDLscclkDDLdynamic

clkDDLscsc

Lscsc

fVCfVCfVCP

fVCP

CC

22210

2

=+==

Another activity factor

clkDDLclkDDLscclkDDLdynamic fff10

includes activity and short circuit effectsMinimum ISC : Rise and fall edges of input as sharp (minimum tsc) and as equal as possible.BUT This requires large currents in previous stage large transistors large CL large dynamic powerTrade off between dynamic power of previous stage and short circuit power of next stage

CMOS Dynamic Power DissipationGlitchesGlitches

GlitchesExtra output transitions due to asynchronous arrival of multiple inputs

Leads to power consumption

Minimized by managing input arrival time by adjusting - path delays- gate delaysg y- right selection of gate and

logic architecture

SPICE:0.25 m adjust the inputs of a 2 Input NOR gate until a glitch appears at the g goutput during a transient analysis. What are the conditions for the glitch to occur .

CMOS Static Power DissipationStatic CurrentsStatic Currents

2 St ti C t2. Static Currents

Subthreshold Channel leakage current in "off" devicesSubthreshold Channel leakage current in "off" devices

Junction Reverse bias current through pn junctions

Standby (DC) Current through normally on devices (Pseudo-NMOS)( )

( ) VIIIP ++( ) DDstandbyjunctionldsubthreshostatic VIIIP ++=

CMOS Static Power DissipationSt ti C tStatic Currents

1. Subthreshold leakage current Isub N+ N+P

Most important static current loss

N NPSource Drain

NMOSBipolar action due to close proximity of source and drainForward Bias of source junction Diffusion of minority carriers

in the channel (base) region( )[ ] ( )( )TkqVTnkVVVqssub BDSBoffsetTgs eeII // 1= ( ) g

To reduce I design factorsTo reduce Isub design factors1. Larger VT trade off between ION and IOFF2 Adj V d i i ( l )2. Adjust VT during operation (complex)

3. Reduce VDS increase channel length 4. Add series R or Qs to PUN/ PDN to fragment VDS5. Reduce temperature

CMOS Static Power DissipationSt ti C tStatic Currents

2. Junction leakage current Ipn2. Junction leakage current Ipn

( )( ) ( )( )11 //0 == TkqVSpnTkqVpn BbiasBbias eJAeII ppNegligible in most digital circuits

To reduce Ipn design factor

Reduce junction area of source and drain (bottom and sidewall)

Standby Current IStandby Current IDC

DC current in pseudo-NMOS gates when Vout = VOL

Total Static Power Pstat= Ileak VDD= (Isub+ Ipn+ IDC)VDD

Power - Delay Trade-offsGoal

Reduce power and delay Minimize Power-delay product (PDP)PDP = Paverage x tp = Average power x average delayAssume: Dominant source of dissipation P = CVDD2fAssume: Dominant source of dissipation Paverage CVDD f

Propagation delay = 1/2f

PDP = CV 2f/2f = CV 2/2 PDP = CVDD2f/2f = CVDD2/2 PDP = Energy per switching operation (per toggle)

2)()()()(

2

00010,DD

outout

V

outout

outcCCVdvtvCdttv

dtdvCdttvtiE DD ====

Energy stored in C after a charging operation

2000, dt Design factors for PDP reduction

Capacitance, Voltage swing, Supply voltage

PDP obscures effects of design modification delay

Power - Delay Trade offsEnergy Delay ProductEnergy Delay Product

Energy-Delay Product EDPEnergy Delay Product EDPNew metrics that show delay

EDP ( ti d l )2EDP = average power x (average propagation delay)2.

ptPDPEDP =

s

CVVCIVCt

dtdVCI

==

e

d

v

a

l

u

e Energy

Energy.delay

( )TDDDD

satp VVK

CVIVCt

322

=

o

r

m

a

l

i

z

e

gy y

( )TDDDD

VVKVCEDP

2 2

32

=

N

o

V

Delay

ToptDDDD

VVVEDP

230 , ==

VDD

CMOS Inverter DelayHodges and Jackson, Chapter 6, Section 6.5.1, 6.5.2

Input (Gate) capacitance

Cin = CG(Wn+Wp) = CG(Wn + 2Wn)

VDD

in G n p G n n= 3 CGWn

Reff = Reqn (Ln/Wn)VV

Tinv = Reff Cin = Reqn (Ln/Wn) CG (3 Wn) = 3 ReqnCGLn

No load: Capacitance at Output =

VoutCout

VinCselfCin

No load: Capacitance at Output = inverter own capacitances at drain (CL = Cself)

With load: Load capacitance = Cself + Cout capacitance due toWith load: Load capacitance Cself Cout capacitance due to a) input capacitance of load (Fan-out) gates at output b) wiring capacitance

CL = Cself + Cout

CMOS Inverter Delay

Delay time constant Td

Td = Reff CL = Reff[Cout + Cself] = ReffCin [Cout/Cin + Cself/Cin] = Ti [C t/Ci + i ] Tinv [Cout/Cin + in]

Cout/Cin = f = fan out ratio (electrical effort) = C /C depends on the gate layoutVDD

in = Cself/Cin depends on the gate layout

VoutVin

CoutCselfCin

Sizing Inverter for optimum delay

Required to drive a very large capacitance using inverter (s) To reduce the delay the effective resistance should be very small Solution: Solution:1. Use one very big inverter with a very small resistance

- It will have a very high input capacitance shifting the problem the previous stage

- Its drain capacitance will also increase and adds to the load self loading capacitance

In Out

Cl oa

d

i

n

g

CLCin high C

s

e

l

f

Chain of Inverters

2. Use a chain of inverters to minimize the delay from input to output Design issue sizing of each inverteroutput Design issue sizing of each inverter

In Out

CLC1N1 j-1 j j+1

Total delay Td = Tinv [Ci+1/Ci + inv] = Tinv[3CGWi+1/(3CGWi) + inv]Consider delay of two consecutive inverters

i=1

N N

i=1

Consider delay of two consecutive inverters

Dj = Tinv(Wj/(Wj-1 + inv) + Tinv(Wj+1/Wj + inv)To obtain the minimum delay derive D wrt W and equate to zeroTo obtain the minimum delay derive Dj wrt Wj and equate to zero

dDj/dWj = Tinv (1/Wj-1) Tinv (Wj+1/Wj2) = 0

Wj/Wj-1 = Wj+1/Wj Wj = VWj+1Wj-1)

Optimimum Chain of Inverters2. Use a chain of inverters to minimize the delay from input to

output Design issue sizing of each inverterp g g

In OutIn Out

CL= fN CinCinfN-11 f f2 fN-2

Wj/Wj-1 = Cj/Cj-1 = Cout/Cin of inverter j = fj = f = constant for all inverters

Each inverter is doing the same electrical effort

CL/Cin = CL/CN x CN/CN-1 x CN-1/CN-2 X..X C2/Cin= fN = F = Total electric effort of chain

At optimum sizing each gate delay = Tinv(Cj/Cj-1 + in) Minimum path delay = NTi (f + i ) = NTi (F1/N + i ) Minimum path delay = NTinv(f + in) = NTinv(F + in)

Optimum Chain of Inverters

Example: assume 3 inverters

In Out

C 8CC 1f f 2

CL = 8C1C11

3f = 8 = 2

Rewrite N in terms of fan-out/stage f

fN = CL/C1 N = ln (CL/C1)ln fNeed to find N that minimizesTd

T = NT [ + (C /C )1/N] = T ln(C /C ) [ in + f ]Td = NTinv [in + (CL/C1)1/N] = Tinv ln(CL/C1) ln f[ in ]


To get minimum delay derive Td wrt to f

dTd/df = Tinv ln (CL/C1) x = 0ln f 1 in/f

(ln f )2(ln f )fopt = exp (1 + in/fopt) 5

If in = 0 (i.e. Cself = 0) f = e 4

4.5

N = ln (CL/C1]

If in = 13.5fopt fopt = 3.6 4in

f = 3.6 N = 0.78 . ln (CL/C1] 2.5

3

0 0.5 1 1.5 2 2.5 3inv


D

e

l

a

y

f=

e

)

(f = 3.6

D

(

6)f

Practically in 1 Curve very flat for f 2M t d l d f 4 ( i b )Most common used value used f = 4 (magic number)


Td = N Tinv (in + F ), F = CL/C1N

F (i = 1)

Unbuffered= (1+F)

Two Stage Chain = 2(1+F0.5)

Opt. Inverter Chain = N.(1+3.6)(in 1) (1+F) ( ) ( )

10 11 8.3 8.3

100 101 22 16 5100 101 22 16.5

1,000 1001 65 24.8

10 000 10 001 202 33 1

Impressive speed-ups with optimized cascaded

10,000 10,001 202 33.1

p p p p

inverter chain for very large capacitive loads.


Example of Inverter (Buffer) Staging (Assume in = 1)

1N f tp

CL = 64 C1C1 = 1

8

1 64 65

CL = 64 C1C1 = 1

1 8

2 8 18

C 64 CC 1

1 4 16

3 4 15Optimum

CL = 64 C1C1 = 1

1 2 8 8 22 6

3 4 15

CL = 64 C1C1 = 1

1 2.8 22.64 2.8 15.3

Optimum Chain of Inverters: Energy vs Delay

C fCin f2Cin f

3Cindriver

To be driven

CL = f4Cin

Cin To be driven

During every switching cycle all inverters are switching

Overhead capacitances

g y g y gEnergy drawn from supply = CjV2DDDelay decreases but area and energyDelay decreases but area and energy increases with number of inverters

Trade-off (Compromise)Give up some delay for less energy / areaenergy / area

N tp,minEmin

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