Non Redundant Data Cache
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U U P P C C Non Redundant Data Cache Carlos Molina, Carles Aliagas and Montse García Universitat Rovira i Virgili – Tarragona, Spain {cmolina,caliagas,mgarciaf}@etse.urv.es Antonio González and Jordi Tubella Universitat Politècnica de Catalunya – Barcelona, Spain {antonio,jordit}@ac.upc.es ISLPED´03, Seoul (Korea) - August 25-27, 2003
description
ISLPED´03, Seoul (Korea) - August 25-27, 2003. Non Redundant Data Cache. Carlos Molina, Carles Aliagas and Montse García Universitat Rovira i Virgili – Tarragona, Spain {cmolina,caliagas,mgarciaf}@etse.urv.es Antonio González and Jordi Tubella - PowerPoint PPT Presentation
Transcript of Non Redundant Data Cache
UU PP CC
Non Redundant Data CacheNon Redundant Data Cache
Carlos Molina, Carles Aliagas and Montse García
Universitat Rovira i Virgili – Tarragona, Spain
{cmolina,caliagas,mgarciaf}@etse.urv.es
Antonio González and Jordi Tubella
Universitat Politècnica de Catalunya – Barcelona, Spain
{antonio,jordit}@ac.upc.es
ISLPED´03, Seoul (Korea) - August 25-27, 2003
MotivationMotivation
Caches spend close to 50% of total die area
L1 Dcache L1 Icache L2 Cache Total Area
Pentium 4 2 % 3 % 20 % 25 %
Mips R20k 23 % 26 % none 54 %
Crusoe 5400 10 % 9 % 27 % 46 %
Power 4 2 % 1 % 50 % 53 %
Alpha 21364 4 % 3 % 36 % 43 %
Caches may be responsible for 10% to 20% of total power dissipated by a
processor
Data Value ReplicationData Value Replication
0123456789
10
0 10 20 30 40 50 60 70 80 90
Data Value ReplicationData Value Replication
0102030405060708090
100
0 10 20 30 40 50 60 70 80 90
ObjectiveObjective
To reduce die area
But mantaining miss ratio
Latency
Energy consumption
Conventional CacheConventional Cache
If (Value A==Value B) then Value Redundancy
Value A
Value B
12345
12345
Tag X
Tag Y
Non Redundant Data Cache (1)Non Redundant Data Cache (1)
Pointer TablePointer Table Value TableValue Table
12345
12345
Tag X
Tag Y
12345
Die Area ReductionDie Area Reduction
Tag X
Tag Y
Additional Hardware: PointersAdditional Hardware: PointersAdditional Hardware: CountersAdditional Hardware: Counters
12345 count
Data Value InliningData Value Inlining
Some values can be represented with a small
number of bits (Narrow Values)
Narrow values can be inlined into pointer area
Simple sign extension is applied
Benefits enlarges logical capacity of VT reduces latency reduces power dissipation
Tag X
Tag Y
10 count
Non Redundant Data Cache (2)Non Redundant Data Cache (2)
Pointer TablePointer Table Value TableValue Table
count
Tag X
Tag Y
10
10
Simulation EnviromentSimulation Enviroment
Simulators Cacti tool version 3.0 (Static Analysis)
Alpha version of SimpleScalar 3.0 (Dynamic Analysis)
Benchmarks Spec2000
Maximum Optimization Level DEC C & F77 compilers with -non_shared -O5
Statistics Collected for 1 billion instructions Skipping initializations
Inlining PerformanceInlining Performance
0
10
20
30
40
50
60
70
256K
B
512K
B1M
B2M
B4M
B
256K
B
512K
B1M
B2M
B4M
B
256K
B
512K
B1M
B2M
B4M
B
Miss Ratio
Hit Inlined
Miss Inlined
Die AreaDie Area
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
Base VT50 VT30 VT20
512 KB
cm2
Counter
Data
Pointer
Tag
LatencyLatency
00,20,40,60,8
11,21,41,61,8
2
Base VT50 VT30 VT20
512 KB
ns
Tag
Data
Effective
Pointer
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
Base VT50 VT30 VT20
512 KB
nJ
Hit
Hit Label
Hit VT
Miss
Effective
Energy ConsumptionEnergy Consumption
Miss Rate vs Die AreaMiss Rate vs Die Area
15
20
25
30
35
40
45
50
1 10 100
100%
50%
30%
20%
| | |
0,1 0,5 1,0
cm2
Mis
s R
atio
%
%
%
%
%
%
%
%
ResultsResults
Diea AreaReduction
EnergyConsumption
Reduction
Access TimeReduction
Number of MissesIncrement
VT50 VT30 VT20 VT50 VT30 VT20 VT50 VT30 VT20 VT50 VT30 VT20
AMEAN 32% 47% 55% 14% 21% 27% 25% 33% 37% 5% 12% 18%
Caches ranging from 256 KB to 4 MB
ConclusionsConclusions
High degree of value replication is present in
conventional caches
Non redundant data cache
Data value inlining
Die area reduction
Energy consumption reduction
Access time reduction
Minor miss ratio increasing
UU PP CC
Non Redundant Data CacheNon Redundant Data Cache
Carlos Molina, Carles Aliagas and Montse García
Universitat Rovira i Virgili – Tarragona, Spain
{cmolina,caliagas,mgarciaf}@etse.urv.es
Antonio González and Jordi Tubella
Universitat Politècnica de Catalunya – Barcelona, Spain
{antonio,jordit}@ac.upc.es
ISLPED´03, Seoul (Korea) - August 25-27, 2003
