Noise Canceling in 1-D Data: Presentation #2 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana...
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Transcript of Noise Canceling in 1-D Data: Presentation #2 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana...
![Page 1: Noise Canceling in 1-D Data: Presentation #2 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Jan 24, 2005 Architecture.](https://reader035.fdocuments.in/reader035/viewer/2022081513/56649d415503460f94a1b3d5/html5/thumbnails/1.jpg)
Noise Canceling in 1-D Data: Presentation #2
Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar
M2
Jan 24, 2005Architecture Proposal
Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware
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Status
• Design proposal (Done)• Architecture proposal:
– Final algorithm description (Done)– High level simulation in C (Done)– Mapping of algorithm into hardware
(Done) – Behavioral Verilog simulation and test
bench (Debugging)• To be done:
– Floor plan– Structural Verilog– Layout– Spice simulation
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Design Decisions
• Use 16-bit floating point numbers approximating up to 10-5
• Choose M=1 because target applications do not usually have higher harmonics
• Change integer multipliers and adders to floating point
• Make a bigger ROM table for the sine and cosine functions
![Page 4: Noise Canceling in 1-D Data: Presentation #2 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Jan 24, 2005 Architecture.](https://reader035.fdocuments.in/reader035/viewer/2022081513/56649d415503460f94a1b3d5/html5/thumbnails/4.jpg)
Algorithm Description
• Goal: To minimize noise• Algorithm: Based on adaptive
filtering depending on signal weights
• Pseudo-code:i) Take the input signal and model it
using Fourier Transformii) For each sample, model it by
approximating the weight constant and feeding it back to the next sample
iii) Each sample model is then subtracted from the original input signal to monitor the error
![Page 5: Noise Canceling in 1-D Data: Presentation #2 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Jan 24, 2005 Architecture.](https://reader035.fdocuments.in/reader035/viewer/2022081513/56649d415503460f94a1b3d5/html5/thumbnails/5.jpg)
Original Flow-chart
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Revised Flow-chart
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The Micron Experiment
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High Level Simulation in C
Simulation of input before the modification
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Simulation of input file after the modification
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Error comparison
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Mapping of Algorithm into Hardware
• Major functional components:– Floating point multipliers (FPM)– Floating point adders (FPA)– 16-bit Registers (Reg)– ROM – sine, cosine
– SRAM – μ, μ0, ω0
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FP
A
w0 RO
M
FP
M
cos
FP
A
sin
FP
M
x2
FP
S
out
input
FP
MShifter
FP
M
FP
M
x1
error
mu
sumw0
FP
AF
PA
w1w2
Block Diagram
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Behavioral Verilogalways@(datum)begin
w1=0;w2=0;offset = 10;in = datum - offset;sumw0 = sumw0 + w0;x1 = sin(sumw0);x2 = cos(sumw0);
/* output = truncated Fourier Series*/out = 0;out = w1 * x1 + w2 * x2;
/* calculate error*/e = in - out;
/*update amplitude weights */temp = 2*mu*e;w1 = w1 + temp*x1;w2 = w2 + temp*x2;
end
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Revised Transistor Count
Part Transistors
16-bit FPA 5x500 = 2500
16-bit FPM 5x4000 = 20000
SRAM 500
ROM 1600
Registers 7x16x14 = 1568
Total ≈ 26168
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Challenges…
• Timing issues– Need to reuse hardware
(multipliers)– Clock skew – Pipelined architecture to
increase speed and throughput
• SRAM implementation• ROM implementation• Transistor count is too high
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Questions?