Semiconductor Memories

Prof. Kaushik Roy

@ Purdue Univ.

References:

Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey © UCB

Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed.,

N. H. E. Weste and K. Eshraghian

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Chapter Overview

Memory Classification

Memory Architectures

The Memory Core

Periphery

Reliability

Case Studies

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Semiconductor Memory Classification

Read-Write Memory Non-Volatile

Read-Write

Memory

Read-Only Memory

EPROM

E 2 PROM

FLASH

Random

Access

Non-Random

Access

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO

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Memory Architecture: Decoders

Word 0

Word 1

Word 2

Word N 2 2

Word N 2 1

Storage cell

M bits M bits

N

words

S 0

S 1

S 2

S N 2 2

A 0

A 1

A K 2 1

K 5 log 2 N

S N 2 1

Word 0

Word 1

Word 2

Word N 2 2

Word N 2 1

Storage cell

S 0

Input-Output ( M bits)

Intuitive architecture for N x M memory

Too many select signals:

N words == N select signals K = log 2 N

Decoder reduces the number of select signals

Input-Output ( M bits)

Decoder

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Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing to rail-to-rail amplitude

Selects appropriate word

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Hierarchical Memory Architecture

Advantages:

1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

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Read-Only Memory Cells

WL

BL

WL

BL

1 WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2

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MOS OR ROM

WL [0]

V DD

BL [0]

WL [1]

WL [2]

WL [3]

V bias

BL [1]

Pull-down loads

BL [2] BL [3]

V DD

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MOS NOR ROM

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

V DD

BL [1]

Pull-up devices

BL [2] BL [3]

GND

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Precharged MOS NOR ROM

PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

V DD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pre f

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MOS NOR ROM Layout

Programmming using the

Active Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5l x 7l)

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MOS NOR ROM Layout

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (11l x 7l)

Programmming using

the Contact Layer Only

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MOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

V DD

Pull-up devices

BL [3] BL [2] BL [1] BL [0]

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MOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8l x 7l)

Programmming using

the Metal-1 Layer Only

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NAND ROM Layout

Cell (5l x 6l)

Polysilicon

Threshold-altering

implant

Metal1 on Diffusion

Programmming using

Implants Only

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Non-Volatile Memories

The Floating-gate transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n + n +_ p

t ox

t ox

Device cross-section Schematic symbol

G

S

D

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Floating-Gate Transistor Programming

0 V

2 5 V 0 V

D S

Removing programming

voltage leaves charge trapped

5 V

2 2.5 V 5 V

D S

Programming results in higher V T .

20 V

10 V 5 V 20 V

D S

Avalanche injection

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FLOTOX EEPROM

Floating gate

Source

Substrate p

Gate

Drain

n 1 n 1

FLOTOX transistor Fowler-Nordheim

I-V characteristic

20 – 30 nm

10 nm

-10 V

10 V

I

V GD

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EEPROM Cell

WL

BL

V DD

Absolute threshold control

is hard

Unprogrammed transistor

might be depletion

2 transistor cell

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Flash EEPROM

Control gate

erasure

p- substrate

Floating gate

Thin tunneling oxide

n 1 source n 1 drain programming

Many other options …

© Digital Integrated Circuits2nd Memories

Cross-sections of NVM cells

EPROM Flash Courtesy Intel

© Digital Integrated Circuits2nd Memories

Basic Operations in a NOR Flash Memory―

Erase

© Digital Integrated Circuits2nd Memories

Basic Operations in a NOR Flash Memory―

Write

© Digital Integrated Circuits2nd Memories

Basic Operations in a NOR Flash Memory―

Read

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Characteristics of State-of-the-art NVM

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Read-Write Memories (RAM)

STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is applied

Large (6 transistors/cell)

Fast

Differential

Periodic refresh required

Small (1-3 transistors/cell)

Slower

Single Ended

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6-transistor CMOS SRAM Cell

WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

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CMOS SRAM Analysis (Read) WL

BL

V DD

M 5

M 6

M 4

M 1 V DD V DD V DD

BL

Q = 1 Q = 0

C bit C bit

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CMOS SRAM Analysis (Read)

0

0

0.2

0.4

0.6

0.8

1

1.2

0.5

Voltage rise [V]

1 1.2 1.5 2

Cell Ratio (CR)

2.5 3

Voltage R

ise (

V)

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CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0

Q = 1

M 1

M 4

M 5

M 6

V DD

V DD

WL

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6T-SRAM — Layout

VDD

GND

Q Q

WL

BL BL

M1 M3

M4 M2

M5 M6

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Resistance-load SRAM Cell

Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem

M 3

R L R L

V DD

WL

Q Q

M 1 M 2

M 4

BL BL

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SRAM Characteristics

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3-Transistor DRAM Cell

No constraints on device ratios

Reads are non-destructive

Value stored at node X when writing a “1” = V WWL -V Tn

WWL

BL 1

M 1 X

M 3

M 2

C S

BL 2

RWL

V DD

V DD 2 V T

D V V DD 2 V T BL 2

BL 1

X

RWL

WWL

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3T-DRAM — Layout

BL2 BL1 GND

RWL

WWL

M3

M2

M1

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1-Transistor DRAM Cell

Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

D V BL V PRE – V BIT V PRE – C S

C S C BL + ------------ = = V

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DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due

to charge redistribution read-out.

DRAM memory cells are single ended in contrast to

SRAM cells.

The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correct

operation.

Unlike 3T cell, 1T cell requires presence of an extra

capacitance that must be explicitly included in the design.

When writing a “1” into a DRAM cell, a threshold voltage

is lost. This charge loss can be circumvented by

bootstrapping the word lines to a higher value than VDD

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Sense Amp Operation

D V (1)

V (1)

V (0)

t

V PRE

V BL

Sense amp activated Word line activated

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1-T DRAM Cell

Uses Polysilicon-Diffusion Capacitance

Expensive in Area

M 1 word line

Diffused bit line

Polysilicon gate

Polysilicon plate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO 2

Field Oxide n + n +

Inversion layer induced by plate bias

Poly

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SEM of poly-diffusion capacitor 1T-DRAM

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Advanced 1T DRAM Cells

Cell Plate Si

Capacitor Insulator

Storage Node Poly

2nd Field Oxide

Refilling Poly

Si Substrate

Trench Cell Stacked-capacitor Cell

Capacitor dielectric layer Cell plate Word line

Insulating Layer

Isolation Transfer gate

Storage electrode

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Periphery

Decoders

Sense Amplifiers

Input/Output Buffers

Control / Timing Circuitry

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Row Decoders

Collection of 2M complex logic gates

Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder

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Hierarchical Decoders

• • •

• • •

A 2 A 2

A 2 A 3

WL 0

A 2 A 3 A 2 A 3 A 2 A 3

A 3 A 3 A 0 A 0

A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1

A 1 A 1

WL 1

Multi-stage implementation improves performance

NAND decoder using

2-input pre-decoders

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Dynamic Decoders

Precharge devices

V DD f

GND

WL 3

WL 2

WL 1

WL 0

A 0 A 0

GND

A 1 A 1 f

WL 3

A 0 A 0 A 1 A 1

WL 2

WL 1

WL 0

V DD

V DD

V DD

V DD

2-input NOR decoder 2-input NAND decoder

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4-input pass-transistor based column

decoder

Advantages: speed (tpd does not add to overall memory access time)

Only one extra transistor in signal path

Disadvantage: Large transistor count

2-input NOR decoder

A 0

S 0

BL 0 BL 1 BL 2 BL 3

A 1

S 1

S 2

S 3

D

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4-to-1 tree based column decoder

Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders

buffers progressive sizing combination of tree and pass transistor approaches

Solutions:

BL 0 BL 1 BL 2 BL 3

D

A 0

A 0

A 1

A 1

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Decoder for circular shift-register

V DD

V DD

R

WL 0

V DD

f

f f

f

V DD

R

WL 1

V DD

f

f f

f

V DD

R

WL 2

V DD

f

f f

f • • •

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Sense Amplifiers

t p

C D V

I av

---------------- =

make D V as small

as possible

small large

Idea: Use Sense Amplifer

output input

s.a. small transition

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Differential Sense Amplifier

Directly applicable to

SRAMs

M 4

M 1

M 5

M 3

M 2

V DD

bit bit

SE

Out y

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Differential Sensing ― SRAM VDD

VDD

VDD

VDD

BL

EQ

Diff.SenseAmp

(a) SRAM sensing scheme (b) two stage differential amplifier

SRAM cell i

WL i

2xx

VDD

Output

BL

PC

M3

M1

M5

M2

M4

x

SE

SE

SE

Output

SE

x2x 2x

y

y

2y

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Latch-Based Sense Amplifier (DRAM)

Initialized in its meta-stable point with EQ

Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.

EQ

V DD

BL BL

SE

SE

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Reliability and Yield

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Noise Sources in 1T DRam

C cross

electrode

a -particles

leakage C S

WL

BL substrate Adjacent BL

C WBL

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Open Bit-line Architecture —Cross Coupling

Sense Amplifier C

WL 1

BL

C BL

C WBL C WBL

C C

WL 0

C

C BL

C C

WL D WL D WL 0 WL 1

BL

EQ

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Folded-Bitline Architecture

SenseAmplifier

C

WL 1

CWBL

CWBL

C

WL 0 WL 0 WL D

CC

WL 1

CC

WL D

BL CBL

BL CBL

EQ

x

x

y

y

…

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Transposed-Bitline Architecture

SA

Ccross

(a) Straightforward bit-line routing

(b) Transposed bit-line architecture

BL 9

BL

BL

BL 99

SA

Ccross

BL 9

BL

BL

BL 99

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Alpha-particles (or Neutrons)

1 Particle ~ 1 Million Carriers

WL

BL

V DD

n 1

a -particle

SiO 2 1

1

1 1 1

1 2

2 2

2 2

2

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Redundancy

Memory Array

Column Decoder

Row Decoder

Redundant rows

Redundant columns

Row Address

Column Address

Fuse Bank

:

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Error-Correcting Codes

Example: Hamming Codes

with

e.g. B3 Wrong

1

1

0

= 3

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Redundancy and Error Correction

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Sources of Power Dissipation in

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PERIPHERY

ROW DEC

selected

non-selected

CHIP

COLUMN DEC

nC DE V INT f

mC DE V INT f

C PT V INT f

I DCP

ARRAY

m

n

m(n 2 1)i hld

mi act

V DD

V SS

I DD 5 S C i D V i f 1S I DCP

From [Itoh00]

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Programmable Logic Array

GND GND GND GND

GND

GND

GND

V DD

V DD

X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2

AND-plane OR-plane

Pseudo-NMOS PLA

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Dynamic PLA

GND

GND V DD

V DD

X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2

AND f

AND f

OR f

OR f

AND-plane OR-plane

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Semiconductor Memory Trends

(updated)

From [Itoh01]

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Trends in Memory Cell Area

From [Itoh01]

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Semiconductor Memory Trends

Technology feature size for different SRAM generations