Nios Hardware Development Tutorial for the Nios Development Board
Nios TM 2.0
description
Transcript of Nios TM 2.0
1© 2001
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NiosNiosTMTM 2.0 2.0
Altera’s embedded Processor Solution
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Nios Embedded ProcessorNios Embedded Processor Configurable Soft Core
Embedded Processor Optimized for Altera®
Programmable Logic Device (PLD) Architecture
32-Bit RISC Architecture License & Royalty Free Over 6,000 Kits Sold
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Nios Device SupportNios Device Support
Low CostLow Density
ACEX® 1K
Low CostLow-to-Medium Density
FLEX® 10K
High-Speed Differential I/OLow-to-High Density
APEX 20KEAPEX 20KC
High-Speed Differential I/OVery High Density
APEX™ II
High SpeedMulti-Processor Systems (ARM + Nios)Medium-to-High Density
ARM®-Based Excalibur
Very High-Speed I/O with Clock-Data Recovery (CDR)Medium Density
Mercury™
Highest Speed (0.13-µm, All-Layer Copper) DSP BlocksVery High Speed I/O Very High Density
Stratix™
FeaturesFeaturesDevice FamilyDevice Family
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SOPCSOPCBuilderBuilder
Combines Altera Strengths Combines Altera Strengths
Robust IP Offerings Processor DSP Communication
Bus Interface
HardwareDevelopment Tools Quartus® II LeonardoSpectrum™ ModelSim®
Development Boards
High-Density, High-Performance Devices Stratix APEX II Mercury ARM-Based
Excalibur
Software Development Tools Compiler Debugger RTOS
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SOPC_BUILDERSOPC_BUILDER
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A powerful friendly GUI A powerful friendly GUI
SimulationEnvironment
HardwareEnvironment
SoftwareEnvironment
HardwareTeam
SoftwareTeam
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The NiosThe NiosTMTM System Architecture System Architecture
UART nUART 0
Timer nTimer 0
SPI nSPI 0
GPIO nGPIO 0
DMA nDMA 0
MemoryInterface
User-DefinedInterface
OCD
AM
BA
/ A
VA
LON
STRIPE
@decoder
InterruptControler
Wait StateGeneration
Data InMultiplexer
DynamicBus Sizing
Port Interface
AVALON (Bus Peripheral Module)
Arbiter
Arbiter
Arbiter
Arbiter
UserTri_StateDevice
NiosFlash
NiosSRAM
Tri-StateBridge
Arbiter
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SOPC Builder Ready ComponentsSOPC Builder Ready Components
The List Keeps Growing . . .
Nios™ Embedded Processor
ARM922T™Processor
ARM®-to-Nios Bridge (AMBA AHB-to-Avalon)
On-Chip ROMOn-Chip RAM
16550S UARTWatchdog10/100 Ethernet
FLASHCAN 2.0TimerInterface to User Logic
SRAMSPIGPIO
SSRAMUSB 2.0PCI
SDRAMUSB 1.1DMA
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A Lego's like systemA Lego's like systemThe 2.0 CPU core
PeripheralsAvailableOptions
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A modular generationA modular generation
Software Environment
Hardware EnvironmentNetlist Generation
Simulation Environment
Sources for the Synthesis and simulation are available in both VHDL and verilog languages.
All PLD families supported
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NiosNiosTMTM
Hardware Description1- The Core,2- Custom Instruction3- Multi-Mastering
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NiosNiosTMTM processor Features processor Features 1/21/2 32-Bits or 16-Bits RISC Architecture
5 Stage Pipeline Fully-Synchronous Interface Same 16-bits instruction Set for both Data Path sizes.
Windowed Register File Configurable to 512 Registers. Fast Context Switching.
Integrated Interrupt Controller 64 Vectored Interrupts.
Selectable Reset Address
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NiosNiosTMTM processor Features processor Features 2/22/2 Dynamic Bus Sizing mechanism
Arithmetic's functions for the ALU. Fixed Barrel-Shifter that executes all shift instructions in 2 clock cycles,
regardless of the shift-distance. MSTEP multiplier or 16x16 Bits multiplier.
Optimized Data Processing Custom CPU Instructions >2X Acceleration (e.g. MAC, MP3, Bit Swap)
Optimized Data Flow Simultaneous Multi-master Bus Capability Gbps Throughput
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Nios RISC Processor Block DiagramNios RISC Processor Block Diagram Standard RISC Components Fully-Synchronous Interface Native Verilog Native VHDL
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Optional FIFO, Memory, Other Logic
Nios System Module
Extends Nios Instruction Set Up to 5 Instructions
System Builder: Adds User Logic to Nios ALU Assigns Op-Code Generates C & Assembly
Macros
Profiler Tools.
Custom Instruction Block DiagramCustom Instruction Block Diagram
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Direct Memory Access (DMA) Processor Waits For Bus During DMA
System CPU(Master 1)
DMA Arbitor
DMA(Master 2)
System Bus
I/O1
I/O2 Data
Memory
DMA Bus ArbiterBottleneck
Arbiter Determines Which Master Has Access To Shared
Bus
ProgramMemory
Masters
Slaves
Traditional Data Flow for Multi-MastersTraditional Data Flow for Multi-Masters
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Master 1(Nios CPU)
I/O1Program
Memory
Arbiter
DataMemory
1
Master 2(100Base-T)
I D
I/O2
Avalon Bus Avalon Bus
Multiple ArbitrationSchemes Round Robin Priority Based
Masters
Slaves
Simultaneous Multi-Master Avalon BusSimultaneous Multi-Master Avalon Bus
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Multi-Master Avalon
Simultaneous Multi-Master BusSimultaneous Multi-Master Bus
Master 1(Nios CPU)
I/O1Program
Memory
Arbiter
DataMemory
1
Master 2(100Base-T)
Master n(100Base-T)
I D
Arbiter
DataMemory
n
I/O2
Avalon Bus Avalon Bus Avalon Bus
Masters
Slaves
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Simultaneous Multi-Master BusSimultaneous Multi-Master Bus
Master 1(Nios CPU)
Arbiter
DataMemory
1
Master 2(100Base-T)
Master n(100Base-T)
I D
Fetch Code Receive Packets Send PacketsAvalon Bus Avalon Bus
Arbiter
DataMemory
n
Avalon Bus
I/O1Program
Memory
I/O2
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DMA Peripheral supportDMA Peripheral support
Master 1(Nios CPU)
I/O1Program
Memory
Arbiter
DataMemory
1
Master 2(SPI)
I D
I/O2
Avalon Bus Avalon Bus
DMA
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SOPC Builder Design FlowSOPC Builder Design Flow
Define SystemCPU
PeripheralsMemory
User Logic
Generate
FinishedSystem
SignalTapSignalTap™™Logic AnalysisLogic Analysis
Simulate
Application Application HardwareHardware Debug/Profile
Application Software
HardwareHardwareHDLHDL
SimulationSimulation
SoftwareHeader File
Custom LibraryOS Kernel
Download Download
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HDL SimulationHDL Simulation
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Memory Device Simulation ModelsMemory Device Simulation Models Applies to the following Nios Memories
On Chip Memory (ROM or RAM) SRAM (one or two IDT71V016 chips) Flash Memory
Source files (*.c & *.s) are compiled.Data files (*.mif & *.srec) are convertedFile is used in raw format
Useful for non-standard build eg nios-build –cc –O0 hello.c
String is used in raw format
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UART SimulationUART Simulation UART rx and tx transmissions are echoed to ModelSim
Console
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RTL SimulationRTL Simulation Nios SOPC Builder Automatically creates simulation
model plus ModelSim Project Testbench Simulation Scripts Formatted Wave Window
Start ModelSim
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32-BitNios
Processor
SDRAMController
PIO
User-Defined Interface
NiosFlash
NiosSRAMIncluded
Not Included
Address (32)
Read
Write
Data In (32)
Data Out (32)
IRQ
IRQ #(6)
Address (32)
Data (32)
Avalon B
us
Nios Processor
Nios TestBenchNios TestBench
Tri-State
Bridge
UART Timer
On ChipROM
On ChipRAM
Nios32 BitRAM
UserTri_StateDevice
SPI
User-DefinedPeripheral
SDRAM
User Device
User Device
User Device
User Peripheral
Clock
Reset
User Device
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Simulation ScriptsSimulation Scripts When ModelSim is started from the SOPC Builder a
set-up script is run automatically which creates aliases for simulation scripts
The set up script can be run independently as follows: do setup_sim.do
Simulation Scripts ss Compiles HDL source code and loads design cc Rebuilds memory contents based on software code
Includes changes since Nios generation
ww Opens Wave window with “useful” signalsWill have to add user signals
hh Displays help message describing scripts
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Wave WindowWave Window Adds UART and CPU signals by default
CPU Opcodes are decoded and displayed to help trace software execution
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Nios Debugging SolutionsNios Debugging Solutions
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Nios Debug SolutionsNios Debug Solutions
External Memory Daughter Card for Use as Software Trace Capture Buffer
Debugger ModuleMicrotronix
IDE with Integrated Support for Nios On-Chip Debug Module - Hardware Breakpoints & Processor Trace
Arriba!Viosoft
Interface to Nios On-Chip Debug ModuleHardware Breakpoints & Processor Trace
Tracelink *Altera
GDB / Insight *
ProductProduct
Software Debugger Redhat
DescriptionDescriptionProviderProvider
* Included in Excalibur Development Kit Featuring Nios Processor
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Red Hat GNU Debugger (GDB)Red Hat GNU Debugger (GDB) Run Control Breakpoints, Watchpoints, Catchpoints Stack Frame Analysis List & Search Source Files Examine Memory, Constants, Variables Disassemble Machine Code Examine Expressions Using C / C++
Operators
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Red Hat Insight DebuggerRed Hat Insight Debugger Graphical User Interface for GDB Windows
Source Stack Register Memory Watch Expression Local Variables Breakpoints Console
Function Browser
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Altera TracelinkAltera Tracelink Baseline Support for Nios Processor Ver. 2.0 On-Chip Debug &
Software Trace Capabilities Captures Instructions and Data Executing in Nios CPU
Up to 1.2 Million Instructions Captures Trace Data at Full System Speed Uses External Trace Memory Debugger Module
Available from Microtronix
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Nios System Module
Hardware for TraceHardware for Trace Enable On-Chip Debug Logic in SOPC Builder Connect Nios OCD Ports to External Memory on Debugger Module
UART
Other…
ProgramMemory
Sim
ulta
neou
sM
ulti-
Mas
ter
Ava
lon
Bus
OCD
NiosNiosCPUCPU
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NiosNiosTMTM Ethernet Ethernet Development Kit Development Kit (NEDK)(NEDK)
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Nios Ethernet Development KitNios Ethernet Development Kit Supports Wide Range of Applications
Factory Floor Automation Basic Ethernet Connectivity Internet Upgradeable Hardware
Supports All PLD Families
Development Board External 10Mbyte MAC/Phy Support for 2 Ports
Software Included TCP/IP Stack
Reference Design Hardware (Quartus™ Project) Software (Web Server Application)
Price $495
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Linux Development Kit, Linux Development Kit, by Microtronixby Microtronix
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What do you get in the LDK box?What do you get in the LDK box? µCLinux kernel source code
Three daughter boards to enable Linux development on NDK board Memory Expansion: SDRAM & flash OS Support: Real-time Clock & IDE interface Ethernet Connectivity: NEDK daughter card Serial Y-cable for debug
Software & reference application Web server Linux command shell µCLibC & Kernel open source
Hardware reference design Linux works out of the box, no Quartus compile
necessary
Open Source. No licensing fees. No Royalties.
List Price: $2,495
Operating SystemSupport Board
EthernetConnectivity BoardMemory Expansion Board
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Ver 1.0
PCI32 Nios TargetPCI32 Nios TargetMegaCore FunctionMegaCore Function
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PCI32 Nios Target PCI32 Nios Target MegaCore® FunctionMegaCore® Function PCI Interface to Nios via Avalon™ Bus Bridge Nios System Builder Interface Behavioural Simulation Models PCI Testbench for PCI32 Nios Target Core Low-Level Driver Routines in C Source Code for Nios
Embedded Processor Reference Design for Use with Nios Embedded Processor Complete Documentation
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Nios Operating System Nios Operating System (OS) Support(OS) Support
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Nios™ OS / RTOS SupportNios™ OS / RTOS Support
Open-Source OSµCLinuxMicrotronix
KROS
Nucleus PLUS
ProductProduct
Small-Footprint, Royalty-Free, POSIX-Compliant RTOS
Shugyo Design
Tool to Convert pSOS / VxWorks Applications to Nucleus PLUS
Mapusoft Technologies
Royalty-Free, Source-Available RTOSAccelerated Technology
DescriptionDescriptionProviderProvider
OSChanger
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Nucleus PLUSNucleus PLUS Multi-Tasking Real-Time Kernel Priority, Pre-Emptive Scheduler Inter-Task Communication
Pipes, Queues, Mailboxes Inter-Task Synchronization
Semaphores, Signals, Events Memory Management
Fixed or Variable Dynamic Creation/Deletion of All Objects
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uCLinuxuCLinux Linux Development Kit
Software Linux Kernel & uClibc Library – Nios™ Port Nios Linux Driver Support 70+ Applications 30-Day Installation Support
Hardware 10BaseT Ethernet Card Operating System Support Board
CompactFlash Connector Real-Time Clock IDE Interface
SDRAM/Flash Expansion Board
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To add or set up the Software Components, you need to go to the More “[cpu module]” Settings Tab.
The Software Components section on this page will look a lot like the System Contents page (first image) but with software instead of hardware components. The functionality is the same.
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The first of several pages will show up. All the typical options for configuring the kernel are presented as a list of radio buttons and/or checkboxes.
Once the settings are finished, they are saved and ready to be used during the compile process. The final screen will present the “Microtronix Make Console”.
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Since this is a new project, there is no actual source tree for us to compile. The source code repository files (included with the Microtronix Software Component) need to be copied.
The files are copied by clicking the “Copy Files” button.
Assuming this is cpu component “nios_0”, the source tree will be copied to the “Altera Projects\Excalibur\nios_0\uClinux” directory.
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Once the Copy Files button has been pressed, a small console will pop up and begin the copying of files. The “Make Dependencies” button will now be enabled and ready for use.
After the copying is done, pressing the Make Dependencies button will cause a “make clean” command to be executed followed by the “make dep”.
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Once finished, the file “linux.srec” will be ready for you to upload to your Excalibur Board.
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KROSKROS
Real-Time Operating System Features
Tiny Footprint, 16K to 64K POSIX Interface GNU Compiler Support Supports Altera Nios CPU
Advantages Low Cost Source Code Provided Royalty Free
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KROS LatencyKROS Latency POSIX 1c compliant About 6K foot print Based on a very simple Nios Variation (UART & Timer) The WVALID register have to be modified Latency values:
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RoadmapRoadmap
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SOPC Builder RoadmapSOPC Builder Roadmap
SOPC Builder 2.5 SOPC Builder 2.6 SOPC Builder 2.7 Multiple Clock Domains Software Acceleration
Libraries
Stand-Alone Tool Excalibur ARM Support AHB Support
Released with Nios 2.0 Multi-Master Buses
with Slave-Side Arbitration
Avalon Support
2002Q2 Q3Q1 Q4
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Nios Roadmap 2002Nios Roadmap 2002
Q1 2002 Q2 2002 Q3 2002Q1 2002 Q2 2002 Q3 2002 Q4 2002Q4 2002
Nios 2.0 Smaller / Faster CPU Simultaneous Multi-Master Custom Instruction On-Chip Debug SOPC Builder 2.5
Nios 2.1 Stratix Support Quartus II LE Ver 2.0 Bug Fixes
NIOS Ethernet Kit 10/100 MAC/PHY SMSC LAN91C111 Updated Protocol Lib Interrupt Support
SOPC Builder 2.6 Included in Quartus II 2.1 Consistent ARM / Nios Nios OpenCore Plus
Nios 2.2 Instruction Cache JTAG UART
SOPC Builder 2.7 Web Update Multi-Clock Domain Software Components
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Options RoadmapOptions Roadmap
1. Ethernet links 10Mbits available now. 10/100Mbits on going to be released (WW18)
• Port plugs library to new HW
2. µClinux Available for Nios 1.1 – Kernel 2.0 The port for Nios 2.0 is on going – Kernel 2.4 (WW25)
• The LDK has been included in the SOPC_BUILDER.Evaluation CD will be shipped with Nios2.1 update kits.
• Upgrade subscription for $2000.
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SummarizeSummarize
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A Step Beyond...A Step Beyond... NiosTM has a more than 1 year lead on the competition
The NiosTM 1.0 has been released in July 2000. The NiosTM 2.1 released with Stratix support. More than 6000 kits sold all over the world. In many market places, NiosTM is become the flexible solution.
A WYSIWYG (WWhat YYou SSelect IIs WWhat YYou GGet) hardware solution Parameterize the Core and built your peripheral image. All ATERA PLD devices supported Royalty free. No obsolescence.
A complete SW, HW development tools set. Development Tools, Existing Flows Development Board, target debug support. Application demos, Real-Time Operating Systems.
Advanced Training Sessions available
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Nios 2.0 Systems Overview.Nios 2.0 Systems Overview.
Family CPU Features LEs / ESBs MHz Device
ACEX 1K Nios 16-bits1K Internal ROM, 32K External SRAM, 16K External FLASH
1 Timer, 1 UART, 8 INs, 8 OUTs 1400 / 2 30MHz (-3)50MHz (-1) 1K30
Nios 32-bits1K Internal ROM, 256K External SRAM, 1M Extenal FLASH
1 Timer, 1 UART, 8 INs, 8 OUTS 2600 / 8 22MHz (-3)46MHz(-1) 1K100
APEX 20KE Nios 16-bits1K Internal ROM, 32K External SRAM, 16K External FLASH
1 Timer, 1 UART, 32 INs, 32 OUTs 1700 / 7 46MHz (-3)75MHz(-1)
20K100E
Nios 32-bits1K Internal ROM, 256K External SRAM, 1M Extenal FLASH
1 Timer, 1 UART, 8 INs, 8 OUTS 2360 / 13 46MHz(-3)70MHz(-1) 20K100E
1K Internal ROM, 256K External SRAM, 1M Extenal FLASH1 Timer, 1 UART, 8 INs, 8 OUTS
DMA, Ethernet 10Mbits3100 / 13
38MHz(-3)60MHz(-1) 20K100E
APEX 20KC Nios 16-bits1K Internal ROM, 32K External SRAM, 16K External FLASH
1 Timer, 1 UART, 32 INs, 32 OUTs 1700 / 7 52MHz(-9)80MHz(-7) 20K200C
Nios 32-bits1K Internal ROM, 6K Internal RAM, 256K External SRAM,
1M Extenal FLASH, 512Mbits SDRAM3 Timers, 2 UARTs, 32 INs, 32 OUTS
DMA, SDRAM Ctrl
5400 / 3534MHz(-9)49MHz(-7) 20K400C
APEX II Nios 32-bits 1K Internal ROM, 256K External SRAM, 1M Extenal FLASH1 Timer, 2 UARTs, 8 INs, 8 OUTS
85MHz(-5) 2A15
1K Internal ROM, 6K Internal RAM, 256K External SRAM, 1M Extenal FLASH, 512Mbits SDRAM
3 Timers, 2 UARTs, 32 INs, 32 OUTSDMA, SDRAM Ctrl
5400 / 2036MHz(-9)49MHz(-5) 2A15