New random inverter control technique for common mode voltage mitigation of motor drives

Y.S. Lai

Abstract: The purpose of the paper is to present a new inverter control technique which not only mitigates the common mode voltage for motor drives but also sigrufkantly reduces the calculations required for high switchng frequency control, in comparison with the conventional space vector modulation technique. Moreover, it is demonstrated that the presented technique improves the quality of inverter control by randomising the inverter switching frequency, thereby spreading the first dominant harmonic cluster which contributes to the noise. Experimental results derived from a microprocessor-based experimental drive system are presented to confirm the theoretical analysis.

List of principal symbols

FR

h

N

Nc p.u. pk

R B SA = active switching states of inverter control,

SB = active switching states of inverter control,

= inverter switching states y = 0, 1, 2, ..., 7, e.g.

= frequency ratio; ratio of modulatingkanier

= frequency of fundamental voltage (modulating

= number of half carrier periods between two

= number of commutations of power devices = per unit, base voltage = 0.5 V,, = constant for Park transform, Pk = d(Z3) = random bit, either 0 or 1

signals

signal)

samples

either (loo), (010) or (001)

either (110), (011) or (101)

S, = (OOl), S7 = (1 1 l), etc.

= half carrier period = 0.5 T,

SY

Tk = kth sampling point Tz TA, T B = active vector times allocated to switching

states (loo), (010) or (001) and (110), (011) or (I Ol) , respectively

To, T7 = zero voltage vector times allocated to switch- ing states (000) and (1 1 l), respectively

VA, VB = active voltage vector related to switching states SA and SB, respectively

v c o m = common mode voltage Vdc+, V& = voltages of positive and negative DC-link rails,

respectively vDC

v,*

= DC link voltage; Vdc+ - Vd; = reference voltage vector at the sampled instant

0 IEE, 1999 IEE Proceedings online no. 19990 108 DOL 10.1049/epa: 19990 108 Paper first received 24th August and in revised form 23rd December 1998 The author is with the Department of Electrical Engineering, National Taipei University of Technology, 1, Sec. 3. Chung-Hsiao E. Rd., Taipei, 106, Taiwan, Republic of China

= voltage vector related to switching state S,, y = 0, 1, ...) 7

VY

1 Introduction

It is well known that the random pulse-width modulation techniques reduce the annoyed noise and electromagnetic interference (EMI) by randomising the inverter switching frequency, thereby spreading the first dominant harmonic cluster over a wide frequency range. A comprehensive review of the random PWM techniques can be found in [l]. One of the most promising approaches has been proposed by the author [24] whch generates nondetenninistic spec- trum by randomising the switching patterns without invok- ing any modifications to the sampling and modulation processes, and therefore can be incorporated into existing inverter-controlled drive systems.

However, these random techniques [ 1 4 1 and conven- tional space vector modulation technique [5] result in a sig- nificant common mode which contributes to common mode current. It has been shown that the common mode current of a three-phase inverter system associated with common mode voltage causes fault activation of current detection circuits [6], undesired electromagnetic interference (EMI) [7], and damage to motor bearings for motor appli- cations. A number of techniques using common mode choke [SI and filter [6, 91 to mitigate the common mode voltage (current) in the inverter-fed drives have been reported.

Furthermore, recent developments in high frequency power devices offer the possibility of developing high fre- quency inverter control techniques. However, the computa- tion burden imposed on the digital microprocessor for inverter control increases as the switching frequency increases. Although a dedicated digital signal processor or high performance microprocessor can be a solution to hgh switching frequency inverter control, it becomes a challenge to seek for a cost-effective solution to ths issue.

To overcome the issues of inverter control as addressed previously in this Section, a new inverter control technique which sigtllfcantly mitigates the common mode voltage for motor drives applications, randomises the inverter switch- ing frequency and dramatically reduces the calculations required for high switching frequency control, is presented

289 IEE Proc.-Electr. Power Appl., Vol. 146, No. 3, May 1999

in the paper. Experimental results are presented to confirm the theoretical analysis and developments.

a

sA=ool sB=lol Fig. 1 S l S 6 denote sections 1 4 , respectively

Defmitwm ofswitching states for SVM technique

2 Theory

2. I Conventional inverter control technique Fig. 1 shows the definition of switching states and the asso- ciated voltage vectors of inverter control. It is worthy of note that there are eight switching states; six of them, (loo), (010) and (OOl), denoted by SA, and (1 lo), (01 1) and (101), represented using SB, are named active switching states, and (000) and (lll), denoted by So and S7, respectively. The vector times associated with the switching states are shown in eqn. 1 151, and the switching pattern and the associated number of commutations in one carrier period are shown in Table 1:

2 TA = T,a- sin (i - 7 ) J3 2 TB = T,a- sin (7) J3

To = T7 = 0.5 (T, - TA - TB) (1) where

a = v , * / ( p k v d c )

Table 1: Switching patterns and number of commutations, N,, for SVM

Leading edge N, Trailing edge Nc

It is important to note that the number of commutations for the SVM technique shown in Table 1 is constant and equals 3 in every sample period. This feature contributes to the sigmticant dominant clusters in the harmonic spectrum of PWM voltage (current). Moreover, Fig. 2 shows the sampling instants and the associated switchmg patterns for the conventional SVM technique. As shown in Fig. 2, the vector times shown (eqn. 1) are calculated every half car- rier period. Therefore, the calculations required for on-line inverter control increase when the inverter switching fre- quency (carrier frequency) increases.

2.2 Random SVM technique To randomise the inverter switching frequency, thereby reducing the dominant harmonic clusters, and reduce the calculations required for inverter control, a random switch- ing technique has been proposed 12-11.

290

Table 2 illustrates the switching patterns of the random SVM technique [2, 31 in a sampling period. As shown in Table 2, the switching patterns are selected according to the pulse position, leading or trailing edge, and an addi- tional random bit, denoted by ‘RB’. The random bit is generated using a pseudo-random binary sequence (PRBS) generator; more details about the software implementation of the PRBS generator are given in 141. It is important to note that the number of commutations of inverter devices for the random SVM technique shown in Table 2 in two consecutive sampling periods is not constant; it can be 6, 10 or 11, thereby randomising the inverter switchmg fre- quency.

Table 2: Switching patterns and number of commutations for random SVM technique [31

__ _ _ ~

R-E3 Leading edge N, Trailing edge Nc

b Fig.2 (i) Switching patterns; (ii) sampling instants U Starting from leading edge pulse h Starting from trailing edge pulse

Switchmgpattems andsampling instants for SVM technique

(ii) 4 I I 4

a

Tk Tk,l Tk.2 Tk+l

b Fig. 3 (i) Switching patterns; (ii) sampling instants a Starting from leading edge pulse b Starting from trailing edge pulse

Switchmg pattems and s q h g instants for rrmdom technique

IEE ProcElec tr . Power Appl., Vol. 146, No. 3, May 1999

To explain how the random technique [3] reduces the cal- culations required for real-time inverter control, Fig. 3 illustrates the switching patterns and the associated sam- pling instants for the random techque of inverter control using N = 3 as an example; N = number of half carrier periods between two samples. As shown in Fig. 3, the sam- pling frequency is lowered without changing the carrier period to give a sampling period relationship, T, = N T,; one sample is taken every N half carrier periods and the vector times are calculated only at the sampled instant, say Tk and Tk+l.

The vector times for the following half carrier periods between samples, say Tk,l and Tk,2, are the same as those where the sample is taken, say Tk, and therefore the com- putations required for the random inverter control tech- nique can be reduced by N while maintaining the same inverter switching frequency in comparison with the con- ventional SVM technique as shown in Fig. 2. Although the sampling frequency of the random inverter control tech- nique is lowered, the sampling frequency is regular, as illus- trated in Fig. 3. The random SVM technique can therefore be easily incorporated into the existing vector-controlled drive system implemented using a digital microprocessor; more details are reported in [lo].

Noting that the common mode voltage corresponding to the random technique is similar to that associated with the conventional SVM technique [5], more details are explained in the next sub-Section and demonstrated by experimental results in Section 4.

I I I I I I I

L . . . . . . . . . . :

“dc- Fig. 4 Inverter-controlled nwtor drive system

2-3 Effect of zero switching states on common mode voltage The common mode voltage of the inverter-controlled drive, VNo, as shown in Fig. 4, is defined as follows:

3

The contribution of the switching states to the common mode voltage can thus be derived as follows:

for So

It is worthy of note that the Vdc+ and Vd; have opposite polarity; therefore by eqn. 3 the common mode voltage can be reduced if the inverter control technique does not involve the zero switching states, (000) and (1 11).

Fig. 5 shows the relationships between the inverter switching states and common mode voltage. The contribu- tions of zero switching states to common mode voltage are shown in Fig. 56; the upper and lower traces of the enve- lope result from switchg states (111) and (000), respec- tively.

IEE Proc-Electr Power Appl., Vol. 146, No. 3. May 1999

It is of interest to see how the active switching states, SA and SB, affect the common mode voltage. The common mode voltage caused by the switching states SA and SB is shown in Fig. 5c and d, respectively, which can be derived from eqn. 3. The peak value of common mode voltage for active switchng states as shown in Fig. 5c and d is 50% of that for zero switching states as shown in Fig. 5b. There- fore, the common mode voltage, V,,, can be sigmfkantly reduced if no zero switchmg state is used for inverter con- trol.

a

1 .o 0.5

-0.5

-1 .o b

1 .o 0.5 [

0 ot

-1.oL C

1.0r

dO:; -0.5

d -1 .o

Fig. 5 a VAo. VBO, VCU b Common mode voltage for switching states S7 and SO c Common mode voltage for switching state SA d Common mode voltage for switching state SS

Contributwm of inverter switching states to common nwak vofiage

It is important to note that the switchmg patterns shown in Tables 1 and 2 for conventional SVM and random SVM, respectively, invoke zero switching states, So and S7, thereby resulting in si&icantly common mode voltage for inverter-fed drive applications.

3 New random inverter control technique

By the analytical results shown in the preceding Section, the developments of the new random inverter techque should satisfy the following rules: Rule 1: To mitigate the common mode voltage of inverter- fed drives the switching patterns for inverter control should not invoke any zero switching states, as explained using eqn. 3 and Fig. 5. Rule 2: To reduce the dominant harmonic cluster the number of commutations for inverter control should not be constant in a carrier period. Rule 3: To reduce the number of calculations, the sampling frequency is lowered to give a sampling period relationship, T, = N T,; one sample is taken every N half carrier periods and the vector times are calculated only at the sampled instant.

29 1

Note that all these conditions are subject to the fact that the fundamental voltage of inverter output equals the refer- ence voltage vector (modulation signal).

3.7 SVM technique for common mode voltage mitigation Without changing the effective pulse-width of each phase and invoking any zero switching state, the switchmg pat- terns shown in Fig. 6 are modified as illustrated in Fig. 7 using the reference voltage vector in 'sector 1' as an exam- ple. As shown in Fig. 7, the effective pulse-width for each phase is the same as that shown in Fig. 6 providing TNo = To = TN7 = TI, T h = Ti = Tho = To. The features of ths development can be fully explored using the leading pulse shown in Fig. 6 and Fig. 7a as an example and are explained as follows.

(i) '0 : 'A j '6 : '7 I '7 '6 SA so I i : I . . . .

I I j

1 : : 1 ; : 1 ;

. . . .

I ! . . . . . . . .

. . . .

: I : . .

F T ~ ~ T ~ , T, +~-T~-~-T;+L T,' +TL*T~<

PWM waveform undswitclzmgputtm; convention SVM, sector I

. . Tz - .-

Fig. 6

(ii) i : I . . . .

. . . . . . . . ; I j . . . . . .

I I . . : I . . I : I

I : : 1 ;

. .

I I

C

Fig. 7 sector 1 (i) Switching patterns; (ii) PWM waveform

P WM waveform und switchmg patterns; SVM for V,, reduction,

As shown in Fig. 6, the active pulse time ofthe leading edge pulse for phase ' A is (TA + TB + T7), which is equal to that of the leading edge pulse of phase ' A as shown in Fig. 7a if TNo = To = TN7 = TI. A sirmlar process can be applied to the trailing edge of phase 'A to give the Fig. 7a,

292

and can be applied to phase 'C' and phase 'B' to give the results shown in Fig. 7b and c, respectively.

Therefore, the vector times shown in Fig. 7 can be calcu- lated using eqn. 1 and the fundamental voltage of inverter output equals the reference voltage vector (modulation sig- nal). Moreover, as shown in Fig. 7, no zero switching state is invoked for inverter control; therefore the common mode voltage can be si@icantly reduced according to Rule 1.

Similar results for other sectors can be derived too. Therefore, the associated number of commutations and switchmg patterns for Fig. 7a can be summarised in Table 3. Similarly, corresponding to Fig. 7b and c the associated number of commutations and switching patterns are summarised in Tables 4 and 5, respectively.

Table 3: Switching patterns of SVM technique for common mode voltage mitigation; Fig. 7a

Switching patterns and vector times N,

Leadingedge SA - SA + SB + SA 3

Trailingedge S A - SB - SA - SA 3 I C Tm -1- TA - 1- 7-6 * 1- Tm I

I+ T b +I+ Tk+l+ Th -I+ r, -4

Table 4: Switching patterns of SVM technique for common mode voltage mitigation; Fig. 7b

Switching patterns and vector times N,

Table 5: Switching patterns of SVM technique for common mode voltage mitigation; Fig. 7c

~~ ~

Switching patterns and vector times N,

Leading edge SA @ Ss - SA + SB + SA 0 SB 3

Trailing edge

It T , - 1 TA TB Tm * 1

SA@ SB - SB - SA - SA@ SB Itr~-l-rg-l-r~-l-T,Jo'l

3

Note that there are other possible switching patterns for achieving common mode voltage reduction once 'Rule 1' is satisfied. However, it can be shown that the number of commutations in a carrier period will not be less than that of any technique shown in Fig. 7.

3.2 Random SVM technique for common mode voltage mitigation The number of commutations for the common mode miti- gation techniques shown in Table 3-5 is constant in a car- rier period, thereby generating sigmfkant dominant clusters in the harmonic spectrum of voltage (current). To mitigate the common mode voltage and randomise the harmonic spectrum, both Rule 1 and Rule 2 should be satisfied, as discussed previously in Section 2.

Table 6 illustrates the switching patterns and the vector times of the random SVM techmque associated with the common mode voltage mitigation technique shown in Fig. 7a and Table 3. It is important to note that the number of commutations in a carrier period for the new random technique shown in Table 6 is not constant; it can be 6, 10 or 11, depending on the value of the random bit. For example, if 'R-B' = 1 for both leading and trailing edges, the ?witchigg pattern in a carrier period is SA - SA +. SB -+ SA -+ SA -+ SB + S A += SA and the associated

IEE Proc -Electr. Power Appl.. Vol. 146, No. 3, May 1999

number of commutations is 6. S d a r results for other combinations of 'R-B' can also be derived using Table 6. Moreover, similar results associated with Tables 4 and 5 can also be derived to satisfy Rule 2.

Table 6: Switching patterns of random SVM technique for common mode voltage mitigation

Noting that the new random SVM technique does not make any change to the sampling process, the reference voltage vector (modulating signal) is sampled regularly. It can thus be implemented using a digital processor without resorting to additional analogue circuits.

3.3 New random SVM technique As addressed in 'Rule 3', to reduce the number of calcula- tions imposed on the digital microprocessor for the imple- mentation of inverter control, the sampling frequency is lowered to give a sampling period relationship, T, = N T,; one sample is taken every N half carrier periods and the vector times are calculated only at the sampled instant.

Tk Tk,l Tk,2 Tk+l

a

b Fig.8 (i) Switching patterns; (ii) sampling instants a Starting from leading edge pulse b Starting from trailing edge pulse

Switching puttems and sampling instmts for new r&rn technique

Fig. 8 illustrates the switchmg patterns and the associ- ated sampling instants for the new random technique of inverter control using N = 3 as an example; N is the number of half carrier periods between two samples. As demonstrated in Fig. 3 for the conventional random SVM technique [3], the new random technique calculates the vec- tor times only at the sampled instant, say Tk and Tk+l, as shown in Fig. 8, and the vector times for the following half carrier periods between samples, say Tk,l and Tk,2, are the same as those where the sample is taken, say Tk. Therefore the computations required for the new random inverter

IEE Proc.-Electr. Power Appl., Vol. 146, No. 3. May 1999

control techque can be reduced by N while maintaining the same inverter switching frequency.

Note that the switchmg patterns shown in Fig. 8 do not invoke any zero switching states, So and S7, thereby sign& cantly reducing the common mode voltage as explained in eqn. 3. Moreover, the switching patterns illustrated in Fig. 8 result in randomisation of the inverter switching fre- quency as demonstrated in Table 6, thereby dramatically reducing the dominant harmonic clusters of PWM voltage. Further codinnation using experimental results are pre- sented later in this paper.

I - 1 PG (80586)l bus 4 I I I

bus Fig. 9 Designed interface card of PC-based inverter controller

447 Acas

F * I

time 9 Acqs

a

I 1

time 7 Acqs b

I 1

CL time

. Fig. 10 C o m n nwde voltage, eqerhental results a = 0.6p.u.,fi = 30Hz, FR = 45 a Conventional SVM b Conventional random SVM, N = 3 c New random SVM, N = 3

4 Experimental results

4.1 Experimental system Experimental results derived from a PC-based experimental induction motor drive system are presented to codirrn the theoretical analysis. Fig. 9 shows the block diagram and

293

photograph of the designed interface card of the PC-based inverter controller, which consists of an VO address decoder circuit, programmable peripheral interface (PPI), programmable interval timer (PIT) and level control circuit. A PC with an INTEL880586 CPU generates the random bit and calculates the vector times using eqn. 1.

Moreover, the switching patterns are selected as flus- trated in Fig. 8 for the new random technique. The switch- ing states and counter number associated with vector times are send to 8255 and 8254, respectively, via a data bus and decoder circuit. The voltage levels of the switching states are 0 and 5V, and are adjusted to 0 and 15V by the level control circuit to comply with the voltage levels required for inverter control. Once the timer has timed out, 8254 sends an interrupt to PC, and initiates the next process of inverter control.

4.2 Experimental results The experimental results are measured using the following equipment:

oscilloscope: Tektronix TDS 460 A voltage differential probe: SI-900; ratio of attenuation =

20

HI Res I

! " " + ' " ' i

b w ' " " " " time a HI Res

J

b l " ' + h time U

HI Res

CL time

Fig. 1 1 a = 0 3 p u ,fi = 30&, FR = 45 a Conventional SVM b Conventional random SVM, N = 3 c New random SVM, N = 3

Common mode voltage, expermtd results

Fig. 10 shows the common mode voltage of the induction motor controlled by using the conventional SVM technique [5], the conventional random SVM technique [3] and the new random SVM technique, respectively. As shown in Fig. 1Oc for the new random technique, the common mode voltage is si&icantly reduced in comparison with Fig. 1Ou and b for conventional SVM and random SVM, respectively. Similar remarks can also be made from the comparisons results shown in Fig. 11 for lower fundamen- tal voltage (U = 0.3p.u.).

294

Moreover, as explained in Section 3, the calculations required for deriving the result shown in Fig. 10c and Fig. l l c are reduced to 1/N in comparison with those for deriving the results shown in Fig. IOU using the convention SVM technique.

94 Acqs I

i m m 3 9

I

jl.'. '2 a frequency

b frequency 38Acqs ,

C frequency Fig. 1 2 a = 0 6p U ,fi = 30&, FR = 45 a Conventional SVM b Convenhonal random SVM, N = 3 c New random SVM, N = 3

spctrwn of c o m n mode voltage, experunentd results

To fully explore the merits of the new random techtuque, Figs. 12 and 13 illustrate the spectrum of common mode voltage using a = 0.6p.u. and 0.3p.u. as examples, respec- tively. As shown in Fig. 12u and Fig. 13a for the conven- tional SVM technique, the dominant component of common mode voltage is si&icant. In contrast, as shown in Fig. 12c and Fig. 13c the proposed new random tech- nique dramatically reduces the dominant component of common mode voltage. In comparison with conventional SVM and conventional random techniques as shown in Figs. 12 and 13, this improvement becomes more relevant when the voltage command becomes lower.

Furthermore, Figs. 14 and 15 illustrate the voltage spec- trum of inverter output for the conventional SVM tech- nique, conventional random SVM technique, and the new random SVM technique, respectively. As shown in Fig. 14c and Fig. 15c for the new random technique, the first dominant harmonic cluster is dramatically reduced in comparison with Fig. 14a and Fig. 15a for the conven- tional SVM techtuque. The experimental results shown in Fig. 10-15 demonstrate the comparison of results of the conventional techniques and the new random technique, and therefore confirms the theoretical analysis.

5 Conclusion

In tlus paper, a new random inverter control technique for motor drive applications is presented. In comparison with conventional techmques [2-51, the contributions of the new random technique are summarised as follows:

IEE Proc-Electr. Power Appl.. Vol. 146. No. 3, May 1999

HI Res

frequency 2464Acqs I

b frequency 8Acqs

L L

I . . , . C frequency

Fig. 13 a = 0 3 p u . A = 30%, FR = 45 a Conventional SVM b Conventional random SVM, N = 3 c New random SVM, N = 3

Spectrum of c o m n mode voltage, expermtal results

HI Res -- I : J-

a,

H 8

frequency a 4Acqs

al - P - 8

frequency 135Acqs , b

a, cn - 8

C frequency

Fig. 14 a = 0 6 p u , f i = 30%, FR = 45 a Conventional SVM b Conventional random SVM, N = 3 c New random SVM, N = 3

Voltage spectrum of mverter output, expermtal results

si&icant reduction of both the first dominant cluster and computations in comparison with those for existing SVM technique [5];

dramatic mitigation of the common mode voltage in com- parison with that for conventional (random) SVM tech- niques [2-51.

HI Res 1

I . . , a frequency

I " f " " 1 4 Acqs

i

h frequency

1

C frequency Fig. 15 a = 0.3p.u.,fi = 30Hz, FR = 45 a Conventional SVM b Conventional random SVM, N = 3 c New random SVM, N = 3

voltage s p c t m of inverter output, experkntal results

All of these features and the associated theoretical analysis are verified by experimental results derived from a micro- processor-based experimental drive.

Furthermore, it has been shown that the new random technique does not invoke any change to the sampling technique; therefore it can be easily incorporated into the existing inverter control system with only minor modifica- tions to the switchmg patterns. The author wishes to report the test results of incorporating the new random technique into sensorless vector-controlled drives in the future.

6 Acknowledgment

The author gratefully acknowledges C.H. Chen for his con- tribution to the experimental work.

7 References

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