New Approach For Full Chip Electrical Reliability Verification

Frank Feng

New Approach For Full Chip Electrical Reliability Verification

Circuit Verification Methodologist

Calibre D2S

May, 2017

Restricted © 2017 Mentor Graphics Corporation

We live in a dynamic world/society, but we intend to make our lives rich/smooth/safe by rule regulations

Silicon chip is operated under a dynamic environment, but we intend to make our chip working as designed with good reliability by rule checking

The rule checking is a static approach, however, it is a real practical way to verify full chip design reliability, especially for design in advanced technology (28 nm, 16 nm, 10 nm, 7 nm, etc.)

Use Static Rule to Regulate Dynamic Behavior :

2 HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017


Status of Chip Design Reliability Verification : Consider Methodology, Tool, and Foundry Support

3

Reliability Design Issue

Chip Cell/Transistor

Dynamic Static Dynamic Static

ESD ?

Latch-up ?

EOS ?

TDDB ?

Analog Logic Driven Layout Design

?

IR Drop

EM

Reliability Design Issue

Chip Cell/Transistor

Dynamic Static Dynamic Static

ESD

Latch-up

EOS

TDDB

Analog Logic Driven Layout Design

IR Drop

EM

HHF, New Approach For Full Chip Electrical Reliability Verification, May 2017


Manual Check, Marker, or Using Less Accurate Design Data are General ESD/Latch-up Design Practices, but they are un-reliable

4

VDD

VSS

Input

Pad

Core Circuit

IO Cell Power Cell IO Cell

It is interconnect resistance along ESD path wanted by designer

Manual placed marker layer is not a desired method



Comprehensive ESD Design Verification Can be Achieved by Calibre PERC in Automation :

Power Clamping

Circuit

Core Circuit

Power Pads

Ground Pads

5

DVDD AVDD

DVSS AVSS

IO PAD

IO ESD Circuit

ESD Path Resistance

ESD Path Current Density

CDM ESD Circuit

P2P Effective Resistance



Comprehensive Latch-up Design Verification Can be Achieved by Calibre PERC in Automation :

6

Spacing <= #um

N+ OD

P+

STRAP

N+

STRAP

R<#ohm

P+ OD

R<#ohm

required



Comparison Between Automatic And Manual ESD Design Verification Methodology :

7

Items Calibre PERC Marker Layer Eye Ball

Rules Coverage over 90% under 30% under 10%

False Error no many always

Tool Integration topology, LVS, DRC, R-

extraction

DRC + manual

marker

manual

examining

Tool Quality sign-off level dependence no quality

Programmable fully partially never

Run Time ~ hours hours ~ days ~ days

Human Error never sometimes always

User Usage automatically semi-auto manually



Logic Driven Layout Check Flow :

8

PERC LDL P2P/CD

Probe Points

Generation

+

R Extraction

Topology

Pin Pairs Selection

Layout

Netlist Extraction

Layout GDS/OASIS

Static Simulation

↓

Generate Result DFMDB

PERC LDL DRC

Generate

Selected Devices / Nets

Geometrical Shapes

Topology Devices /

Nets Selection

Layout

Netlist Extraction

Layout GDS/OASIS

Execute DRC Operations

↓

Generate Result DFMDB



Netlist Traverse Integrates Layout DRC, LVS, PEX, and Spice Simulation to Provide Functions of :

Programmable Topological Checking, Pattern Recognition, and Voltage Propagation

Logical Driven Layout P2P Effective Resistance Check

Logical Drive Layout Current Density Check

Logical Driven Layout DRC Check



Core Circuit

Topology Checking for Verification of IO/PG ESD Protection Scheme :

Power Pads

10

IO PAD

IO ESD Circuit

Power Pads

Ground Pads Ground Pads

Power Clamp

Trigger CKT



Topology Checking for Verification of Cross Power Domain CDM Protection Scheme :

11

VDD1 VDD2

VSS1 VSS2

Power Clamp

Power Clamp

VSS (Common Ground)

Core Circuit 1 Core Circuit 2



PERC-LDL P2P : For Verification of Reff Along ESD Paths and Across Different Voltage Domains to Ensure ESD Paths will Provide Protection as Designed

Power Pads

Ground Pads 12

IO PAD Core

Circuit Core

Circuit 2 Core

Circuit 1

VDD1 VDD2

VSS1 VSS2



Calibre PERC Catches Violations Matched With Real Silicon Failures :

13

Over Threshold Current Density Burn Weak Interconnect Area

No CDM Protection On Cross Power Domain Net, Receiver Gate Is Damaged



Real User Comment for Calibre PERC : Automatic, Efficient, and Accurate

14 14

Items Eye Ball Calibre PERC

Rules Coverage under 10% over 90%

Time Consumed 3 man day

(24 hours)

0.3 hour execution

+ 1.5 hour layout extraction

+ 1.5 hour current density check

+ 2.5 hour P2P resistance check

Tool Integration Manual Examination Topology, LVS, DRC, P2P, CD

Repetition Effort doubled Small overhead

Human Error Prone immune



Calibre PERC is Qualified by TSMC for Un-Checkable ESD/LATCH-UP Rules in DRM :



Run Summary of ESD Path Reff Measurements For a N10 Design ~ 1 cm^2 / Multi-Billion Devices



Perform Electrical Over Stress Checking without Dynamic Simulation by Calibre PERC Voltage Propagation

Identify design

Label voltages

Propagate voltages

Catch static violations

Debug using RVE

3.6 1.8 1.8

0

EOS has caused integrated circuit failures, regardless of the semiconductor manufacturer

The result of an EOS event can range from degradation to the IC up to catastrophic damage where the IC is permanently non-functional



LOGICS

An Useful Static Voltage Propagation to Handle General Multi-Power Domains Chip Needs : A Methodology to Assist Voltage Shift

18

Core

Power Management

VCC_3P3

VOUT_1P8

Nch_thinOx

Nch_thinOx

Nch_thinOx

Net-A

Net-B

Net-C

Net-D

VOUT_2P5

VCORE_1P2

VCORE_2P5

VCORE_1P8

VCORE_1P2



A Few Techniques Are Used To Shift Voltage in Propagating Voltage into Internal Circuitry :

19

User provides specific nets to assist voltage shift

User provides specific cells or cell placements to assist voltage shift

User provides specific circuit patterns to assist voltage shift



Voltage Dependent DRC is a Feasible Verification Methodology for Interconnect TDDB : is Provided for 20 nm+ Technology by Foundry

20

The thin dielectric between different node for interconnect metal wires is under substantial electrical stress, and is prone to breakdown over time

In Foundry DRC tech file, spacing criteria is raised when net is applied by higher than core voltage. The spacing criteria is further regulated into different levels depending on delta-voltage range between the nets

Foundry has provided text annotation methodology to facilitate voltage dependent DRC checks



LOGICS

To Achieve Voltage Dependent DRC Checking : Static Voltage Propagation + Voltage Shift Methodology + Text Annotated DRC

21

Core

Power Management

VCC_3P3

VOUT_1P8

Nch_thinOx

Nch_thinOx

Nch_thinOx

Net-A

Net-B

Net-C

Net-D

VOUT_2P5

VCORE_1P2

VCORE_2P5

VCORE_1P8

VCORE_1P2

2.5

1.2

1.8

3.3

1.2

1.2

2.5

1.2

3.3

Export high voltage nets with {maxV #} {minV #} annotation



A New EDA Tool Platform Can Handle Wide Scope Of Reliability Verifications :

Realize Area Savings

Voltage Aware DRC

Avoid Chip Failures

EOS ESD

Calibre PERC

Validate SoC / AMS Design Intent

Multi-Power Domains Analog Design Matching Pair

dum

my

dum

my

m1

m1

m2

m2

dum

my

dum

my

m3 m4

Verification Beyond Traditional DRC, LVS, ERC, and PEX Rule Base Approach Align With Foundry Design Rule

22

IO ESD / PG Clamp Verification


New Approach For Full Chip Electrical Reliability Verification

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