Neel Gala, CTO, Incore Semiconductors RiTA (RISC-V Trace ...€¦ · Anmol Sahoo, Project...
Transcript of Neel Gala, CTO, Incore Semiconductors RiTA (RISC-V Trace ...€¦ · Anmol Sahoo, Project...
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RiTA (RISC-V Trace Analyzer)
Anmol Sahoo, Project Associate, IIT Madras
Neel Gala, CTO, Incore Semiconductors
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Outline
▪ Need for a trace analyzer▪ Design and features of RiTA▪ Examples▪ Getting started with RiTA
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SHAKTISHAKTI
Need for a trace analyzer
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Need for a trace analyzer
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▪ Hardware designers need to understand software execution characteristics
▪ Trace analyzers should be able to analyze traces from generic execution contexts - Spike, FPGA, Silicon
▪ Designers can better use this information to extend or improve their designs at various levels
▪ Architectural Decisions▫ Macro-op Fusion▫ Pseudo-ops▫ ISA Extensions
![Page 5: Neel Gala, CTO, Incore Semiconductors RiTA (RISC-V Trace ...€¦ · Anmol Sahoo, Project Associate, IIT Madras Neel Gala, CTO, Incore Semiconductors. SHAKTI Outline Need for a trace](https://reader033.fdocuments.in/reader033/viewer/2022052002/6014d3c27a2a384d425b507f/html5/thumbnails/5.jpg)
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Need for a trace analyzer
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▪ Hardware designers need to understand software execution characteristics
▪ Trace analyzers should be able to analyze traces from generic execution contexts - Spike, FPGA, Silicon
▪ Designers can better use this information to extend or improve their designs at various levels
▪ Architectural Decisions▫ Macro-op Fusion▫ Pseudo-ops▫ ISA Extensions
![Page 6: Neel Gala, CTO, Incore Semiconductors RiTA (RISC-V Trace ...€¦ · Anmol Sahoo, Project Associate, IIT Madras Neel Gala, CTO, Incore Semiconductors. SHAKTI Outline Need for a trace](https://reader033.fdocuments.in/reader033/viewer/2022052002/6014d3c27a2a384d425b507f/html5/thumbnails/6.jpg)
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Need for a trace analyzer
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▪ Hardware designers need to understand software execution characteristics
▪ Trace analyzers should be able to analyze traces from generic execution contexts - Spike, FPGA, Silicon
▪ Designers can better use this information to extend or improve their designs at various levels
▪ Architectural Decisions▫ Macro-op Fusion▫ Pseudo-ops▫ ISA Extensions
![Page 7: Neel Gala, CTO, Incore Semiconductors RiTA (RISC-V Trace ...€¦ · Anmol Sahoo, Project Associate, IIT Madras Neel Gala, CTO, Incore Semiconductors. SHAKTI Outline Need for a trace](https://reader033.fdocuments.in/reader033/viewer/2022052002/6014d3c27a2a384d425b507f/html5/thumbnails/7.jpg)
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Need for a trace analyzer
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▪ Hardware designers need to understand software execution characteristics
▪ Trace analyzers should be able to analyze traces from generic execution contexts - Spike, FPGA, Silicon
▪ Designers can better use this information to extend or improve their designs at various levels
▪ Architectural Decisions▫ Macro-op Fusion▫ ISA Extensions▫ Hardware Optimization
![Page 8: Neel Gala, CTO, Incore Semiconductors RiTA (RISC-V Trace ...€¦ · Anmol Sahoo, Project Associate, IIT Madras Neel Gala, CTO, Incore Semiconductors. SHAKTI Outline Need for a trace](https://reader033.fdocuments.in/reader033/viewer/2022052002/6014d3c27a2a384d425b507f/html5/thumbnails/8.jpg)
SHAKTISHAKTI
Design and features of RiTA
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Design of RiTA
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▪ RiTA is a command line tool written in Python▪ Tiered application
▫ Trace File Parser▫ Instruction Parser▫ Post-processing Modules
▪ Makes it easy to extend!
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Features of RiTA
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The following post-processing modules are being developed in RiTA,▪ Instruction histogram and statistics▪ Register histogram▪ Memory access histogram▪ Branch statistics▪ Dependent instruction sequences
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Examples
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Instruction Histogram
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Register Access Statistics
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Program Counter Histogram
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Getting Started
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▪ The application is available from the PyPI package repository▪ Get Started,▪ pip install rita▪ Future work will look at,
▫ Parsing new ISA extensions▫ Optimization suggestions
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Thank you for your time! :D