NCV3025833 - Smart Power Stage (SPS) Module with ...

DATA SHEETwww.onsemi.com

© Semiconductor Components Industries, LLC, 2019

September, 2021 − Rev. 11 Publication Order Number:

NCV3025833/D

Smart Power Stage (SPS)Module with IntegratedThermal Warning andThermal Shutdown

NCV3025833Description

The SPS family is onsemi’s next-generation, fully optimized,ultra-compact, integrated MOSFET plus driver power stage solutionfor high-current, high-frequency, synchronous buck, DC−DCapplications. The NCV3025833 integrates a driver IC with a bootstrapSchottky diode, two power MOSFETs, and a thermal monitor into athermally enhanced, ultra-compact 5 mm × 5 mm package.

With an integrated approach, the SPS switching power stage isoptimized for driver and MOSFET dynamic performance, minimizedsystem inductance, and power MOSFET RDS(ON). The SPS familyuses onsemi’s high-performance POWERTRENCH® MOSFETtechnology, which reduces switch ringing, eliminating the need for asnubber circuit in most buck converter applications.

A driver IC with reduced dead times and propagation delays furtherenhances the performance. A thermal warning function warns of apotential over-temperature situation. A thermal shutdown functionturns off the driver if an over-temperature condition occurs. TheNCV3025833 incorporates an Auto-DCM Mode (ZCD#) forimproved light-load efficiency.

The NCV3025833 also provides a 3-state 5 V PWM input forcompatibility with a wide range of PWM controllers.

Features• Ultra-compact 5 mm × 5 mm WQFN Copper-clip Package with

Flip Chip Low-Side MOSFET• High Current Handling: 50 A

• 3-State 5 V PWM Input Gate Driver

• Dynamic Resistance Mode for Low-side Drive (LDRV) SlowsLow-side MOSFET during Negative Inductor Current Switching

• Auto DCM (Low-side Gate Turn Off) Using ZCD# Input

• Thermal Warning (THWN#) to Warn Over-temperature of GateDriver IC

• Thermal Shutdown (THDN)

• HS-short Detect Fault# / Shutdown

• Dual Mode Enable / Fault# Pin

• Internal Pull-up and Pull-down for ZCD# and EN Inputs,respectively

• onsemi POWERTRENCH MOSFETs for Clean Voltage Waveforms and Reduced Ringing

See detailed ordering and shipping information on page 25 ofthis data sheet.

ORDERING INFORMATION

WQFNW33CASE 512AE

MARKING DIAGRAM

3025833 = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work Week� = Pb−Free Package

NCV3025833

AWLYYWW�

http://www.onsemi.com/

NCV3025833

www.onsemi.com2

Features (continued)

• onsemi SyncFET� Technology (Integrated Schottky Diode) in Low-side MOSFET

• Integrated Bootstrap Schottky Diode

• Optimized / Extremely Short Dead-times

• Under-voltage Lockout (UVLO) on VCC

• Optimized for Switching Frequencies up to 1.5 MHz

• PWM Minimum Controllable On-time: 30 ns

• Low Shutdown Current: < 3 �A

• Optimized FET Pair for Highest Efficiency: 10~15%Duty Cycle

• Operating Junction Temperature Range: −40°C to+125°C

• onsemi Green Packaging

• Automotive Qualified to AEC−Q100 with WettableFlanks

• NCV Prefix for Automotive and Other ApplicationsRequiring Unique Site and Control Change

Requirements; AEC−Q100 Qualified and PPAPCapable

• These Devices are Pb-Free, Halogen Free/BFR Freeand are RoHS Compliant

Applications• Notebook, Tablet PC and Ultrabook

• Servers and Workstations, V-Core and Non-V-CoreDC−DC Converters

• Desktop and All-in-One Computers, V-Core andNon-V-Core DC−DC Converters

• High-performance Gaming Motherboards

• High-current DC−DC Point-of-Load Converters

• Networking and Telecom Microprocessor VoltageRegulators

• Small Form-factor Voltage Regulator Modules

• Automotive-qualified Systems


NCV3025833

www.onsemi.com3

PIN CONFIGURATION

9

10

11

12

13

14

15

16 17 18 19 20 21 22 23

24

25

26

27

28

29

30

31

8 7 6 5 4 3 2 1 PWM

ZCD

#

VCC

AG

ND

BO

OT

NC

PHA

SE

VIN

SW

SW

SW

GL

PGND

PVCC

THWN#

EN/FAULT#

PGND

PGND

PGND

PGND

VIN

VIN

VIN

SW SW SW SW SW SW SW SW

8 7 6 5 4 3 2 1

16 17 18 19 20 21 22 23

2425

2627

2829

3031

910

1112

1314

15

32AGND

33GL

Figure 1. Pin Configuration − Top View and Transparent View

PIN DESCRIPTION

Pin No. Symbol Description

1 PWM PWM input to the gate driver IC

ÁÁÁÁÁÁÁÁÁÁÁÁ

2 ÁÁÁÁÁÁÁÁÁÁ

ZCD# ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Enable input for the ZCD (Auto DCM) comparator



VCC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power supply input for all analog control functions; this is the “quiet” VCC


4, 32 ÁÁÁÁÁÁÁÁÁÁ

AGND ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Analog ground for analog portions of the IC and for substrate, internally tied to PGND



BOOT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies the charge toturn on the N-channel high-side MOSFET.ÁÁÁÁÁÁ

ÁÁÁÁÁÁ6ÁÁÁÁÁÁÁÁÁÁNC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁNo connectÁÁÁÁÁÁ

ÁÁÁÁÁÁ7

ÁÁÁÁÁÁÁÁÁÁ

PHASEÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Return connection for the boot capacitor, internally tied to SW nodeÁÁÁÁÁÁÁÁÁÁÁÁ

8~11ÁÁÁÁÁÁÁÁÁÁ

VINÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power input for the power stageÁÁÁÁÁÁÁÁÁÁÁÁ

12~15, 28ÁÁÁÁÁÁÁÁÁÁ

PGNDÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power return for the power stageÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

16~26ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

SWÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Switching node junction between high-side and low-side MOSFETs; also input to the gate driver SW nodecomparator and input into the ZCD comparator


27, 33 ÁÁÁÁÁÁÁÁÁÁ

GL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Gate Low, Low-side MOSFET gate monitor



PVCC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power supply input for LS (Note1) gate driver and boot diode



THWN# ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

125°C Thermal Warning Flag – pulls LOW upon detection of 125°C thermal warning preset temperature



EN / FAULT#ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Dual-functionality, enable input to the gate driver IC. FAULT# − internal pull-down physically pulls this pinLOW upon detection of fault condition (HS (Note 2) MOSFET short or 150°C THDN).

1. LS = Low Side2. HS = High Side


NCV3025833

www.onsemi.com4

DIAGRAMS

CVINCVCCCPVCC

NCV3025833

PWM

ZCD#

THWN#

EN/FAULT#

PVCC VCC VIN

BOOT

PHASE

SW

AGND

RVCC

VINV5V

EN

PWM Input

VOUT

LOUT

OFF

ON

RBOOT

CBOOT

COUTPGND

THWN#

GL

Figure 2. Typical Application Diagram

Figure 3. Functional Block Diagram

BOOTPVCC VIN

FAULT

PWM CONTROLLOGIC

PWM INPUT

EN/UVLO

ZCD/CCM/DCMLOGIC

LEVELSHIFT

EN/FAULT#

HDRV

LDRV1

LDRV2

FAULTLATCH

THWN#

VCC

PWM

PHASE

SW

PGND

ZCD#

AGND

GL

VCC

PVCC

PVCC

0.8 V/ 2.0 V

0.8 V/ 2.0 V

POR

POR

RUP_PWM

RDN_PWM

THWN /THDN

VCC

10 �A


NCV3025833

www.onsemi.com5

ABSOLUTE MAXIMUM RATINGS (TA = TJ = 25°C)

Symbol Parameter Min Max Unit

VCC Supply Voltage Referenced to AGND −0.3 6.0 V

PVCC Drive Voltage Referenced to AGND −0.3 6.0 V

VEN/FAULT# Output Enable / Disable Referenced to AGND −0.3 6.0 V

VPWM PWM Signal Input Referenced to AGND −0.3 VCC+0.3 V

VZCD# ZCD Mode Input Referenced to AGND −0.3 6.0 V

VGL Low Gate Manufacturing Test Pin Referenced to AGND (DC Only) −0.3 6.0 V

Referenced to AGND, AC < 20 ns −3.0 6.0

VTHWN# Thermal Warning Referenced to AGND −0.3 6.0 V

VIN Power Input Referenced to PGND, AGND −0.3 30.0 V

VPHASE PHASE Referenced to PGND, AGND (DC Only) −0.3 30.0 V

Referenced to PGND, AC < 20 ns −7.0 35.0

VSW Switch Node Input Referenced to PGND, AGND (DC Only) −0.3 30.0 V

Referenced to PGND, AC < 20 ns −7.0 35.0

VBOOT Bootstrap Supply Referenced to AGND (DC Only) −0.3 35.0 V

Referenced to AGND, AC < 20 ns −5.0 40.0

VBOOT−PHASE Boot to PHASE Voltage Referenced to PVCC −0.3 6.0 V

VIN−PHASE VIN to Phase Voltage DC only −0.3 30.0 V

AC < 5ns −7.0 35 V

IO(AV)(Note 3)

Output Current fSW = 300 kHz, VIN = 12 V, VOUT = 1.8 V − 50 A

fSW = 1 MHz, VIN = 12 V, VOUT = 1.8 V − 45

IFAULT EN / FAULT# Sink Current −0.1 7.0 mA

EAVDS Single−Pulse Drain−to−Source Avalanche Energy, High−Side FET (TJ = 25 °C, VGS = 5 V, L = 1.65 �H, IL = 97.0 APK)

− 21.4 mJ

ESD Electrostatic Discharge Protection Human Body Model, AEC−Q100−002 2000 − V

Charged Device Model, AEC−Q100−011 2000 −

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.3. IO(AV) is rated with testing onsemi’s SPS evaluation board at TA = 25°C with natural convection cooling. This rating is limited by the peak

SPS temperature, TJ = 150°C, and varies depending on operating conditions and PCB layout. This rating may be changed with differentapplication settings.

THERMAL INFORMATION

Symbol Parameter Value Unit

�J−Lead(Note 4)

Junction-to-Lead Thermal Resistance (Mounted on 2S2P test board with 0 LFM at TA = 25°C)

2.9 °C/W

�J−CaseTop Junction-to-Top of Case Thermal Resistance (Mounted on 2S2P test board with 0 LFM at TA = 25°C)

13.4 °C/W

TA Ambient Temperature Range −40 to +125 °C

TJ Maximum Junction Temperature +150 °C

TSTG Storage Temperature Range −55 to +150 °C

4. Measured at PGND Pad (Pins 12 – 15)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

VCC Control Circuit Supply Voltage 4.5 5.0 5.5 V

PVCC Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

VIN Output Stage Supply Voltage 4.5 (Note 5) 19.0 24.0 (Note 6) V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.5. 3.0 V VIN is possible according to the application condition.6. Operating at high VIN can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes during MOSFET switching

transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute Maximum Ratings in the tableabove.


NCV3025833

www.onsemi.com6

ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = +25°C unless otherwise noted. Min/Max values are valid for VIN = 12 V, VCC = PVCC = 5 V±10% and TJ = TA = −40°C ~ +125°C and are guarenteed by test, design, or statistical correlation)

Symbol Parameter Test Conditions Min Typ Max Unit

BASIC OPERATION

IQ Quiescent Current IQ = IVCC + IPVCC, EN = HIGH, PWM = LOWor HIGH or Float (Non-Switching)

− − 2 mA

ISHDN Shutdown Current ISHDN = IVCC + IPVCC, EN = GND − − 3 �A

VUVLO UVLO Threshold VCC Rising 3.5 3.8 4.1 V

VUVLO_HYST UVLO Hysteresis − 0.4 − V

tD_POR POR Delay to Enable IC VCC UVLO Rising to Internal PWM Enable − − 20 �s

EN INPUT

VIH_EN High-Level Input Voltage 2.0 − − V

VIL_EN Low-Level Input Voltage − − 0.8 V

RPLD_EN Pull-Down Resistance − 250 − k�

tPD_ENL EN LOW Propagation Delay PWM = GND, EN Going LOW to GL GoingLOW

− 25 45 ns

tPD_ENH EN HIGH Propagation Delay PWM = GND, EN Going HIGH to GL GoingHIGH

− − 25 �s

ZCD# INPUT

VIH_ZCD# High-Level Input Voltage 2.0 − − V

VIL_ZCD# Low-Level Input Voltage − − 0.8 V

IPLU_ZCD# Pull-Up Current − 10 − �A

tPD_ZLGLL ZCD# LOW Propagation Delay PWM = GND, ZCD# Going LOW to GLGoing LOW (assume IL ≤ 0)

− 10 − ns

tPD_ZHGLH ZCD# HIGH Propagation Delay PWM = GND, ZCD# Going HIGH to GLGoing HIGH

− 10 − ns

PWM INPUT

RUP_PWM Pull-Up Impedance − 10 − k�

RDN_PWM Pull-Down Impedance − 10 − k�

VIH_PWM PWM High Level Voltage 3.8 − − V

VTRI_Window 3-State Window 1.2 − 3.1 V

VIL_PWM PWM Low Level Voltage − − 0.8 V

tD_HOLD−OFF 3-State Shut-Off Time − 90 130 ns

VHIZ_PWM 3-State Open Voltage 2.1 2.5 2.9 V

MINIMUM CONTROLLABLE ON−TIME

tMIN_PWM_ON PWM Minimum Controllable On-Time

Minimum PWM HIGH Pulse Required forSW Node to Switch from GND to VIN

30 − − ns

FORCED MINIMUM GL HIGH TIME

tMIN_GL_HIGH Forced Minimum GL HIGH Minimum GL HIGH Time when LOW VBOOT−SW detected and PWM LOW ≤ 100 ns

− 100 − ns

PWM INPUT PROPAGATION DELAYS AND DEAD TIMES (VIN = 12 V, VCC = PVCC = 5 V, fsw = 1 MHz, IOUT = 20 A, TA = 25°C)

tPD_PHGLL PWM HIGH Propagation Delay PWM Going HIGH to GL Going LOW, VIH_PWM to 90% GL

− 15 − ns

tPD_PLGHL PWM LOW Propagation Delay PWM Going LOW to GH (Note 7) GoingLOW, VIL_PWM to 90% GH

− 30 − ns

tPD_PHGHH PWM LOW Propagation Delay (ZCD# Held LOW)

PWM Going HIGH to GH Going HIGH,VIH_PWM to 10% GH (ZCD# = LOW, IL = 0,assumes DCM)

− 10 − ns

tD_DEADON LS Off to HS On Dead Time GL Going LOW to GH Going HIGH, 10%GL to 10% GH, PWM Transition LOW toHIGH (See Figure 30)

− 10 − ns


NCV3025833

www.onsemi.com7

ELECTRICAL CHARACTERISTICS (continued)(VIN = 12 V, VCC = PVCC = 5 V and TA = TJ = +25°C unless otherwise noted. Min/Max values are valid for VIN = 12 V, VCC = PVCC = 5 V±10% and TJ = TA = −40°C ~ +125°C and are guarenteed by test, design, or statistical correlation)

Symbol UnitMaxTypMinTest ConditionsParameter

PWM INPUT PROPAGATION DELAYS AND DEAD TIMES (VIN = 12 V, VCC = PVCC = 5 V, fsw = 1 MHz, IOUT = 20 A, TA = 25°C)

tD_DEADOFF HS Off to LS On Dead Time GH Going LOW to GL Going HIGH, 10%GH to 10% GL, PWM Transition HIGH toLOW (See Figure 30)

− 5 − ns

tR_GH_20A GH Rise Time under 20 A IOUT 10% GH to 90% GH, IOUT = 20 A − 9 − ns

tF_GH_20A GH Fall Time under 20 A IOUT 90% GH to 10% GH, IOUT = 20 A − 9 − ns

tR_GL_20A GL Rise Time under 20 A IOUT 10% GL to 90% GL, IOUT = 20 A − 9 − ns

tF_GL_20A GL Fall Time under 20 A IOUT 90% GL to 10% GL, IOUT = 20 A − 6 − ns

tPD_TSGHH Exiting 3-State Propagation Delay PWM (from 3-State) Going HIGH to GHGoing HIGH, VIH_PWM to 10% GH

− − 45 ns

tPD_TSGLH Exiting 3-State Propagation Delay PWM (from 3-State) Going LOW to GL Going HIGH, VIL_PWM to 10% GL

− − 45 ns

WEAK LOW−SIDE DRIVER (LDRV2 Only under CCM2 Mode Operation, VCC = PVCC = 5 V)

RSOURCE_GL Output Impedance, Sourcing Source Current = 100 mA − 0.82 − �

RSINK_GL Output Impedance, Sinking Sink Current = 100 mA − 0.86 − �

LOW−SIDE DRIVER (Paralleled LDRV1 + LDRV2 under CCM1 Mode Operation, VCC = PVCC = 5 V)

RSOURCE_GL Output Impedance, Sourcing Source Current = 100 mA − 0.47 − �

RSINK_GL Output Impedance, Sinking Sink Current = 100 mA − 0.29 − �

tR_GL GL Rise Time 10% GL to 90% GL, CLOAD = 7.0 nF − 9 − ns

tF_GL GL Fall Time 90% GL to 10% GL, CLOAD = 7.0 nF − 6 − ns

THERMAL WARNING FLAG (125°C)

TACT_THWN_125 Activation Temperature Measured on the driver IC with TJ = TA − 125 − °C

TRST_THWN_125 Reset Temperature − 110 − °C

RPLD_THWN Pull-Down Resistance IPLD_THWN = 1 mA − 40 − �

THERMAL SHUTDOWN (150°C)

TACT_THDN Activation Temperature Measured on the driver IC with TJ = TA − 150 − °C

RPLD_EN−THDN Pull-Down Resistance IPLD_EN−THDN = 1 mA − 100 − �

CATASTROPHIC FAULT (SW Monitor)

VSW_MON SW Monitor Reference Voltage − 1.3 2 V

tD_FAULT Propagation Delay to Pull EN /FAULT# Signal = LOW

− 20 − ns

BOOT DIODE

VF Forward-Voltage Drop IF = 10 mA − 0.4 − V

VR Breakdown Voltage IR = 1 mA 30 − − V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.7. GH = Gate High, internal gate pin of the high-side MOSFET.


NCV3025833

www.onsemi.com8

TYPICAL PERFORMANCE CHARACTERISTICS(Test Conditions: VIN = 12 V, VCC = PVCC = 5 V, VOUT = 1 V, LOUT = 250 nH, TA = 25°C and natural convection cooling,

unless otherwise noted.)

Figure 4. Safe Operating Area 12 VIN Figure 5. Safe Operating Area 19 VIN

Figure 6. Power Loss vs. Output Current with 12 VIN Figure 7. Power Loss vs. Output Current with 19 VIN

0

5

10

15

20

25

30

35

40

45

50

60

55

0 25 50 75 100 125

Mo

du

le O

utp

ut

Cu

rren

t, I O

UT

[A]

150PCB Temperature, TPCB [�C]

FSW = 300kHz

FSW = 1000kHz

VIN = 12V, PVCC & VCC = 5V, VOUT = 1V05

101520253035404550

6055

0 25 50 75 100 125

Mo

du

le O

utp

ut

Cu

rren

t, I O

UT

[A]

150PCB Temperature, TPCB [�C]

FSW = 300kHz

FSW = 1000kHz

VIN = 19V, PV CC & VCC = 5V, V OUT = 1V

0123456789

1011

1312

0 5 10 15 20 25 30 35 40 45 50

Mo

du

le P

ow

er L

oss

, PL

M O

D[W

]

55Module Output Current, IOUT [A]

12Vin,300kHz12Vin,500kHz12Vin,800kHz12Vin,1000kHz

PVCC & VCC = 5V, VOUT = 1V

0123456789

101112

1413

0 5 10 15 20 25 30 35 40 45 50

Mo

du

le P

ow

er L

oss

, PL

M O

D[W

]


19Vin,300kHz19Vin,500kHz19Vin,800kHz19Vin,1000kHz

PVCC & VCC = 5V, VOUT = 1V


NCV3025833

www.onsemi.com9



Figure 8. Power Loss vs. Switching Frequency Figure 9. Power Loss vs. Input Voltage

Figure 10. Power Loss vs. Driver Supply Voltage Figure 11. Power Loss vs. Output Voltage

Figure 12. Power Loss vs. Output Inductor Figure 13. Driver Supply Current vs. SwitchingFrequency

0.8

0.9

1.0

1.1

1.2

1.4

1.3

300 400 500 600 700 800 900

No

rmal

ized

Mo

du

le P

ow

er L

oss

1000Module Switching Frequency, FSW [kHz]

VIN = 19V, PVCC & VCC = 5V, VOUT = 1V, IOUT = 30A

0.95

1.00

1.05

1.10

1.20

1.15

4 6 8 10 12 14 16 18

No

rmal

ized

Mo

du

le P

ow

er L

oss

20Module Input Voltage, VIN [V]

PVCC & VVCC= 5V, VOUT = 1V, FSW = 500kHz,IOUT = 30A

0.90

0.95

1.00

1.05

1.10

1.15

4.0 4.5 5.0 5.5

No

rmal

ized

Mo

du

le P

ow

er L

oss

6.0Driver Supply Voltage, PVCC & VCC [V]

VIN = 12V, VOUT = 1V, FSW = 500kHz, IOUT = 30A

1.0

1.1

1.2

1.3

1.5

1.4

1.0 1.5 2.0 2.5

No

rmal

ized

Mo

du

le P

ow

er L

oss

3.0Module Output Voltage, VOUT [V]

VIN = 12V, PVCC & VVCC = 5V,FSW = 500kHz, IOUT = 30A

1.000

1.002

1.004

1.006

1.008

1.010

1.014

1.012

250 300 350 400

No

rmal

ized

Mo

du

le P

ow

er L

oss

450Output Inductor, L OUT [nH]

VIN = 12V, PVCC & VVCC = 5V, FSW = 500kHz,VOUT = 1V, IOUT = 30A

0.01

0.015

0.02

0.025

0.03

0.04

0.035

300 400 500 600 700 800 900

Dri

ver

Su

pp

ly C

urr

ent,

I PV

CC+

I VC

C[A

]

1000Module Switching Frequency, FSW [kHz]

VIN = 12V, PVCC& VCC = 5V, VOUT = 1V, IOUT = 0A


NCV3025833

www.onsemi.com10



Figure 14. Driver Supply Current vs. DriverSupply Voltage

Figure 15. Driver Supply Current vs. OutputCurrent

Figure 16. UVLO Threshold vs. Temperature Figure 17. PWM Threshold vs. Driver SupplyVoltage

Figure 18. PWM Threshold vs. Temperature Figure 19. ZCD# Threshold vs. Driver SupplyVoltage

0.016

0.017

0.018

0.019

0.020

0.021

0.023

0.022

4.5 5.0 5.5Dri

ver

Su

pp

ly C

urr

ent,

I PV

CC

+ I V

CC

[A]

6.0Driver Supply Voltage, PVCC & VVCC [V]

VIN = 12V, VOUT = 1V, FSW = 500kHz, IOUT = 0A

0.90

0.92

0.94

0.96

0.98

1.00

1.02

1.04

1.06

0 5 10 15 20 25 30 35 40 45

No

rmal

ized

Dri

ver

Su

pp

ly C

urr

ent


FSW= 300kHz

FSW= 800kHz

VIN = 12V, PVCC & VVCC = 5V, VOUT = 1V

3.2

3.3

3.4

3.5

3.6

3.7

3.8

4.0

3.9

−50 −25 0 25 50 75 100

Dri

ver

Su

pp

ly V

olt

age,

VC

C[V

]

125Driver IC Junction Temperature, TJ [oC]

UVLOUP

UVLODN

0.0

0.5

1.0

1.5

2.0

2.5

3.0

4.0

3.5

4.50 4.75 5.00 5.25

PW

M T

hre

sho

ld V

olt

age,

VP

WM

[V]

5.50Driver Supply Voltage, VCC [V]

VIH_PWMTA = 25°C

VTRI_HI_PWM

VTRI_LO_PWM

VIL_PWM

VHIZ_PWM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

4.0

3.5

−50 −25 0 25 50 75 100

PW

M T

hre

sho

ld V

olt

age,

VP

WM

[V]


VCC = 5V VIH_PWM

V TRI_HI_PWM

VTRI_LO_PWM

VIL_PWM

VHIZ_PWM

1.0

2.0

1.5

4.50 4.75 5.00 5.25

ZC

D T

hre

sho

ld V

olt

age,

VZ

CD

[V]

5.50Driver Supply Voltage, VCC [V]

V IH

TA = 25°C

V IL


NCV3025833

www.onsemi.com11



Figure 20. ZCD# Threshold vs. Temperature Figure 21. ZCD# Pull−up Current vs. Temperature

Figure 22. EN Threshold vs. Driver Supply Voltage Figure 23. EN Threshold vs. Temperature

Figure 24. EN Pull−Down Current vs. Temperature Figure 25. Boot Diode Forward Voltage vs.Temperature

0.5

1

2

1.5

−50 −25 0 25 50 75 100

ZC

D T

hre

sho

ld V

olt

age,

VZ

CD

[V]


VCC = 5V

VIH

VIL

5

7

9

11

15

13

−50 −25 0 25 50 75 100

ZC

D P

ull−

Up

Cu

rren

t, I Z

CD

_HIG

H[u

A]

125

Driver IC Junction Temperature, TJ [oC]

VCC = 5V

1.2

1.3

1.4

1.6

1.5

4.50 4.75 5.00 5.25

EN

Th

resh

old

Vo

ltag

e, V

EN

[V]

5.50

Driver Supply Voltage, VCC [V]

VIH_EN

VIL_EN

TA = 25°C

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.8

1.7

−50 −25 0 25 50 75 100

EN

Th

resh

old

Vo

ltag

e, V

EN

[V]


VIH_EN

VIL_EN

VCC = 5V

6

6.5

7

7.5

8

9

8.5

−50 0 50 100

EN

Pu

ll−

Do

wn

Cu

rren

t, I

PL

D[u

A]


VCC = 5V

300

350

400

500

450

−50 −25 0 25 50 75 100Bo

ot

Dio

de

Fo

rwar

d V

olt

age,

VF

[mV

]


IF = 10mA


NCV3025833

www.onsemi.com12



Figure 26. Driver Shutdown vs. Temperature Figure 27. Driver Quiescent Current vs.Temperature

1.5

1.75

2

2.25

2.5

3

2.75

−50 −25 0 25 50 75 100Dri

ver

Sh

ut−

Do

wn

Cu

rren

t, I S

HD

N[u

A]


VCC = 5V, EN = GND

1

1.1

1.2

1.3

1.5

1.4

−50 −25 0 25 50 75 100

Dri

ver

Qu

iesc

ent

Cu

rren

t, I C

C[m

A]


VCC = 5V, EN = High

PWM = Float

PWM = High

FUNCTIONAL DESCRIPTION

The SPS NCV3025833 is a driver-plus-MOSFET moduleoptimized for the synchronous buck converter topology.A PWM input signal is required to properly drive thehigh-side and the low-side MOSFETs. The part is capable ofdriving speed up to 1.5 MHz.

Power-On Reset (POR)The PWM input stage incorporates a POR feature to

ensure both LDRV and HDRV are forced inactive (LDRV =HDRV = 0) until UVLO > ~3.8 V (rising threshold). Afterall gate drive blocks are fully powered on and have finishedthe startup sequence, the internal driver IC EN_PWM signalis released HIGH, enabling the driver outputs. Once thedriver POR has finished (< 20 �s maximum), the driverfollows the state of the PWM signal (it is assumed that atstartup the controller is either in a high-impedance state orforcing the PWM signal to be within the driver 3-statewindow).

Three conditions below must be supported for normalstartup / power-up.• VCC rises to 5 V, then EN goes HIGH:

• EN pin is tied to the VCC pin:

• EN is commanded HIGH prior to 5 V VCC reaching theUVLO rising threshold.

Under-Voltage Lockout (UVLO)UVLO is performed on VCC only, not on PVCC or VIN.

When the EN is set HIGH and VCC is rising over the UVLOthreshold level (3.8 V), the part starts switching operationafter a maximum 20 �s POR delay. The delay isimplemented to ensure the internal circuitry is biased, stable,

and ready to operate. Two VCC pins are provided: PVCCand VCC. The gate driver circuitry is powered from thePVCC rail. The user should connect VCC to PVCC througha low-pass R−C filter. This provides a filtered 5 V bias to theanalog circuitry on the IC.

Driver State

3.83.4 VCC [V]

Disable

Enable

* EN pin keeps HIGH

Figure 28. UVLO on VCC

EN / FAULT# (Enable / Fault Flag)The driver can be disabled by pulling the EN / FAULT#

pin LOW (EN < VIL_EN), which holds both GL and GH

LOW regardless of the PWM input state. The driver can beenabled by raising the EN / FAULT# pin voltage HIGH (EN> VIH_EN). The driver IC has less than 3 �A shutdowncurrent when it is disabled. Once the driver is re-enabled, ittakes a maximum of 20 �s startup time.

EN / FAULT# pin is an open-drain output for fault flagwith an internal 250 k� pull-down resistor. Logic HIGHsignal from PWM controller or ~10 k� external pull-upresistor from EN / FAULT# pin to VCC is required to startdriver operation.


NCV3025833

www.onsemi.com13

Table 1. UVLO AND DRIVER STATE

UVLO EN Driver State

0 X Disabled (GH & GL = 0)

1 0 Disabled (GH & GL = 0)

1 1 Enabled (see Table 2)

1 Open Disabled (GH & GL = 0)

The EN / FAULT# pin has two functions; enabling /disabling driver and fault flag. The fault flag signal is activeLOW. When the driver detects a fault condition duringoperation, it turns on the open-drain on the EN / FAULT# pinand the pin voltage is pulled LOW. The fault conditions are:• High-side MOSFET false turn-on or VIN ~ SW short

during low-side MOSFET turn on:• Thermal Shutdown (THDN) when the driver internal

junction temperature (TJ) reaches 150°C.

When the driver detects a fault condition and disablesitself, a POR event on VCC is required to restart the driveroperation.

3-State PWM InputThe NCV3025833 incorporates a 3-state 5 V PWM input

gate drive design. The 3-state gate drive has both logicHIGH and LOW levels, along with a 3-state shutdownwindow. When the PWM input signal enters and remainswithin the 3-state window for a defined hold-off time(tD_HOLD−OFF), both GL and GH are pulled LOW. Thisfeature enables the gate drive to shut down both thehigh-side and the low-side MOSFETs to support featuressuch as phase shedding, a common feature on multi-phasevoltage regulators.

Table 2. EN / PWM / 3-STATE / ZCD# LOGIC STATES

EN PWM ZCD# GH GL

0 X X 0 0

1 3-State X 0 0

1 0 0 0 1 (IL > 0), 0 (IL < 0)

1 1 0 1 0

1 0 1 0 1

1 1 1 1 0

PWM

GL

GH−PHASE(intenal)

BOOT−GND

VIH_PWM

VIL_PWM

tFALL_GH

tRISE_GL

SW

tPD_PHGLL tPD_PLGHL tD_DEADOFFtD_DEADONtFALL_GL

tRISE_GH

tPD_PLGLHtPD_PHGLL = PWM HI to GL LO, VIH_PWM to 90% GLtFALL_GL = 90% GL to 10% GLtD_DEADON = LS Off to HS On Dead Time, 10% GL to VBOOT−GND ≤ PVCC − VF_DBOOT − 1V or BOOT−GND dip start pointtRISE_GH = 10% GH to 90% GH, VBOOT−GND ≤ PVCC − VF_DBOOT − 1V or BOOT−GND dip start point to GL bounce start point

tPD_PLGHL = PWM LO to GH LO, VIL_PWM to 90% GH or BOOT−GND decrease start point, tPD_PLGLH − tD_DEADOFF − tFALL_GHtFALL_GH = 90% GH to 10% GH, BOOT−GND decrease start point to 90% VSW or GL dip start pointtD_DEADOFF = HS Off to LS On Dead Time, 90% VSW or GL dip start point to 10% GLtRISE_GL = 10% GL to 90% GLtPD_PLGLH = PWM LO to GL HI, VIL_PWM to 10% GL

Figure 30. PWM Timing Diagram

90% 90%

90% 90%

10% 10%

10% 10%

90%

PVCC − VF_DBOOT − 1 V


NCV3025833

www.onsemi.com14

VIH_PWM

VTRI_HI

VTRI_LO

VIL_PWM

3−StateWindow

3−StateWindow

VIH_PWM

VTRI_HI

VTRI_LO

VIL_PWM

PWM

GH−PHASE

GL

Figure 31. PWM Threshold DefinitionNOTE:8. The timing diagram in Figure 31 assumes very slow ramp on PWM.9. Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> tD_HOLD−OFF.10.VTRI_HI = PWM trip level to enter 3-state on PWM falling edge.11. VTRI_LO = PWM trip level to enter 3-state on PWM rising edge.12.VIH_PWM = PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.13.VIL_PWM = PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.

(8) (8)

(12)

(9) (9)

(10)

(11)

(13)

Power SequenceSPS NCV3025833 requires four (4) input signals to

conduct normal switching operation: VIN, VCC / PVCC,PWM, and EN. PWM should not be applied before VCC andthe amplitude of PWM should not be higher than VCC. Thebelow example of a power sequence is for a referenceapplication design:• From no input signals

♦ VIN On: Typical 12 VDC♦ VCC / PVCC On: Typical 5 VDC♦ EN HIGH: Typical 5 VDC♦ PWM Signaling: 5 V HIGH / 0 V LOW

The VIN pins are tied to the system main DC power rail.PVCC and VCC pins are tied together to supply gate

driving and logic circuit powers from the system VCC rail.Or the PVCC pin can be directly tied to the system VCC rail,and the VCC pin is powered by PVCC pin through a filterresistor located between PVCC pin and VCC pin. The filterresistor reduces switching noise impact from PVCC to VCC.

The EN pin can be tied to the VCC rail with an externalpull-up resistor and it will maintain HIGH once the VCC railturns on. Or the EN pin can be directly tied to the PWMcontroller for other purposes.

High-Side DriverThe high-side driver (HDRV) is designed to drive

a floating N-channel MOSFET (Q1). The bias voltage forthe high-side driver is developed by a bootstrap supplycircuit, consisting of the internal Schottky diode andexternal bootstrap capacitor (CBOOT). During startup, theSW node is held at PGND, allowing CBOOT to charge to

PVCC through the internal bootstrap diode. When the PWMinput goes HIGH, HDRV begins to charge the gate of thehigh-side MOSFET (internal GH pin). During thistransition, the charge is removed from the CBOOT anddelivered to the gate of Q1. As Q1 turns on, SW rises to VIN

,

forcing the BOOT pin to VIN + VBOOT, which providessufficient VGS enhancement for Q1. To complete theswitching cycle, Q1 is turned off by pulling HDRV to SW.CBOOT is then recharged to PVCC when the SW falls toPGND. HDRV output is in phase with the PWM input. Thehigh-side gate is held LOW when the driver is disabled or thePWM signal is held within the 3-state window for longerthan the 3-state hold-off time, tD_HOLD−OFF.

Low-Side DriverThe low-side driver (LDRV) is designed to drive the

gate-source of a ground-referenced, low-RDS(ON),

N-channel MOSFET (Q2). The bias for LDRV is internallyconnected between the PVCC and AGND. When the driveris enabled, the driver output is 180° out of phase with thePWM input. When the driver is disabled (EN = 0 V), LDRVis held LOW.

Continuous Current Mode 2 (CCM2) OperationA main feature of the low-side driver design in SPS

NCV3025833 is the ability to control the part of the low-side gate driver upon detection of negative inductor current,called CCM2 operation. This is accomplished by using theZCD comparator signal. The primary reason for scalingback on the drive strength is to limit the peak VDS stresswhen the low-side MOSFET hard-switches inductorcurrent. This peak VDS stress has been an issue with


NCV3025833

www.onsemi.com15

applications with large amounts of load transient and fastand wide output voltage regulation.

The MOSFET gate driver in SPS NCV3025833 operatesin one of three modes, described below.

Continuous Current Mode 1 (CCM1) with PositiveInductor Current

In this mode, inductor current is always flowing towardsthe output capacitor, typical of a heavily loaded power stage.The high-side MOSFET turns on with the low-side bodydiode conducting inductor current and SW is approximatelyVF below ground, meaning hard-switched turn on and offthe high-side MOSFET.

Discontinuous Current Mode (DCM)Typical of lightly loaded power stage; the high-side

MOSFET turns on with zero inductor current, ramps theinductor current, then returns to zero every switching cycle.When the high-side MOSFET turns on under DCMoperation, the SW node may be at any voltage from a VFbelow ground to a VF above VIN. This is because after thelow-side MOSFET turns off, the SW node capacitanceresonates with the inductor current.

The level shifter in driver IC should be able to turn on thehigh-side MOSFET regardless of the SW node voltage. Inthis case, the high-side MOSFET turns off a positive current.

During this mode, both LDRV1 and LDRV2 operate inparallel and the low-side gate driver pull-up and pull-downresistors are operating at full strength.

Continuous Current Mode 2 (CCM2) with NegativeInductor Current

This mode is typical in a synchronous buck converterpulling energy from the output capacitors and delivering theenergy to the input capacitors (Boost Mode). In this mode,the inductor current is negative (meaning towards theMOSFETs) when the low-side MOSFET is turned off (maybe negative when the high-side MOSFET turns on as well).This situation causes the low-side MOSFET to hard switchwhile the high-side MOSFET acts as a synchronous rectifier(temporarily operated in synchronous Boost Mode).

During this mode, only the “weak” LDRV2 is used forlow-side MOSFET turn-on and turn-off. The intention is toslow down the low-side MOSFET switching speed when itis hard switching to reduce peak VDS stress.

Dead-Times in CCM1 / DCM / CCM2The driver IC design ensures minimum MOSFET dead

times, while eliminating potential shoot-through (cross-conduction) currents. To ensure optimal module efficiency,body diode conduction times must be reduced to the lownano-second range during CCM1 and DCM operation.

CCM2 alters the gate drive impedance while operating thepower MOSFETs in a different mode versus CCM1 / DCM.Altered dead-time operation must be considered.

Low-Side MOSFET Off to High-Side MOSFET On DeadTime in CCM1 / DCM

To prevent overlap during the low-side MOSFET off tohigh-side MOSFET on switching transition, an adaptivecircuitry monitors the voltage at the GL pin. When the PWMsignal goes HIGH, GL goes LOW after a propagation delay(tPD_PHGLL). Once the GL pin is discharged below ~ 1 – 2 V,GH is pulled HIGH after an adaptive delay, tD_DEADON.

Some situations where the ZCD# rising-edge signal leadsthe PWM rising edge by tens of nanoseconds, can cause GHand GL overlap. This event can occur when the PWMcontroller sends PWM and ZCD# signals that lead, lag, orare synchronized. To avoid this phenomenon, a secondaryfixed propagation delay (tFD_ON1) is added to ensure thereis always a minimum delay between low-side MOSFET offto high-side MOSFET on.

Low-Side MOSFET Off to High-Side MOSFET On DeadTime in CCM2

As noted in the CCM2 Operation section, the low-sidedriver strength is scale-able upon detection of CCM2.CCM2 feature slows the charge and discharge of thelow-side MOSFET gate to minimize peak switching voltageovershoots during low-side MOSFET hardswitching(negative inductor current). To avoid cross-conduction, theslowing of the low-side gate also requires an adjustment(increase) of the dead time between low-side MOSFET offto high-side MOSFET on. A fairly long fixed dead time(tFD_ON2) is implemented to ensure there is no crossconduction during this CCM2 operation.

High-Side MOSFET Off to Low-Side MOSFET On DeadTime in CCM1 / DCM

To get very short dead time during high-side MOSFET offto low-side MOSFET on transition, a fixed dead timemethod is implemented in the SPS gate driver. Thefixed-dead-time circuitry monitors the internal HS signaland adds a fixed delay long enough to gate on GL aftera desired tD_DEADOFF (~5 ns, tD_DEADOFF = tFD_OFF1) regardlessof SW node state.

Exiting 3-State ConditionWhen exiting a valid 3-state condition, the gate driver of

the NCV3025833 follows the PWM input command. If thePWM input goes from 3-state to LOW, the low-sideMOSFET is turned on. If the PWM input goes from 3- stateto HIGH, the high-side MOSFET is turned on. This isillustrated in Figure 32 below.


NCV3025833

www.onsemi.com16

VIH_PWM

VIL_PWM

VTRI_HI

VTRI_LO

VIH_PWM

3−StateWindow

VTRI_HI

VTRI_LO

VIH_PWM VTRI_HI

VIL_PWMVIL_PWM

10%10%

10%

90%

90%

10% 10%

90%

10% 10%

tPD_PHGLL

tD_DEADON

tPD_PLGHL

tD_DEADOFF

tPD_PHGLL

tD_DEADON2 tD_HOLD−OFF

tPD_THGHH tPD_TLGLH

Less thantD_HOLD−OFF

Less thantD_HOLD−OFF

GL / GHoff

GL / GHoff

tD_HOLD−OFF

3−Statet HOLD_OFF

Window

3−Statet HOLD_OFF

Window

InductorCurrent

PWM

SW

GL

GH to SW

tPD_XXX = propagation delay from external signal (PWM, ZCD#, etc.) to IC generated signal. Example : tPD_PHGLL – PWM going HIGH tolow-side MOSFET VGS (GL) going LOWtD_XXX = delay from IC generated signal to IC generated signal. Example: tD_DEADON – low-side MOSFET VGS LOW to high-side MOSFET VGS HIGH

PWMtPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGStPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGStPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (ZCD# held LOW)

ZCD#tPD_ZLGLL = ZCD# fall to LS VGS fall, VIL_ZCD# to 90% LS VGStPD_ZHGLH = ZCD# rise to LS VGS rise, VIH_ZCD# to 10% LS VGS

Exiting 3-StatetPD_TSGHH = PWM 3-State to HIGH to HS VGS rise, VIH_PWM to 10% HS VGStPD_TSGLH = PWM 3-State to LOW to LS VGS rise, VIL_PWM to 10% LS VGS

Dead TimestD_DEADON = LS VGS fall to HS VGS rise, LS-Comp trip value to 10% HS VGStD_DEADOFF = SW fall to LS VGS rise, SW-Comp trip value to 10% LS VGS

NOTES:

Figure 32. PWM HIGH / LOW / 3-State Timing Diagram


NCV3025833

www.onsemi.com17

Exiting 3-State with Low BOOT−SW VoltageThe SPS module is used in multi-phase VR topologies

requiring the module to wait in 3-state condition for anindefinite time. These long idle times can bleed the bootcapacitor down until eventual clamping occurs based onPVCC and VOUT. Low BOOT−SW can cause increasedpropagation delays in the level-shift circuit as well as allHDRV floating circuitry, which is biased from theBOOT−SW rail. Another issue with a depleted BOOT−SWcapacitor voltage is the voltage applied to the HS MOSFETgate during turn-on. A low BOOT−SW voltage results ina very weak HS gate drive, hence, much larger HS RDS(ON)and increased risk for unreliable operation since the HSMOSFET may not turn-on if BOOT−SW falls too low.

To address this issue, the SPS monitors for a lowBOOT−SW voltage when the module is in 3-state condition.When the module exits 3-state condition with a lowBOOT−SW voltage, a 100 ns minimum GL on time is outputregardless of the PWM input. This ensures the bootcapacitor is adequately charged to a safe operating level andhas minimal impact on transient response of the system.Scenarios of exiting 3-state condition are listed below.

• If the part exits 3-state with a low BOOT−SW voltagecondition and the controller commands PWM = HIGH,the SPS outputs a 100 ns GL pulse and follows thePWM = HIGH command (see Figure 33).

• If the part exits 3-state with a low BOOT−SW voltagecondition and the controller commands PWM = LOWfor 100 ns or more, the SPS follows the PWM input. IfPWM = LOW for less than 100 ns, GL remains on for100 ns then follows the PWM input (see Figure 34 andFigure 35).

• If no low BOOT−SW condition is detected, the SPSfollows the PWM command when exiting 3-state(see Figure 36).

The SPS momentarily stays in an adaptive dead timemode when exiting 3-state condition or at initial power-up.This adaptive dead time mode lasts for no more than two (2)consecutive switching cycles, giving the boot capacitorample time to recharge to a safe level. The module switchesback to fixed dead time control for maximum efficiency.

Figure 33. Low BOOT−SW Voltage Detected andPWM from 3-State to HIGH

Low BOOT−SW voltage detected

PWM

GH toPHASE

LOWBOOT−SW

detect

GL / GHoff

VIH_PWM

100 nsGL pulse

GL

Figure 34. Low BOOT−SW Voltage Detected andPWM from 3-State to LOW for more than 100 ns


PWM

GH toPHASE

LOWBOOT−SW

detect

GL / GHoff

VIL_PWM

> 100 nsGL pulse

GL

PWM LOW> 100 ns

Figure 35. Low BOOT−SW voltage Detected and PWM from 3-State to LOW for Less than 100 ns


PWM

GH toPHASE

LOWBOOT−SW

detect

GL / GHoff

VIL_PWM

100 nsGL pulse

GL

PWM LOW< 100 ns

I

Figure 36. Low BOOT−SW Voltage NOT Detected andPWM from 3-State to HIGH or LOW

Low BOOT−SW voltage NOT detected

PWM

GH toPHASE

LOWBOOT−SW

detect

GL / GHoff

VIL_PWM

GL

VIH_PWM

GL / GHoff


NCV3025833

www.onsemi.com18

Zero Cross Detect (ZCD) OperationThe ZCD control block houses the circuitry that

determines when the inductor current reverses direction andcontrols when to turn off the low-side MOSFET. A lowoffset comparator monitors the SW-to-PGND voltage of thelow-side MOSFET during the LS MOSFET on-time. Whenthe sensed voltage switches polarity from negative topositive, the comparator changes state and reverse currenthas been detected. This comparator offset must sense thenegative VSW within a 0.5 mV worst-case range. The

negative offset is to ensure the inductor current neverreverses; some small body-diode conduction is preferable tohaving negative current.

The comparator is switched on after the rising edge of thelow-side gate drive and turned off by the signal at the inputto the low-side gate driver. In this way, the zero-currentcomparator is connected with a break-before-makeconnection, allowing the comparator to be designed with alllow-voltage transistors.

Figure 37. ZCD# & PWM Timing Diagram

PWM

ZCD#

GH toSW

GL

SW

InductorCurrent(simplified

slopes)

SW(zoom)

VIH_ZCD#

tPD_PHGLL

VIL_ZCD#

VIH_PWMVIH_PWMVIH_PWM

VIL_PWM

10%

90%

90%

10%

tD_DEADON

tPD_PLGHL

tD_DEADOFF

tPD_PHGLL

tD_DEADON2

tPD_ZCD

10%

10%

90%

tPD_PHGHH

10%

Delay from PWM goingHIGH to HS VGS HIGH(HS turn−on in DCM)

90%

10%

90%

tPD_ZHGLH tPD_ZLGLL

Delay from ZCD# goingHIGH to LS VGS HIGH

Delay from ZCD# goingLOW to LS VGS LOW

VIN

VOUTCCM

CCM(Negative inductor current) DCM DCM

CCM operation withpositive inductor current

CCM operation withnegative inductor current

DCM operation: DiodeEmulation using the GL (LSMOSFET VGS) to eliminatenegative inductor current

DCM operation: DiodeEmulation using the GL (LSMOSFET VGS) to eliminatenegative inductor current

ZCD# used tocontrol negativeinductor current(fault condition)

VZCD_OFF :−0.5 mV

Thermal Warning Flag (THWN#)The NCV3025833 provides a thermal warning (THWN)

for over-temperature conditions. The THWN flag pullsTHWN# pin LOW (to AGND) if the driver IC detects the125°C activation temperature. The THWN# pin outputreturns to high-impedance state once the temperature falls tothe 110°C reset temperature. Figure 38 shows the THWN#operation. THWN does not disable the SPS module andworks independently of other features.

The THWN mode of operation requires a pull-up resistorto VCC rail. THWN# flag is active LOW.

Thermal Shutdown (THDN)A programmed thermal shutdown engages once the driver

TJ reaches 150°C. The shutdown event is a latched shutdown, where the THDN signal clocks the fault latch andphysically pulls down the EN pin.

Recycling 5 V VCC (POR event) is required to re-enablethe driver IC.

110 125 T

0

5

VTHWN#

[V]

Figure 38. Gate Driver TJ vs. VTHWN#

[°C]* RTHWN# = 10 k� to 5 VCC


NCV3025833

www.onsemi.com19

The 150°C THDN feature is combined with a 125°CTHWN# flag. If the driver temperature reaches 125°C, theTHWN# pin is pulled LOW. If the driver continuesoperation and its temperature increases up to 150°C, thermalshutdown is activated. The SPS module is shut down by ENLOW and the THWN# flag is de-asserted, so the VTHWN#returns HIGH. Figure 40 shows the relationship amongTHWN#, EN, and driver temperature.

Figure 40. VTHWN#, VEN vs. Driver Temperature

0

5

0

5

125 150 TJ

VTHWN#

[V]

VEN [V]

[°C]

* RTHWN# = 10 k� to 5 VCC* REN = 10 k� to 5 VCC

Catastrophic FaultSPS NCV3025833 includes a catastrophic fault feature. If

a HS MOSFET short is detected, the driver internally pullsthe EN / FAULT# pin LOW and shuts down the SPS driver.The intention is to implement a basic circuit to test the HSMOSFET short by monitoring LDRV and the state of SWnode.

If a HS short fault is detected, the SPS module clocks thefault latch shutting down the module. The module requiresa VCC POR event to restart.

PWM

LDRV(internal)

SW

SW−Fault(internal)

FAULT(internal)

EN/FAULT#

Potential noise fromadjacent phases switching

HS FET short duringLS FET turning on

false trigger

Normal switching operation EN/FAULT#pulled LOW and

driver IC disabled

Figure 42. Catastrophic Fault Waveform


NCV3025833

www.onsemi.com20

APPLICATION INFORMATION

Decoupling Capacitor for PVCC & VCCFor the supply inputs (PVCC and VCC pins), local

decoupling capacitors are required to supply the peakdriving current and to reduce noise during switchingoperation. Use at least 0.68 ~ 1 �F / 0402 ~ 0603 / X5R ~X7R multi-layer ceramic capacitors for both power rails.Keep these capacitors close to the PVCC and VCC pins andPGND and AGND copper planes. If they need to be locatedon the bottom side of board, put through-hole vias on eachpads of the decoupling capacitors to connect the capacitorpads on bottom with PVCC and VCC pins on top.

The supply voltage range on PVCC and VCC is 4.5 V ~5.5 V, and typically 5 V for normal applications.

R−C Filter on VCCThe PVCC pin provides power to the gate drive of the

high-side and low-side power MOSFETs. In most cases,PVCC can be connected directly to VCC, which is the pinthat provides power to the analog and logic blocks of thedriver. To avoid switching noise injection from PVCC intoVCC, a filter resistor can be inserted between PVCC andVCC decoupling capacitors.

Recommended filter resistor value range is 0 ~ 10 �,typically 0 � for most applications.

Bootstrap CircuitThe bootstrap circuit uses a charge storage capacitor

(CBOOT). A bootstrap capacitor of 0.1 ~ 0.22 �F / 0402 ~0603 / X5R ~ X7R is usually appropriate for most switchingapplications. A series bootstrap resistor may be needed forspecific applications to lower high-side MOSFET switchingspeed. The boot resistor is required when the SPS isswitching above 15 V VIN; when it is effective at controllingVSW overshoot. RBOOT value from zero to 6 � is typicallyrecommended to reduce excessive voltage spike and ringingon the SW node. A higher RBOOT value can cause lowerefficiency due to high switching loss of high-side MOSFET.

Do not add a capacitor or resistor between the BOOT pinand GND.

EN / FAULT# (Input / Output)The driver in SPS is enabled by pulling the EN pin HIGH.

The EN pin has internal 250 k� pull-down resistor, so itneeds to be pulled-up to VCC with an external resistor orconnected to the controller or system to follow up thecommand from them. If the EN pin is floated, it cannot turnon the driver.

The fault flag LOW signal is asserted on the EN / FAULT#pin when the driver temperature reaches THDN temperatureor a high-side MOSFET fault occurs. Then the driver shutsdown.

The typical pull-up resistor value on EN ~ VCC is 10 k�.Do not add a noise filter capacitor on the EN pin.

PWM (Input)The PWM pin recognizes three different logic levels from

PWM controller: HIGH, LOW, and 3-state. When the PWMpin receives a HIGH command, the gate driver turns on thehigh-side MOSFET. When the PWM pin receives a LOWcommand, the gate driver turns on the low-side MOSFET.When the PWM pin receives a voltage signal inside of the3-state window (VTRI_Window) and exceeds the 3-statehold-off time, the gate driver turns off both high-side andlow-side MOSFETs. To recognize the high-impedance3-state signal from the controller, the PWM pin has aninternal resistor divider from VCC to PWM to AGND. Theresistor divider sets a voltage level on the PWM pin insidethe 3-state window when the PWM signal from thecontroller is high-impedance.

ZCD# (Input)When the ZCD# pin sets HIGH, the ZCD function is

disabled and high-side and low-side MOSFETs switch inCCM (or FCCM, Forced CCM) by PWM signal. When theZCD# pin is LOW, the low-side MOSFET turns off when theSPS driver detects negative inductor current during thelow-side MOSFET turn-on period. This ZCD feature allowshigher converter efficiency under light-load condition andPFM / DCM operation.

The ZCD# pin has an internal current source from VCC,so it may not need an external pull-up resistor. Once VCC issupplied and the driver is enabled, the ZCD# pin holds logicHIGH without external components and the driver operatesswitching in CCM or FCCM. The ZCD# pin can begrounded for automatic diode emulation in DCM by the SPSitself, or it can be connected to the controller or system tofollow the command from them.

The typical pull-up resistor value on ZCD# ~ VCC is10 k� for stable ZCD# HIGH level. If not using the ZCDfeature, tie the ZCD# pin to VCC with a pull-up resistor. Donot add any noise filter capacitor on the ZCD# pin.

THWN# (Output) / THDNThe THWN# pin is an open-drain, so needs an external

pull-up resistor to VCC. If the driver temperature reaches125°C, the VTHWN# is pulled LOW. When the driver TJcools to less than 110°C, the VTHWN# returns HIGH. ThisTHWN# flag operates when the driver TJ is below 150°C.

If the driver TJ continuously increases over 150°C afterasserting the 125°C THWN flag, the thermal shutdownfeature activates and the SPS module is turned off. Thisshutdown is a latch function, so the driver remains shutdown even if its temperature cools down to 25°C. The SPSmodule needs to be re-enabled by VCC POR once the THDNis activated.


NCV3025833

www.onsemi.com21

A typical pull-up resistor on THWN# ~ VCC is 10 k�. Ifnot using THWN#/THDN features, tie THWN# to GND. Donot add a noise filter capacitor on the THWN# pin.

Power Loss and EfficiencyFigure 43 shows an example diagram for power loss and

efficiency measurement.

Power loss calculation and equation examples:PIN = (VIN ∗ IIN) + (VCC ∗ ICC) [W]PSW = VSW ∗ IOUT [W]POUT = VOUT ∗ IOUT [W]PLOSS_MODULE = PIN – PSW [W]PLOSS_TOTAL = PIN – POUT [W]EFFIMODULE = (PSW / PIN) ∗ 100 [%]EFFITOTAL = (POUT / PIN) ∗ 100 [%]

PVCC

VCC

VIN

VOUT

PowerSupply 1

PowerSupply 2

PulseGenerator

PWM

ElectronicLoad

VIN / IIN

VCC / ICC

VOUT / IOUT

HS GD

LS VSW / IOUT

ON Semiconductor SPS

Evaluation Board

Figure 43. Power Loss and Efficiency Measurement Diagram


NCV3025833

www.onsemi.com22

PCB LAYOUT GUIDELINE

Figure 44 through Figure 47 provide examples of single-phase and multi-phase layouts for the NCV3025833 andcritical components. All of the high-current paths; such asVIN, SW, VOUT, and GND coppers; should be short andwide for low parasitic inductance and resistance. This helpsachieve a more stable and evenly distributed current flow,along with enhanced heat radiation and systemperformance.

Input ceramic bypass capacitors must be close to the VINand PGND pins. This reduces the high-current power loopinductance and the input current ripple induced by the powerMOSFET switching operation.

The SW copper trace serves two purposes. In addition tobeing the high-frequency current path from the SPS packageto the output inductor, it serves as a heat sink for the low-sideMOSFET. The trace should be short and wide enough topresent a low-impedance path for the high-frequency,high-current flow between the SPS and the inductor. Theshort and wide trace minimizes electrical losses and SPStemperature rise. The SW node is a high-voltage andhigh-frequency switching node with high noise potential.Care should be taken to minimize coupling to adjacenttraces. Since this copper trace acts as a heat sink for thelow-side MOSFET, balance using the largest area possibleto improve SPS cooling while maintaining acceptable noiseemission.

An output inductor should be located close to theNCV3025833 to minimize the power loss due to the SWcopper trace. Care should also be taken so the inductordissipation does not heat the SPS.

POWERTRENCH MOSFETs are used in the output stageand are effective at minimizing ringing due to fast switching.In most cases, no RC snubber on SW node is required. Ifa snubber is used, it should be placed close to the SW andPGND pins. The resistor and capacitor of the snubber mustbe sized properly to not generate excessive heating due tohigh power dissipation.

Decoupling capacitors on PVCC, VCC, and BOOTcapacitors should be placed as close as possible to the PVCC~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin pairs toensure clean and stable power supply. Their routing tracesshould be wide and short to minimize parasitic PCBresistance and inductance.

The board layout should include a placeholder forsmall-value series boot resistor on BOOT ~ PHASE. Theboot-loop size, including series RBOOT and CBOOT, shouldbe as small as possible.

A boot resistor may be required when the SPS is operatingabove 15 V VIN and it is effective to control the high-side

MOSFET turn-on slew rate and SW voltage overshoot.RBOOT can improve noise operating margin in synchronousbuck designs that may have noise issues due to groundbounce or high positive and negative VSW ringing. Insertinga boot resistance lowers the SPS module efficiency.Efficiency versus switching noise must be considered.RBOOT values from 0.5 � to 0.6 � are typically effective inreducing VSW overshoot.

The VIN and PGND pins handle large current transientswith frequency components greater than 100 MHz. Ifpossible, these pins should be connected directly to the VINand board GND planes. The use of thermal relief traces inseries with these pins is not recommended since this addsextra parasitic inductance to the power path. This addedinductance in series with either the VIN or PGND pindegrades system noise immunity by increasing positive andnegative VSW ringing.

PGND pad and pins should be connected to the GNDcopper plane with multiple vias for stable grounding. Poorgrounding can create a noisy and transient offset voltagelevel between PGND and AGND. This could lead to faultyoperation of gate driver and MOSFETs.

Ringing at the BOOT pin is most effectively controlled byclose placement of the boot capacitor. Do not add anyadditional capacitors between BOOT to PGND. This maylead to excess current flow through the BOOT diode,causing high power dissipation.

The ZCD# and EN pins have weak internal pull-up andpull-down current sources, respectively. These pins shouldnot have any noise filter capacitors. Do not float these pinsunless absolutely necessary.

Put multiple vias on the VIN and VOUT copper areas tointerconnect top, inner, and bottom layers to evenlydistribute current flow and heat conduction. Do not put toomany vias on the SW copper to avoid extra parasiticinductance and noise on the switching waveform. As long asefficiency and thermal performance are acceptable, placeonly one SW node copper on the top layer and put no vias onthe SW copper to minimize switch node parasitic noise. Viasshould be relatively large and of reasonably low inductance.Critical high-frequency components; such as RBOOT,CBOOT, RC snubber, and bypass capacitors; should belocated as close to the respective SPS module pins aspossible on the top layer of the PCB. If this is not feasible,they can be placed on the board bottom side and their pinsconnected from bottom to top through a network oflow-inductance vias.


NCV3025833

www.onsemi.com23

PCB LAYOUT GUIDELINE

Figure 44. Single-Phase Board Layout Example – Top View

Figure 45. Single-Phase Board Layout Example – Bottom View (Mirrored)


NCV3025833

www.onsemi.com24

PCB LAYOUT GUIDELINE (continued)

Figure 46. 6-Phase Board Layout Example with 6 mm x 6 mm Inductor – Top View

Figure 47. 6-Phase Board Layout Example with 6 mm x 6 mm Inductor – Bottom View (Mirrored)


NCV3025833

www.onsemi.com25

PACKAGE MARKING AND ORDERING INFORMATION

Part Number Top Marking Current Rating Package Shipping (Qty / Packing)†

NCV3025833MTW NCV3025833

50 A 31-Lead, Clip Bond WQFN31 5x5, 0.5P(Pb-Free/Halogen Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

POWERTRENCH is registered trademark and SyncFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or itssubsidiaries in the United States and/or other countries.


NCV3025833

www.onsemi.com26

PACKAGE DIMENSIONS

WQFNW33, 5x5, 0.5PCASE 512AE

ISSUE A

A

B

8

1

9

23

16

31 24

15

32

33

8

1

9

23

16

31 24

15

32

33

EXPOSED COPPER


NCV3025833

www.onsemi.com27

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patentcoverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customerapplication by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classificationin a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. Thisliterature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATIONTECHNICAL SUPPORTNorth American Technical Support:Voice Mail: 1 800−282−9855 Toll Free USA/CanadaPhone: 011 421 33 790 2910

LITERATURE FULFILLMENT:Email Requests to: [email protected]

ON Semiconductor Website: www.onsemi.com

Europe, Middle East and Africa Technical Support:Phone: 00421 33 790 2910For additional information, please contact your local Sales Representative

◊


www.onsemi.com/site/pdf/Patent-Marking.pdf

NCV3025833 - Smart Power Stage (SPS) Module with ...

Documents

Transcript of NCV3025833 - Smart Power Stage (SPS) Module with ...