NCP3155 - Synchronous Buck Regulator · CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div Time...

© Semiconductor Components Industries, LLC, 2012

February, 2012 − Rev. 31 Publication Order Number:

NCP3155/D

NCP3155A, NCP3155B

3 A Synchronous BuckRegulator

The NCP3155 is a DC/DC synchronous switching regulator withfully integrated power switches and full fault protection. Theswitching frequency of 1 MHz and 500 kHz allows the use of smallfilter components, which results in smaller board space and reducedBOM cost. Available in a SOIC-8 package.

Features• Input Voltage Range from 4.7 V to 24 V

• Adjustable Output Voltage

• 1 MHz Operation (NCP3155A – 500 kHz)

• Internally Programmed 1.2 ms Soft−Start (NCP3155A – 2.4 ms)

• 0.8 ± 1.0% Reference Voltage

• 48 m� HS−FET and 18 m� LS−FET

• Current Limit Protection

• Transconductance Amplifier with External Compensation

• Input Undervoltage Lockout

• Output Overvoltage and Undervoltage Detection

• These are Pb−Free Devices

Typical Applications• Set Top Boxes

• DVD Drives and HDD

• LCD Monitors and TVs

• Cable Modems

• Telecom/Networking/Datacom Equipment

Figure 1. Typical Application Circuit

NCP3155FB1

4.7 V − 24 VBST VSW

PGND

AGND

ISET

COMP

VIN VOUT

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SOIC−8 NBCASE 751

MARKING DIAGRAM

3155xALYW

�

1

8

1

8

PIN CONNECTIONS

FBCOMP

AGNDBST

ISETVIN

VSWPGND

(Top View)

Device Package Shipping†

ORDERING INFORMATION

NCP3155ADR2G SOIC−8(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.

NCP3155BDR2G SOIC−8(Pb−Free)

2500 / Tape & Reel

3155x = Specific Device Codex = A or B

A = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

NCP3155A, NCP3155B

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GATEDRIVELOGIC

VC

CLK/DMAX/SOFTSTART

OOV

BOOSTACTIVE

LEVELSHIFT

SAMPLE &HOLD

VC

HSDRV

PGND

AGND

−+

−+

−+

VIN

COMP

FB

REF

RAMP

OSCILLATOR

BST

VSWVIN

Figure 2. NCP3155 Block Diagram

INTERNAL BIAS

ISET1.5 V

THERMAL SD

POR/STARTUP

OUV

CURRENTLIMIT

VIN

ISET

LSDRV

PIN FUNCTION DESCRIPTION

Pin Pin Name Description

1 PGND The PGND pin is the high current ground pin for the lower MOSFET and drivers which should be soldered to alarge copper area to reduce thermal resistance.

2 VIN The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN pinis also connected to the internal power NMOS switch. It is also used in conjunction with the VSW pin to sensecurrent in the high side MOSFET. The VIN pin has high dI/dt edges and must be decoupled to PGND pin closeto the pin of the device.

3 BST Supply rail for the floating top gate driver. Connect a capacitor (CBST) between this pin and the VSW pin. Typ-ical values for CBST range from 1 nF to 100 nF.

4 COMP Compensation pin. The comp pin is the output of the transconductance amplifier and the non−inverting input ofthe PWM comparator. The comp pin in conjunction with the FB pin are used to compensate the voltage−controlfeedback loop.

5 FB Inverting input to the Operational Transconductance Amplifier (OTA). The FB pin in conjunction with the extern-al compensation serves to stabilize and achieve the desired output voltage with voltage mode compensation.

6 AGND The AGND pin serves as small−signal ground. All small−signal ground paths should connect to the AGND pinat a single point to avoid any high current ground returns.

7 ISET Bottom gate MOSFET driver pin and the internal current set pin. Place a resistor to ground to set the currentlimit of the converter.

8 VSW The VSW pin is the connection of the drain and source of the internal N MOSFETS. The VSW pin swings fromVIN when the high side switch is on to small negative voltages when the low side switch is on with high dV/dttransitions.

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ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted)

Rating Symbol VMAX VMIN Unit

Main Supply Voltage Input VCC 26.4 −0.3 V

Boost to VSW differential voltage BST−VSW 13.2 −0.3 V

High Side Drive Boost Pin BST 45 −0.3 V

Switch Voltage Node VSW 30 −0.6 V

Transconductance Amplifier Output COMP 5.5 −0.3 V

Feedback FB 6.0 −0.3 V

Current Limit Set ISET 13.2 −0.3 V

Operating Junction Temperature Range (Note 1) TJ −40 to +125 °C

Maximum Junction Temperature TJ(MAX) +150 °C

Storage Temperature Range Tstg −55 to +150 °C

Thermal Characteristics − SOIC−8 Package (Note 2)Thermal Resistance Junction−to−Air (Note 3) R�JA

110170 °C/W

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free (Note 3)

RF 260 Peak °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. The maximum package power dissipation limit must not be exceeded.

PD �TJ(max) � TA

R�JA

2. The value of �JA is measured with the device mounted on 1 in2 FR�4 board with 1 oz. copper, in a still air environment with TA = 25°C. Thevalue in any given application depends on the user’s specific board design.

3. The value of �JA is measured with the device mounted on minimum footprint, in a still air environment with TA = 25°C. The value in any givenapplication depends on the user’s specific board design.

NCP3155A, NCP3155B

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted)

Characteristic Conditions Min Typ Max Unit

Input Voltage Range − 4.7 24 V

SUPPLY CURRENT

VCC Supply Current NCP3155A VFB = 0.8 V, Switching, VCC = 4.7 V − 11.1 − mA

VFB = 0.8 V, Switching, VCC = 24 V − 31.5 − mA

VCC Supply Current NCP3155B VFB = 0.8 V, Switching, VCC = 4.7 V − 16.5 − mA

VFB = 0.8 V, Switching, VCC = 24 V − 54.7 − mA

UNDER VOLTAGE LOCKOUT

UVLO Rising Threshold VCC Rising Edge 4.0 4.3 4.7 V

UVLO Falling Threshold VCC Falling Edge 3.5 3.9 4.3 V

OSCILLATOR

Oscillator Frequency NCP3155A TJ = +25°C, 4.7 V � VCC � 24 V 415 500 585 kHz

TJ = −40°C to +125°C, 4.7 V � VCC � 24 V 400 500 600 kHz

Oscillator Frequency NCP3155B TJ = +25°C, 4.7 V � VCC � 24 V 830 1000 1170 kHz

TJ = −40°C to +125°C, 4.7 V � VCC � 24 V 820 1000 1180 kHz

Ramp−Amplitude Voltage Vpeak − Valley − 1.5 − V

Ramp Valley Voltage 0.46 0.71 0.85 V

PWM

Minimum Duty Cycle (Note 4) − 7.0 − %

Maximum Duty Cycle 80 84 − %

Soft Start Ramp Time NCP3155ANCP3155B

VFB = VCOMP −−

2.41.2

−−

ms

ERROR AMPLIFIER (GM)

Transconductance 0.9 1.3 1.9 mS

Open Loop dc Gain (Notes 4 and 6) − 70 − dB

Output Source Current VFB = 750 mV 45 70 100 �A

Output Sink Current VFB = 850 mV 45 70 100 �A

FB Input Bias Current − 0.5 500 nA

Feedback Voltage TJ = 25 C4.7 V < VIN < 24 V, −40°C < TJ < +125°C

0.7920.784

0.80.8

0.8080.816

VV

COMP High Voltage VFB = 750 mV 4.0 4.4 5.0 V

COMP Low Voltage VFB = 850 mV − 72 250 mV

OUTPUT VOLTAGE FAULTS

Feedback OOV Threshold 0.91 1.00 1.09 V

Feedback OUV Threshold 0.56 0.60 0.64 V

PWM OUTPUT STAGE

High−Side Switch On Resistance VIN = 12 VVIN = 4.7 V

−−

4865

6385

m�

Low−Side Switch On Resistance VIN = 12 VVIN = 4.7 V

−−

1821

3550

m�

OVERCURRENT

ISET Source Current 7 13.5 18 �A

Current Limit Set Voltage (Note 5) RSET = 22.1 k� − 298 − mV

THERMAL SHUTDOWN

Thermal Shutdown (Notes 4 and 7) − 175 − °CHysteresis (Notes 4 and 7) − 20 − °C

4. Guaranteed by design.5. The voltage sensed across the high side MOSFET during conduction.6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 M�.7. This is not a protection feature.

NCP3155A, NCP3155B

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TYPICAL PERFORMANCE CHARACTERISTICS

0

10

20

30

40

50

60

70

80

90

100

0 0.5 1 1.5 2 2.5 3

EF

FIC

EN

CY

(%

)

Iout, OUTPUT CURRENT (A)

Figure 3. Efficiency vs Output Current andOutput Voltage

Vout = 5.0 V

3.3 V

1.5 V

1.2 V

NCP3155A, Vin = 12 VTypical Application CircuitFigure 45

Figure 4. Efficiency vs Output Current andOutput Voltage

0

10

20

30

40

50

60

70

80

90

100

0 0.5 1 1.5 2 2.5 3Iout, OUTPUT CURRENT (A)

EF

FIC

EN

CY

(%

)

NCP3155B, Vin = 12 VTypical Application CircuitFigure 45

Vout = 5.0 V

3.3 V

1.5 V

1.2 V

Figure 5. Efficiency vs Output Current and InputVoltage

EF

FIC

EN

CY

(%

)

Iout, OUTPUT CURRENT (A)

0

10

20

30

40

50

60

70

80

90

100

0 0.5 1 1.5 2 2.5 3

NCP3155A, Vout = 5 VTypical Application CircuitFigure 45

Vin = 12 V

Vin = 24 V

Vin = 18 V

4.96

4.98

5

5.02

5.04

5.06

5.08

5.1

4.9

4.92

4.94

4.96

4.98

5

5.02

5.04

5.06

5.08

5.1V

OU

T (

V)

Figure 6. Load Regulation vs Input VoltageIout, OUTPUT CURRENT (A)

NCP3155A, Vout = 5 VTypical Application CircuitFigure 45

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

Vin = 24 VVin = 12 V

Vin = 18 V

Input = 12 V, Output = 5.0 V, Load = 2 A,CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSWCH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/divTime Scale: 2.0 �s/div; Figure 45

Figure 7. Switching Waveforms (NCP3155A)


Figure 8. Switching Waveforms (NCP3155A)

NCP3155A, NCP3155B

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Figure 9. Switching Waveforms (NCP3155B)

792

794

796

798

800

802

804

806

808

−40 −25 −10 5 20 35 50 65 80 95 110 125

VF

B (

mV

)

TEMPERATURE (°C)

Figure 10. Feedback Reference Voltage vsTemperature

430440450460470480490500510520530540550560570

−40 −25 −10 5 20 35 50 65 80 95 110 125

f SW

(kH

z)

TEMPERATURE (°C)

Figure 11. Switching Frequency vs InputVoltage and Temperature

Vin = 12 V − 24 V

Vin = 4.7 V

860880900920940960980

1000102010401060108011001120

−40 −25 −10 5 20 35 50 65 80 95 110 125

f SW

(kH

z)

TEMPERATURE (°C)

Figure 12. Switching Frequency vs InputVoltage and Temperature

NCP3155A NCP3155B

Vin = 12 V − 24 V

Vin = 4.7 V

1.3

1.32

1.34

1.36

1.38

1.4

1.42

1.44

1.46

1.48

1.5

−40 −25 −10 5 20 35 50 65 80 95 110 125

g m (

mS

)

TEMPERATURE (°C)Figure 13. Transconductance vs Temperature

3.5

3.6

3.7

3.8

3.9

4

4.1

4.2

4.3

4.4

4.5

40 25 10 5 20 35 50 65 80 95 110 125TEMPERATURE (°C)

Figure 14. Input Undervoltage vs Temperature

UV

LO (

V)

UVLO Rising

UVLO Falling

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400

500

600

700

800

900

1000

1100

1200

−40 −25 −10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 15. Output Protection vs Temperature

TH

RE

SH

OLD

VO

LTA

GE

(m

V)

Output Overvoltage Threshold

Output Undervoltage Threshold

400

450

500

550

600

650

700

750

800

850

900

950

1000

−40 −25 −10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 16. Ramp Valley Voltage vs Temperature

VA

LLE

Y V

OLT

AG

E (

mV

)

10

11

12

13

14

15

16

17

−40 −25 −10 5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 17. ISET Current vs Temperature

ISE

T (�A

)

Input = 12 V, Output = 1.8 V, Load = 2 A,CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSWCH3: 10 V/div; CH2: 2.0 V/div; CH1: 5.0 V/divTime Scale: 1.0 ms/div; Figure 45

Figure 18. Startup Waveforms (NCP3155A)

Input = 12 V, Output = 1.8 V, Load = 2 A,CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSWCH3: 10 V/div; CH2: 1.0 V/div; CH1: 5.0 V/divTime Scale: 0.5 ms/div; Figure 46

Figure 19. Startup Waveforms (NCP3155B)

Input = 12 V(CH2) Green = VOUT, CH1 (Yellow) = VSWCH2: 0.5 V/div; CH1: 5.0 V/divTime Scale: 2.0 ms/div; Figure 45

Figure 20. Current Limit Waveforms (NCP3155A)

NCP3155A, NCP3155B

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Input = 12 V(CH2) Green = VOUT, CH1 (Yellow) = VSWCH2: 0.5 V/div; CH1: 5.0 V/divTime Scale: 2.0 ms/div; Figure 46

Figure 21. Current Limit Waveforms (NCP3155B)

0

10

20

30

40

50

60

70

80

90

100

110

40 25 10 5 20 35 50 65 80 95 110 125

RD

S(o

n) (

m�

)

TEMPERATURE (°C)

Figure 22. High−Side MOSFET RDS(on) vsTemperature

Vin = 10 V − 24 V

Vin = 5.0 V

0

5

10

15

20

25

30

−40 −25 −10 5 20 35 50 65 80 95 110 125

RD

S(o

n) (

m�

)

TEMPERATURE (°C)

Figure 23. Low−Side MOSFET RDS(on) vsTemperature

Vin = 10 V − 24 V

Vin = 5.0 V

0

0.5

1

1.5

2

2.5

3

3.5

25 30 35 40 45 50 55 60 65 70 75 80 85

1.0 V < Vout < 1.8 V

3.3 V

2.5 V

OU

TP

UT

CU

RR

EN

T (

A)

TA, AMBIENT TEMPERATURE (°C)

Figure 24. Derating Curve, 12 V Input

0

0.5

1

1.5

2

2.5

3

3.5

25 30 35 40 45 50 55 60 65 70 75 80 85

OU

TP

UT

CU

RR

EE

NT

(A

)



Vout = 5.0 V

1.8 V

3.3 V2.5 V

0

0.5

1

1.5

2

2.5

3

3.5

25 30 35 40 45 50 55 60 65 70 75 80 85

OU

TP

UT

CU

RR

EN

T (

A)



3.3 V

Vout = 5.0 V

12 V 2.5 V

Vout = 5.0 V

NCP3155A

NCP3155A NCP3155A

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0

0.5

1

1.5

2

2.5

3

3.5

25 30 35 40 45 50 55 60 65 70 75 80 85

OU

TP

UT

CU

RR

EN

T (

A)



3.3 V

Vout = 5.0 V

1.0 to1.2 V

2.5 V1.8 V

0

0.5

1

1.5

2

2.5

3

3.5

25 30 35 40 45 50 55 60 65 70 75 80 85

Vout = 5.0 V

3.3 V2.5 V

1.8 V



OU

TP

UT

CU

RR

EN

T (

A)


0

0.5

1

1.5

2

2.5

3

3.5

25 30 35 40 45 50 55 60 65 70 75 80 85


OU

TP

UT

CU

RR

EN

T (

A)

Vout = 5.0 V

2.5 V

3.3 V

12 V

NCP3155B NCP3155B

NCP3155B

NCP3155A, NCP3155B

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DETAILED DESCRIPTION

OVERVIEWThe NCP3155A/B operates as a 500 kHz/1.0 MHz, voltage

mode, pulse width modulated, (PWM) synchronous buckconverter. It drives high−side and low−side N−channel powerMOSFETs. The NCP3155 incorporates an internal boostcircuit consisting of a boost clamp and boost diode to providesupply voltage for the high side MOSFET gate driver. TheNCP3155 also integrates several protection features includinginput undervoltage lockout (UVLO), output undervoltage(OUV), output overvoltage (OOV), adjustable high−sidecurrent limit (ISET and ILIM), and thermal shutdown (TSD).

The operational transconductance amplifier (OTA)provides a high gain error signal from Vout which iscompared to the internal 1.5 V pk-pk ramp signal to set theduty cycle converter using the PWM comparator. The highside switch is turned on by the positive edge of the clockcycle going into the PWM comparator and flip flopfollowing a non-overlap time. The high side switch is turnedoff when the PWM comparator output is tripped by themodulator ramp signal reaching a threshold levelestablished by the error amplifier. The gate driver stageincorporates fixed non− overlap time between the high−side

and low−side MOSFET gate drives to prevent crossconduction of the power MOSFET’s.

POR and UVLOThe device contains an internal Power On Reset (POR) and

input Undervoltage Lockout (UVLO) that inhibits the internallogic and the output stage from operating until VCC reaches itsrespective predefined voltage levels (4.3 V typical).

Startup and ShutdownOnce VCC crosses the UVLO rising threshold the device

begins its startup process. Closed−loop soft−start beginsafter a 400 �s delay wherein the boost capacitor is charged,and the current limit threshold is set. During the 400 �s delaythe OTA output is set to just below the valley voltage of theinternal ramp. This is done to reduce delays and to ensure aconsistent pre−soft−start condition. The device increases theinternal reference from 0 V to 0.8 V in 32 discrete stepswhile maintaining closed loop regulation at each step. Eachstep contains 32 switching cycles. Some overshoot may beevident at the start of each step depending on the voltageloop phase margin and bandwidth. The total soft−start timeis 2.4 ms for the NCP3155A and 1.2 ms for the NCP3155B.

Figure 30. Soft−Start Details

Internal Reference Voltage

25 mV Steps

0.8 V

0V

0 .7V

OTA Output

Internal Ramp

Output Voltage

32 Voltage Steps

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OOV and OUVThe output voltage of the buck converter is monitored at

the feedback pin of the output power stage. Twocomparators are placed on the feedback node of the OTA tomonitor the operating window of the feedback voltage asshown in Figures 31 and 32. All comparator outputs areignored during the soft−start sequence as soft−start isregulated by the OTA and false trips would be generated.After the soft−start period has ended, if the feedback isbelow the reference voltage of comparator 2 (VFB < 0.6 V),

the output is considered “undervoltage” and the device willinitiate a restart. When the feedback pin voltage risesbetween the reference voltages of comparator 1 andcomparator 2 (0.6 < VFB < 1.0), then the output voltage isconsidered “Power Good.” Finally, if the feedback voltageis greater than comparator 1 (VFB > 1.0 V), the outputvoltage is considered “overvoltage,” and the device willlatch off. To clear a latch fault, input voltage must berecycled. Graphical representation of the OOV and OUV isshown in Figures 33 and 34.

Vref = 0.8 V

Vref*75%

Vref*125%

Comparator 1

Comparator 2

LOGIC

Soft Start Complete

Restart

Latch off

FB

Figure 31. OOV and OUV Circuit Diagram

Power Good = 1

Power Good = 1

Vref = 0.8 V

Voov = Vref * 125%

OUVP & Power Good = 0

OOVP & Power Good = 0

Hysteresis = 5 mV

Hysteresis = 5 mV

Power Not good High

Power Not Good Low

Figure 32. OOV and OUV Window Diagram

Vouv = Vref * 75%

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0.8 V (vref *100%)

0.6 V (vref *75%)

1.0 V (vref *125%)

FB Voltage

Latch off

Reinitiate Softstart

Softstart Complete

Figure 33. Powerup Sequence and Overvoltage Latch

0.8 V (vref *100%)

0.6 V (vref *75%)

1.0 V (vref *125%)

FB Voltage

Latch off

Reinitiate Softstart

Softstart Complete

Figure 34. Powerup Sequence and Undervoltage Soft−Start

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CURRENT LIMIT AND CURRENT LIMIT SET

OverviewThe NCP3155 uses the voltage drop across the High Side

MOSFET during the on time to sense inductor current. The

ILimit block consists of a voltage comparator circuit whichcompares the differential voltage across the VCC Pin and theVSW Pin with a resistor settable voltage reference. The senseportion of the circuit is only active while the HS MOSFETis turned ON.

CONTROL

Vset6

RSet

Iset13 uA

DAC /COUNTER

Ilim Out

PGND

ISET

VSW

VIN

VCC

Itrip Ref

VSense

SwitchCap

Figure 35. Iset / ILimit Block Diagram

Itrip Ref−63 Steps, 6.51 mV/step

Current Limit SetThe ILimit comparator reference is set during the startup

sequence by forcing a typically 13 �A current through thelow side gate drive resistor. The gate drive output will riseto a voltage level shown in the equation below:

Vset � Iset * Rset (eq. 1)

Where ISET is 13 �A and RSET is the gate to source resistoron the low side MOSFET.

This resistor is normally installed to prevent MOSFETleakage from causing unwanted turn on of the low sideMOSFET. In this case, the resistor is also used to set theILimit trip level reference through the ILimit DAC. The Isetprocess takes approximately 350 �s to complete prior toSoft−Start stepping. The scaled voltage level across the ISETresistor is converted to a 6 bit digital value and stored as thetrip value. The binary ILimit value is scaled and converted tothe analog ILimit reference voltage through a DAC counter.The DAC has 63 steps in 6.51 mV increments equating to amaximum sense voltage of 403 mV. During the Iset period

prior to Soft−Start, the DAC counter increments thereference on the ISET comparator until it crosses the VSETvoltage and holds the DAC reference output to that countvalue. This voltage is translated to the ILimit comparatorduring the ISense portion of the switching cycle through theswitch cap circuit. See Figure 35. Exceeding the maximumsense voltage results in no current limit. Steps 0 to 10 resultin an effective current limit of 0 mV.

Current Sense CycleFigure 36 shows how the current is sampled as it relates

to the switching cycle. Current level 1 in Figure 36represents a condition that will not cause a fault. Currentlevel 2 represents a condition that will cause a fault. Thesense circuit is allowed to operate below the 3/4 point of agiven switching cycle. A given switching cycle’s 3/4 Tontime is defined by the prior cycle’s Ton and is quantized in10 ns steps. A fault occurs if the sensed MOSFET voltageexceeds the DAC reference within the 3/4 time window ofthe switching cycle.

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1/4 1/2

Ton−1

1/4

3/4

Ton

¾Ton−2

¾Ton−1

No Trip:Vsense < Itrip Ref at 3/4 Point

Trip:Vsense > Itrip Ref at 3/4 Point

3/4

3/4 Point Determined byPrior Cycle

Vsense

1/2

Current Level 2

Current Level 1

Itrip Ref

Figure 36. ILimit Trip Point Description

Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample timevalue is held and used for the following cycle’s limit sample time

Soft−Start Current limitDuring soft−start the ISET value is doubled to allow for

inrush current to charge the output capacitance. The DACreference is set back to its normal value after soft−start hascompleted.

VSW RingingThe ILimit block can lose accuracy if there is excessive

VSW voltage ringing that extends beyond the 1/2 point of thehigh−side transistor on−time. Proper snubber design andkeeping the ratio of ripple current and load current in the10−30% range can help alleviate this as well.

Current LimitA current limit trip results in completion of one switching

cycle and subsequently half of another cycle Ton to accountfor negative inductor current that might have causednegative potentials on the output. Subsequently the powerMOSFETs are both turned off and a 4 soft−start time periodwait passes before another soft−start cycle is attempted.

Iave vs Trip PointThe average load trip current versus RSET value is shown

the equation below:

IAveTRIP �Iset � Rset

RDS(on)

�1

4�VIN � VOUT

L�

VOUT

VIN

�1

FSW

�(eq. 2)

Where:L = Inductance (H)ISET = 13 �ARSET = Gate to Source Resistance (�)RDS(on) = On Resistance of the HS MOSFET (48 m�)VIN = Input Voltage (V)

VOUT = Output Voltage (V)FSW = Switching Frequency (Hz)

Boost Clamp FunctionalityThe boost circuit requires an external capacitor connected

between the BST and VSW pins to store charge for supplyingthe high and low−side gate driver voltage. This clamp circuitlimits the driver voltage to typically 7.5 V when VIN > 9 V,otherwise this internal regulator is in dropout and typicallyVIN − 1.25 V.

The boost circuit regulates the gate driver output voltageand acts as a switching diode. A simplified diagram of theboost circuit is shown in Figure 37. While the switch nodeis grounded, the sampling circuit samples the voltage at theboost pin, and regulates the boost capacitor voltage. Thesampling circuit stores the boost voltage while the VSW ishigh and the linear regulator output transistor is reversedbiased.

VIN

8.9V

BST

VSW

LSDR

Figure 37. Boost Circuit

SwitchSampling

Circuit

NCP3155A, NCP3155B

http://onsemi.com15

Reduced sampling time occurs at high duty cycles wherethe low side MOSFET is off for the majority of the switchingperiod. Reduced sampling time causes errors in theregulated voltage on the boost pin. High duty cycle / inputvoltage induced sampling errors can result in increasedboost ripple voltage or higher than desired DC boost voltage.Figure 38 outlines all operating regions.

The recommended operating conditions are shown inRegion 1 (Green) where a 0.1 �F, 25 V ceramic capacitorcan be placed on the boost pin without causing damage to thedevice or MOSFETS. Larger boost ripple voltage occurring

over several switching cycles is shown in Region 2 (Yellow).The boost ripple frequency is dependent on the outputcapacitance selected. The ripple voltage will not damage thedevice or �12 V gate rated MOSFETs.

Conditions where maximum boost ripple voltage coulddamage the device or �12 V gate rated MOSFETs can beseen in Region 3 (Orange). Placing a boost capacitor that isno greater than 3.3 nF on the boost pin limits the maximumboost voltage < 12 V. The typical drive waveforms forRegions 1, 2 and 3 (green, yellow, and orange) regions ofFigure 38 are shown in Figure 39.

Figure 38. Safe Operating Area for Boost Voltage with a 0.1 �F Capacitor

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 902

11.5V

22V

4

6

8

10

12

14

16

18

20

22

24

Normal Operation

(Region 1)

Increased Boost Ripple

(Still in Specification)

(Region 2)

Increased Boost Ripple

Capacitor Optimization

Required (Region 3)

71%

MaxDutyCycle

Region 1 Region 2

Region 3

INP

UT

VO

LTA

GE

DUTY CYCLE

BOOST VOLTAGE LEVELS

NCP3155A, NCP3155B

http://onsemi.com16

VBOOST

VIN7.5V

Normal

Maximum

VBOOST

VIN

Normal

Maximum

0V

VBOOST

VIN

7.5V

Figure 39. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom)

7.5V

7.5V

7.5V

0V

7.5V

0V

To illustrate, a 0.1 �F boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specificationsfor the driver supply voltage. See Figure 40.

NCP3155A, NCP3155B

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Boost Voltage

0

2

4

6

8

10

12

14

16

18

4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5Input Voltage (V)

Boo

st V

olta

ge (

V)

Figure 40. Boost Voltage at 80% Duty Cycle

Voltage Ripple

Maximum Allowable Voltage

Maximum Boost Voltage

Inductor SelectionWhen selecting the inductor, it is important to know the

input and output requirements. Some example conditionsare listed below to assist in the process.

Table 1. DESIGN PARAMETERS

Design Parameter Example Value

Input Voltage (VIN) 9 V to 16 V

Nominal Input Voltage (VIN) 12 V

Output Voltage (VOUT) 3.3 V

Input ripple voltage (VINRIPPLE) 300 mV

Output ripple voltage (VOUTRIPPLE) 50 mV

Output current rating (IOUT) 3 A

Operating frequency (Fsw) 500 kHz

A buck converter produces input voltage (VIN) pulses thatare LC filtered to produce a lower dc output voltage (VOUT).The output voltage can be changed by modifying the on timerelative to the switching period (T) or switching frequency.The ratio of high side switch on time to the switching periodis called duty cycle (D). Duty cycle can also be calculatedusing VOUT, VIN, the low side switch voltage drop VLSD,and the High side switch voltage drop VHSD.

F �1

T(eq. 3)

D �TON

T(� D �

TOFF

T(eq. 4)

D �VOUT VLSD

VIN � VHSD VLSD

� D �VOUT

VIN(eq. 5)

� 27.5% �3.3 V

12 V

The ratio of ripple current to maximum output currentsimplifies the equations used for inductor selection. Theformula for this is given in Equation 6.

ra ��I

IOUT

(eq. 6)

The designer should employ a rule of thumb where thepercentage of ripple current in the inductor lies between10% and 40%. When using ceramic output capacitors theripple current can be greater thus a user might select a higherripple current, but when using electrolytic capacitors a lowerripple current will result in lower output ripple. Now,acceptable values of inductance for a design can becalculated using Equation 7.

L �VOUT

IOUT ra FSW

(1 � D) � 8.2 �H

(eq. 7)

�3.3 V

3 A 20% 500 kHz (1 � 27.5%)

The relationship between ra and L for this design exampleis shown in Figure 41.

NCP3155A, NCP3155B

http://onsemi.com18

0

2

4

6

8

10

12

14

16

18

20

10% 15% 20% 25% 30% 35% 40%VIN, (V)

L, IN

DU

CTA

NC

E (�H

)

18 V−InVout = 3.3 V

Figure 41. Ripple Current Ratio vs. Inductance

12 V−In

9 V−In

To keep within the bounds of the parts maximum rating,calculate the RMS current and peak current.

IRMS � IOUT 1 ra2

12� � 3.01 A

(eq. 8)

� 3 A 1 (0.2)2

12�

IPK � IOUT �1 ra

2 � 3.3 A � 3 A �1

(0.2)

2(eq. 9)

An inductor for this example would be around 8.2 �H andshould support an rms current of 3.01 A and a peak currentof 3.3 A.

The final selection of an output inductor has bothmechanical and electrical considerations. From amechanical perspective, smaller inductor values generallycorrespond to smaller physical size. Since the inductor isoften one of the largest components in the regulation system,a minimum inductor value is particularly important inspace−constrained applications. From an electricalperspective, the maximum current slew rate through theoutput inductor for a buck regulator is given by Equation 10.

SlewRateLOUT �VIN � VOUT

LOUT

� 1.1A�s

(eq. 10)

�12 V � 3.3 V

8.2 �H

This equation implies that larger inductor values limit theregulator’s ability to slew current through the outputinductor in response to output load transients. Consequently,output capacitors must supply the load current until theinductor current reaches the output load current level. Thisresults in larger values of output capacitance to maintaintight output voltage regulation. In contrast, smaller values ofinductance increase the regulator’s maximum achievableslew rate and decrease the necessary capacitance, at theexpense of higher ripple current. The peak−to−peak ripplecurrent for the NCP3155A is given by the followingequation:

IPP �VOUT(1 � D)

LOUT FSW

(eq. 11)

Ipp is the peak to peak current of the inductor. From thisequation it is clear that the ripple current increases as LOUTdecreases, emphasizing the trade−off between dynamicresponse and ripple current.

The power dissipation of an inductor consists of bothcopper and core losses. The copper losses can be furthercategorized into dc losses and ac losses. A good first orderapproximation of the inductor losses can be made using theDC resistance as they usually contribute to 90% of the lossesof the inductor shown below:

LPCU � IRMS2 DCR (eq. 12)

The core losses and ac copper losses will depend on thegeometry of the selected core, core material, and wire used.Most vendors will provide the appropriate information tomake accurate calculations of the power dissipation then thetotal inductor losses can be capture buy the equation below:

LPtot � LPCU_DC LPCU_AC LPCore (eq. 13)

Input Capacitor SelectionThe input capacitor has to sustain the ripple current

produced during the on time of the upper MOSFET, so itmust have a low ESR to minimize the losses. The RMS valueof this ripple is:

IinRMS � IOUT D (1 � D)� (eq. 14)

D is the duty cycle, IinRMS is the input RMS current, andIOUT is the load current.

The equation reaches its maximum value with D = 0.5.Loss in the input capacitors can be calculated with thefollowing equation:

PCIN � ESRCIN �IIN�RMS2 (eq. 15)

PCIN is the power loss in the input capacitors and ESRCINis the effective series resistance of the input capacitance.Due to large dI/dt through the input capacitors, electrolyticor ceramics should be used. If a tantalum must be used, itmust by surge protected. Otherwise, capacitor failure couldoccur.

Input Start−up CurrentTo calculate the input startup current, the following

equation can be used.

IINRUSH �COUT VOUT

tSS

(eq. 16)

Iinrush is the input current during startup, COUT is the totaloutput capacitance, VOUT is the desired output voltage, andtSS is the soft start interval. If the inrush current is higher thanthe steady state input current during max load, then the inputfuse should be rated accordingly, if one is used.

NCP3155A, NCP3155B

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Output Capacitor SelectionThe important factors to consider when selecting an

output capacitor is dc voltage rating, ripple current rating,output ripple voltage requirements, and transient responserequirements.

The output capacitor must be rated to handle the ripplecurrent at full load with proper derating. The RMS ratingsgiven in datasheets are generally for lower switchingfrequency than used in switch mode power supplies but amultiplier is usually given for higher frequency operation.The RMS current for the output capacitor can be calculatedbelow:

CoRMS � IO ra

12�(eq. 17)

The maximum allowable output voltage ripple is acombination of the ripple current selected, the outputcapacitance selected, the equivalent series inductance (ESL)and ESR.

The main component of the ripple voltage is usually due tothe ESR of the output capacitor and the capacitance selected.

VESR_C � IO ra �ESRCo 1

8 FSW Co (eq. 18)

The ESL of capacitors depends on the technology chosenbut tends to range from 1 nH to 20 nH where ceramiccapacitors have the lowest inductance and electrolyticcapacitors then to have the highest. The calculatedcontributing voltage ripple from ESL is shown for the switchon and switch off below:

VESLON �ESL IPP FSW

D(eq. 19)

VESLOFF �ESL IPP FSW

(1 � D)(eq. 20)

The output capacitor is a basic component for the fastresponse of the power supply. In fact, during load transient,for the first few microseconds it supplies the current to theload. The controller immediately recognizes the loadtransient and sets the duty cycle to maximum, but the currentslope is limited by the inductor value.

During a load step transient the output voltage initially dropsdue to the current variation inside the capacitor and the ESR(neglecting the effect of the effective series inductance (ESL)).

�VOUT−ESR � �ITRAN ESRCo (eq. 21)

A minimum capacitor value is required to sustain thecurrent during the load transient without discharging it. Thevoltage drop due to output capacitor discharge isapproximated by the following equation:

�VOUT−DISCHG ��ITRAN

2 LOUT

COUT �VIN � VOUT

(eq. 22)

In a typical converter design, the ESR of the output capacitorbank dominates the transient response. It should be notedthat �VOUT−DISCHARGE and �VOUT−ESR are out ofphase with each other, and the larger of these two voltageswill determine the maximum deviation of the output voltage(neglecting the effect of the ESL).

Conversely during a load release, the output voltage canincrease as the energy stored in the inductor dumps into theoutput capacitor. The ESR contribution from Equation 18still applies in addition to the output capacitor charge whichis approximated by the following equation:

�VOUT−CHG ��ITRAN

2 LOUT

COUT VOUT

(eq. 23)

As with any power design, proper laboratory testing shouldbe performed to insure the design will dissipate the requiredpower under worst case operating conditions. Variablesconsidered during testing should include maximum ambienttemperature, minimum airflow, maximum input voltage,maximum loading, and component variations.

Feedback and CompensationThe NCP3155 is a voltage mode buck convertor with a

transconductance error amplifier compensated by anexternal compensation network. Compensation is needed toachieve accurate output voltage regulation and fast transientresponse. The goal of the compensation circuit is to providea loop gain function with the highest crossing frequency andadequate phase margin (minimally 45°). The transferfunction of the power stage (the output LC filter) is a doublepole system. The resonance frequency of this filter isexpressed as follows:

fP0 �1

2 � L COUT� (eq. 24)

Parasitic Equivalent Series Resistance (ESR) of theoutput filter capacitor introduces a high frequency zero tothe filter network. Its value can be calculated by using thefollowing equation:

fZ0 �1

2 � COUT ESR(eq. 25)

The main loop zero crossover frequency f0 can be chosento be 1/10 − 1/5 of the switching frequency. Table 2 showsthe three methods of compensation.

Table 2. COMPENSATION TYPES

Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type

fP0 < fZ0 < f0 < fS/2 Type II Electrolytic, Tantalum

fP0 < f0 < fZ0 < fS/2 Type III Method I Tantalum, Ceramic

fP0 < f0 < fS/2 < fZ0 Type III Method II Ceramic

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Compensation Type IIThis compensation is suitable for electrolytic capacitors.

Components of the Type II (Figure 42) network can bespecified by the following equations:

Figure 42. Type II Compensation

RC1 �2 � f0 L VRAMP VOUT

ESR VIN Vref gm(eq. 26)

CC1 �1

0.75 2 � fP0 RC1

(eq. 27)

CC2 �1

� RC1 fS

(eq. 28)

R1 �VOUT � Vref

Vref

R2 (eq. 29)

VRAMP is the peak−to−peak voltage of the oscillator rampand gm is the transconductance error amplifier gain.Capacitor CC2 is optional.

Compensation Type IIITantalum and ceramics capacitors have lower ESR than

electrolytic, so the zero of the output LC filter goes to ahigher frequency above the zero crossover frequency. Thisrequires a Type III compensation network as shown inFigure 43.

There are two methods to select the zeros and poles of thiscompensation network. Method I is ideal for tantalumoutput capacitors, which have a higher ESR than ceramic:

Figure 43. Type III Compensation

fZ1 � 0.75 fP0 (eq. 30)

fZ2 � fP0 (eq. 31)

fP2 � fZ0 (eq. 32)

fP3 �fS

2(eq. 33)

Method II is better suited for ceramic capacitors thattypically have the lowest ESR available:

fZ2 � f0 1 � sin�max

1 sin �max� (eq. 34)

fP2 � f0 1 sin �max

1 � sin �max� (eq. 35)

fZ1 � 0.5 fZ2 (eq. 36)

fP3 � 0.5 fS (eq. 37)

�max is the desired maximum phase margin at the zerocrossover frequency, ƒ0. It should be 45° − 75°. Convertdegrees to radians by the formula:

�max � �maxdegress �2 �360

: Units � radians (eq. 38)

The remaining calculations are the same for both methods.

RC1 ��2

gm(eq. 39)

CC1 �1

2 � fZ1 RC1

(eq. 40)

CC2 �1

2 � fP3 RC1

(eq. 41)

CFB1 �2 � f0 L VRAMP COUT

VIN RC1

(eq. 42)

RFB1 �1

2� CFB1 fP2

(eq. 43)

R1 �1

2 � CFB1 fZ2

� RFB1 (eq. 44)

R2 �V

ref

VOUT � Vref

R1 (eq. 45)

If the equation in Equation 46 is not true, then a higher valueof RC1 must be selected.

R1 R2 RFB1

R1 RFB1 R2 RFB1 R1 R2�

1gm

(eq. 46)

NCP3155A, NCP3155B

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Output Current DeratingThe NCP3155 has a wide input voltage and output voltage

capability. It also operates in a variety of thermalenvironments. These thermal conditions limit the maximumoutput current for a given input and output voltage.Therefore, proper output current derating must beconsidered, taking into account ambient temperature,airflow, the input and output conditions, and the need forincreased reliability. Figures 24 − 29 show safe operatingconditions vs. output current for input voltages of 12 V,18 V, and 24 V. These curves assumed 300 mm2 of 2 ozcopper. Sufficient cooling could also be provided to ensurereliable operation. Finally, to maintain operation in the safeoperating areas shown in the curves, it is recommended touse the NCP3155 with input to output conditions as shownin Figure 44. Figure 44. Recommended Maximum Output

Voltage vs Input Voltage

0

2

4

6

8

10

12

14

4 6 8 10 12 14 16 18 20 22 24

VIN, INPUT VOLTAGE (V)

VO

UT,

OU

TP

UT

VO

LTA

GE

(V

)

NCP3155A, NCP3155B

http://onsemi.com22

NCP3155A

FB1

VOUTBST

VSW

PGND

AGND

ISET

COMP

VINVIN5 V

10.8 – 24 V

0.1�

8.2�

150� 22�

47�47�

24k 33p

1.8n

18.2kR1

19.62k

649

820p



680p

1.5

VOUT (V) R1 (k�)

1.2 39.2k

1.5 22.1k

3.3 6.19k

5.0 3.74k

NCP3155B

FB1

VOUTBST

VSW

PGND

AGND

ISET

COMP

VINVIN1.8 V

9 − 16 V

0.1�

4.7�

150� 22�

220�220�

22.1k 220p

12n

4.7k4.99k

6.21k

649

2.2n680p

1.5

NCP3155A, NCP3155B

http://onsemi.com23



NCP3155B

FB1

VOUTBST

VSW

PGND

AGND

ISET

COMP

VINVIN3.3 V

10.8 − 14 V

0.1�

4.7�

150� 22�

22�22�

24k 10p

1.2n

27k6.19k

19.62k

270

560p680p

1.5

NCP3155B

FB1

VOUTBST

VSW

PGND

AGND

ISET

COMP

VINVIN3.3 V

10 − 14 V

0.1�

4.7�

150� 22�

10�220�

22.1k 150p

8.2n

6.8k4.99k

15.8k

580

680p680p

1.5

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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DESCRIPTION:

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PAGE 1 OF 2SOIC−8 NB

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1

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NCP3155 - Synchronous Buck Regulator · CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div Time...

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