© Semiconductor Components Industries, LLC, 2012

May, 2012 − Rev. 21 Publication Order Number:

NCL30105/D

NCL30105

Constant Off Time PWMCurrent-Mode Controller forLED Applications

The NCL30105 is a peak current controlled fixed off time controllerdesigned for LED driver applications in which the LEDs are operatedin deep Continuous Conduction Mode (CCM) without requiring slopecompensation. Featuring an adjustable off time generator, thecontroller can drive a MOSFET up to a 500 kHz switching frequency.

A dedicated dimming pin enables the use of a pulse−widthmodulated logic signal to dim the LEDs directly. The soft−start pincreates a startup sequence that slowly ramps up the peak current andenables the adjustment of the peak current setpoint for analogdimming control. The device features robust protection features todetect switch overcurrent faults and to detect maximum on timeevents.

Features• Constant Off Time Current−Mode Control Operation

• Adjustable Off Time (0.5 �s to 10 �s)

• Internal Leading Edge Blanking

• Source 250 mA / Sink 500 mA Peak Drive Capability

• ±3.2% Current Sense Accuracy at 25°C

• Internal Startup Delay

• 3.3 V Logic Level Dimming Input

• This is a Pb−Free Device

Safety Features• Thermal Shutdown

• Maximum On Time Protection

• Overcurrent Protection

Typical Application• LED Backlight Drivers for LCD Panels

• LED Light Bars

• LED Street Lighting

• LED Bulbs

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Device Package Shipping†

ORDERING INFORMATION

NCL30105DR2G SOIC−8(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.

SOIC−8D SUFFIXCASE 751

MARKING DIAGRAM

L0105ALYW

�

1

8

L0105 = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

1

8

PIN CONNECTIONS

toff

VCC

NC

SSTARTDIM

CS DRV

GND

1

(Top View)

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Figure 1. Typical Application Diagram

Vin

NCL30105

DIMSoft−Start /Ipeak Adjustment

toff

DIM

VCC

CS

GND

DRV

SSTART

NC

M

L

D

VCC

CVCCRtoff Rsense

CSSTART

LED1

LEDN

CLED

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Figure 2. Internal Circuit Architecture

SRQ

DIM

CS DRV

SSTART

+ −

toffgenerator

Q

Q

toff

VCC UVLO ok = 1, else 0

GND

NC

set current

high= rst

updown

S

R

Q

ref

+−

1 = reset1 = reset

SET

SETstartpulse

Vcc

Vcc

OVRI

OVRI

tLEBtLEB(fault)

VILIMVILIM(fault)

Vtoff(open)

VDIM(open)

RDIM

Q

Q

tstart(delay)

ISSTART

VSSTART(open)

Nfault

count to Nfault

/ Iratio

ton > ton(MAX)

+

Von = VCC(on)Voff = VCC(off)

Table 1. PIN FUNCTION DESCRIPTION

PinNumber Pin Name Function Pin Description

1 toff Adjusts the Off TimeDuration

A resistor to ground sets the off time duration.

2 DIM Dimming Input This pin is used for PWM dimming or to enable/disable the controller.

3 VCC Supplies the Controller An external auxiliary voltage connected to this pin supplies the controller.

4 CS Current Sense Input This pin monitors the peak current. When the peak current reaches theinternal threshold, the DRV is turned off.

5 DRV Driver Output The output of the driver is connected to an external MOSFET gate.

6 GND − The controller ground.

7 SSTART Soft−start / Peak CurrentAdjustment

A capacitor connected to this pin sets the soft−start duration. The voltageof this pin adjusts the peak current set point for analog dimming.

8 NC Non−connected Pin Non−connected pin

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Table 2. MAXIMUM RATINGS TABLE (Notes 1 – 4)

Rating Symbol Value Unit

toff Voltage Vtoff −0.3 to 5.5 V

toff Current Itoff ±10 mA

DIM Voltage VDIM −0.3 to 7 V

DIM Current IDIM ±10 mA

SSTART Voltage VSSTART −0.3 to 5.5 V

SSTART Current ISSTART ±10 mA

CS Voltage VCS −0.3 to 7 V

CS Current ICS ±10 mA

DRV Voltage VDRV −0.3 to VCC V

DRV Sink Current IDRV(sink) 500 mA

DRV Source Current IDRV(source) 250 mA

Supply Voltage VCC −0.3 to 22 V

Supply Current ICC ±20 mA

Power Dissipation (SO−8)(TA = 70°C, 2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)

PD 450 mW

Thermal Resistance Junction−to−Ambient (SO−8)(2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)Junction−to−Air, Low conductivity PCB (Note 3)Junction−to−Air, High conductivity PCB (Note 4)

R�JA178168127

°C/W

Operating Junction Temperature Range TJ −40 to 150 °C

Storage Temperature Range TSTG −60 to 150 °C

Lead Temperature (Soldering, 10 s) TL 300 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. This device series contains ESD protection and exceeds the following tests:

Pins 1 − 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.Pins 1 − 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.Pins 1 − 8: Charged Device Model 2000 V per JEDEC Standard JESD22−C101C.

2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified

for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.

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Table 3. ELECTRICAL CHARACTERISTICS (Rtoff = 40.2 k�, VDIM = 3 V, CSSTART = 100 nF, VCS = 0 V, CDRV = 1 nF, VCC = 12 V,unless otherwise specified (For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified))

Characteristic Test Conditions Symbol Min Typ Max Unit

STARTUP AND SUPPLY CIRCUITS

Startup Voltage Threshold VCC Increasing VCC(on) 9 10 11 V

Minimum Operating Voltage VCC Decreasing VCC(off) 8 8.8 10 V

Supply Voltage Hysteresis VCC(on) − VCC(off) VCC(HYS) 1 1.2 1.5 V

Current Consumption in Latch Mode ICC(latch) − 510 900 �A

Startup Current Consumption VCC < VCC(on) − 500 mV ICC1 − 250 390 �A

Device Disabled Current Consumption VDIM = 0 V ICC2 − 0.71 1.7 mA

Device Switching Current Consumption fSW = 60 kHz ICC3 − 1.84 2.49 mA

GATE DRIVE

Drive Sink Resistance ISNK = 25 mA RSNK − 6.0 13.2 �

Drive Source Resistance ISRC = 25 mA RSRC − 24 44 �

Rise Time VDRV = 10% to 90% tr − 80 140 ns

Fall Time VDRV = 90% to 10% tf − 25 60 ns

CURRENT SENSE

Current Sense Voltage Threshold TJ =−40°C to 125°CTJ =25°C

VILIM 0.950.977

1.011.01

1.051.042

V

Current Sense Propagation Delay VCS = 0 V to 1.2 V Step, dV/dt = 10 V/�s

VCS = VILIM to VDRV = 10%

tILIM − 60 150 ns

Leading Edge Blanking Duration tLEB 470 545 670 ns

CONSTANT OFF TIME GENERATOR (Note 5)

Off Time (Note 6) Rtoff = 5 k� toff1 0.87 1.02 1.13 �s

Recommended Off Time Resistor Range Rtoff(range) 2.5 − 60 k�

Minimum Off Time Rtoff = 0 � toff(MIN) 0.3 0.37 0.5 �s

Maximum Off Time Rtoff = open toff(MAX) 10 11.77 14.5 �s

toff Pin Regulated Voltage Vtoff(REG) 0.95 1 1.05 V

Maximum Switching Frequency (Note 7) Rtoff = 0 � f(MAX) 500 − − kHz

SOFT−START

Soft−Start Charge Current VSSTART = 3 V ISSTART 17 20 23 �A

Soft−Start Voltage to Peak Current SetPoint Ratio

VSSTART = VILIM * Iratio Iratio 2.85 3 3.15 −

Soft−Start Pin Open Voltage VSSTART(open) 4.5 5 5.5 V

Soft−Start Internal Discharge SwitchResistance

ISSTART = 5 mA RDS(on)SSTART 200 350 500 �

DIMMING INPUT

Dimming Enable Voltage Threshold VDIM Increasing VDIM(H) 1.8 2 2.2 V

Dimming Disable Voltage Threshold VDIM Decreasing VDIM(L) 0.8 1 1.2 V

DIM Pin Open Voltage VDIM(open) 4 4.5 5.5 V

DIM Pin Internal Pull−Up Resistor VDIM = 0 V RDIM 50 90 150 k�

Dimming Wake−Up Time VDIM = 0 V to 3 V Step,dV/dt = 10 V/�s

VDIM = VDIM(H) to VDRV = 90%

twake − 0.28 1 �s

5. See Figure 17.6. The tolerance of toff is guaranteed by design.7. The thermal limitation of the device specified by the Maximum Ratings Table must not be exceeded.

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Table 3. ELECTRICAL CHARACTERISTICS (Rtoff = 40.2 k�, VDIM = 3 V, CSSTART = 100 nF, VCS = 0 V, CDRV = 1 nF, VCC = 12 V,unless otherwise specified (For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified))

Characteristic UnitMaxTypMinSymbolTest Conditions

PROTECTION

Maximum On Time ton(MAX) 29.8 34 42.1 �s

Number of Consecutive Maximum OnTime Events or Overcurrent Events

Nfault − 8 − −

Overcurrent Current Sense VoltageThreshold

VILIM(fault) 1.5 1.6 1.7 V

Overcurrent Propagation Delay VCS = 0 V to 2 V Step,dV/dt = 10 V/�s

VCS = VILIM(fault) to VDRV = 10%

tILIM(fault) 10 70 150 ns

Overcurrent Leading Edge Blanking Dur-ation

tLEB(fault) 170 220 280 ns

Leading Edge Blanking Duration Ratio tLEB(fault)/tLEB tLEB(ratio) 0.3 0.4 0.8 −

Startup Delay VCC = VCC(on) to VDRV = 90% tstart(delay) 100 130 172 ms

Thermal Shutdown TJ = Increasing TSHDN 155 °C

Thermal Shutdown Hysteresis TJ = Decreasing TSHDN(HYS) 40 °C

Thermal Shutdown Delay TSHDN(delay) 75 �s

5. See Figure 17.6. The tolerance of toff is guaranteed by design.7. The thermal limitation of the device specified by the Maximum Ratings Table must not be exceeded.

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TYPICAL CHARACTERISTICS

Figure 3. Startup Voltage Threshold vs.Junction Temperature

Figure 4. Minimum Operating Voltage vs.Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−509.0

9.2

9.6

9.8

10.0

10.4

10.8

11.0

1251007550250−25−508.0

8.2

8.4

8.8

9.0

9.4

9.8

10.0

Figure 5. Supply Voltage Hysteresis vs.Junction Temperature

Figure 6. Startup Current Consumption vs.Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−500.5

0.6

0.7

0.9

1.1

1.2

1.3

1.5

1251007550250−25−50150

170

190

210

230

250

290

330

Figure 7. Device Disabled CurrentConsumption vs. Junction Temperature

Figure 8. Device Switching CurrentConsumption vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−500.0

0.1

0.3

0.4

0.6

0.7

0.9

1.0

1501007550250−25−501.0

1.2

1.4

1.6

1.8

2.0

2.2

VC

C(o

n), S

TAR

TU

P V

OLT

AG

ET

HR

ES

HO

LD (

V)

VC

C(o

ff), M

INIM

UM

OP

ER

AT

ING

VO

LTA

GE

(V

)

VC

C(H

YS

), S

UP

PLY

VO

LTA

GE

HY

ST

ER

ES

IS (

V)

I CC

1, S

TAR

TU

P C

UR

RE

NT

CO

NS

UM

PT

ION

(�A

)

I CC

2, D

EV

ICE

DIS

AB

LED

CU

RR

EN

TC

ON

SU

MP

TIO

N (

mA

)

I CC

3, D

EV

ICE

SW

ITC

HIN

GC

UR

RE

NT

CO

NS

UM

PT

ION

(m

A)

150

9.4

10.2

10.6

8.6

9.2

9.6

150

150

0.8

1.0

1.4

150

270

0.2

0.5

0.8

150 125

310

2.4

2.6

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TYPICAL CHARACTERISTICS

Figure 9. Current Sense Voltage Threshold vs.Junction Temperature

Figure 10. Leading Edge Blanking Duration vs.Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−500.90

0.92

0.96

0.98

1.00

1.04

1.08

1.10

1251007550250−25−50500

510

520

540

550

570

Figure 11. Current Sense Propagation Delayvs. Junction Temperature

Figure 12. Soft−Start Charge Current vs.Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−5020

30

50

60

70

100

1251007550250−25−5016

17

18

19

20

21

23

24

Figure 13. Soft−Start Voltage to Peak CurrentSet Point Ratio vs. Junction Temperature

Figure 14. Off Time vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−502.85

2.95

3.05

3.15

1501007550250−25−500.85

0.90

0.95

1.00

1.05

1.10

1.15

VIL

IM, C

UR

RE

NT

SE

NS

E V

OLT

AG

ET

HR

ES

HO

LD (

V)

t LE

B, L

EA

DIN

G E

DG

E B

LAN

KIN

GD

UR

AT

ION

(ns

)

t ILIM

, CU

RR

EN

T S

EN

SE

PR

OP

AG

AT

ION

DE

LAY

(ns

)

I SS

TAR

T, S

OF

T−

STA

RT

CH

AR

GE

CU

RR

EN

T (�A

)

I ratio

, SO

FT−

STA

RT

VO

LTA

GE

TO

PE

AK

CU

RR

EN

T S

ET

PO

INT

RA

TIO

t off,

OF

F T

IME

(�s)

150

0.94

1.02

1.06

530

560

150

150

40

80

150

22

2.90

3.00

3.10

150 125

Rtoff = 5 k�

580

600

590

90

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TYPICAL CHARACTERISTICS

Figure 15. Minimum Off Time vs. JunctionTemperature

Figure 16. Maximum Off Time vs. JunctionTemperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−500.1

0.2

0.3

0.6

0.7

1251007550250−25−509.0

9.5

10.0

12.0

12.5

14.0

Figure 17. Off Time vs. toff Pin Resistor Figure 18. Maximum On Time vs. JunctionTemperature

Rtoff, toff PIN RESISTOR (k�) TJ, JUNCTION TEMPERATURE (°C)

62.542.532.522.512.52.501

3

7

9

13

1251007550250−25−5020

25

30

35

40

50

Figure 19. Overcurrent Current Sense VoltageThreshold vs. Junction Temperature

Figure 20. Dimming Thresholds vs. JunctionTemperature

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−501.40

1.50

1.65

1.80

1501007550250−25−500.0

0.5

1.0

1.5

2.0

2.5

t off(

MIN

), M

INIM

UM

OF

F T

IME

(�s)

t off(

MA

X),

MA

XIM

UM

OF

F T

IME

(�s)

t off,

OF

F T

IME

(�s)

t on(

MA

X),

MA

XIM

UM

ON

TIM

E (�s)

VIL

IM(f

ault)

, OV

ER

CU

RR

EN

T C

UR

RE

NT

SE

NS

E V

OLT

AG

E T

HR

ES

HO

LD (

V)

VD

IM, D

IMM

ING

VO

LTA

GE

TH

RE

SH

OLD

S (

V)

150

0.4

0.5

11.0

13.5

150

2

11

150

45

1.45

1.60

1.75

150 125

10.5

11.5

13.0

52.5

456

8

10

12

1.55

1.70

VDIM(H)

VDIM(L)

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TYPICAL CHARACTERISTICS

Figure 21. Zoomed In Off Time vs. toff PinResistor

9.58.57.56.55.54.53.52.50.0

0.5

1.0

2.5

3.0

Rtoff, toff PIN RESISTOR (k�)

t off,

OF

F T

IME

(�s)

10.5

1.5

2.0

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Application InformationIntroduction

NCL30105 implements a current−mode architectureoperated with a constant off time. The internal current setpoint and the external sense resistor determine the on timeduration. The off time duration is adjusted with a resistorconnected from the toff pin to ground. The constant off timeoperation enables deep continuous conduction modeoperation without requiring slope compensation. The DIMpin enables the use of a PWM signal to modulate theswitching pattern and adjust the average luminosity. TheSSTART pin creates a soft−start that reduces the stress on thepower components during startup and enables the use of ananalog dimming signal to set the peak current by adjustingthe SSTART pin voltage.• Constant Off Time Peak Current−Mode Operation:

The constant off time technique enables the controllerto operate a converter in deep continuous conductionmode without requiring slope compensation. Theconstant off time technique is inherently immune tosub−harmonic oscillations.

• Off Time Adjustment: A pull−down resistorconnected to the toff pin sets the off time duration.

• Maximum On Time Protection: an internal circuitmonitors the drive signal on time duration. If the driveon time duration reaches ton(MAX), the fault up/downcounter is incremented by 1. If the drive on timeduration reaches ton(MAX) during the next clock cycle,the counter is incremented again. If the drive on timeduration does not reach ton(MAX) due to the currentcomparator being triggered during the next drive ontime, the counter is decremented by 1. This sequencecontinues until the counter reaches 8. If the counterreaches 8, the NCL30105 is immediately latched off.When VCC is forced below VCC(off) and then aboveVCC(on), the latch is reset.

• LED Short−Circuit Protection: If the CS pin voltageincreases above VILIM(fault), the overcurrent comparatoris triggered, which turns off the drive and incrementsthe fault up/down counter by 1. If the overcurrentcomparator is triggered again during the next drive ontime, the counter is incremented again. If theovercurrent comparator is not triggered due to thecurrent comparator being triggered during the nextdrive on time, the counter is decremented by 1. Thissequence continues until the counter reaches 8. If thecounter reaches 8, the part is immediately latched off.When VCC is forced below VCC(off) and then aboveVCC(on), the latch is reset.

• Power On Delay: When VCC reaches VCC(on), thetstart(delay) timer begins counting, during which thedrive is disabled. When tstart(delay) elapses, the SSTART

pin current source is enabled and the soft−startsequence begins.

• Soft−Start Operation: A capacitor connected to theSSTART pin is charged by an internal current sourceafter the tstart(delay) timer period has elapsed. Thesoft−start period is completed when the SSTART pinvoltage reaches VILIM*Iratio. The soft−start capacitor isdischarged during the tstart(delay) to ensure the SSTARTpin voltage begins charging from zero.

• Peak Adjustment: Analog dimming is achieved byforcing the SSTART pin below VILIM*Iratio, whichlowers the peak current set point. Note: even if theSSTART pin is forced to 0 V, there is still a minimumon time every switching cycle. Under this condition, theminimum on time is the current sense leading edgeblanking time plus the propagation delay to turn off theMOSFET and the off time is determined by the toffresistor value.

• Leading Edge Blanking: an internal circuit blinds thecurrent sense comparator for a few hundrednanoseconds when the output drive goes high. The LEBensures that controller remains insensitive to theturn−on voltage spikes observed on the CS pin due tothe free−wheel diode recovery time.

• Dimming Input: a dedicated pin is provided to PWMmodulate the LED current to reduce the LEDluminosity. The circuit is driven on and off via a 3.3−Vlogic level signal. The DIM pin can also be used as anenable/disable pin, since the switching is disabled whenthere is a logic low signal applied to this pin.

• Thermal Shutdown: if the junction temperature of thecontroller exceeds an internal threshold, the drive isdisabled. The drive remains disabled until the junctiontemperature decreases below the internal hysteresisthreshold. The disabling of the drive protects thecontroller from destruction due to overheating.

Startup SequenceWhen VCC reaches VCC(on), the NCL30105 maintains the

drive low and the soft−start capacitor (CSSTART, connectedto the SSTART pin) remains pulled to ground by the internalpull−down switch until the startup delay (tstart(delay))elapses. Once the tstart(delay) period has elapsed, the drive isenabled and a soft−start sequence begins. The internalcurrent source begins charging CSSTART and the voltage onthe SSTART pin (VSSTART) begins increasing. The peakcurrent set point is equal to VSSTART divided by Iratio. WhenVSSTART reaches the voltage that sets the maximum peakcurrent (VSSTART = VILIM*Iratio), the soft−start sequence iscomplete and the peak current set point is equal to VSSTARTdivided by Iratio. Figure 22 describes a typical start−upsequence.

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Figure 22. A Typical Startup Sequence

User changesthe setpoint

reset

Soft−StartSequence

Constant Peak Variable Peak

Internaltimer reset

Soft−StartSequence

tstart(delay)

VDRV

VCC

VCC(off)

VCC(on)

VCS

VSSTART VSSTART(open)

VSSTART = VILIM * Iratio

VILIM

Soft−Start PinThe soft−start internal section is shown in Figure 23. The

soft−start sequence is implemented using a current sourcethat charges an external capacitor. The relationship betweenthe capacitor voltage and the peak current voltage set pointis Iratio. The maximum peak current set point isVSSTART/Iratio. For luminosity balancing purposes, it ispossible to force the voltage on the SSTART pin from anexternal source. When forcing VSSTART with an external

source, the current into the SSTART pin must be limited toensure that the maximum current rating is not exceeded. Itis recommended to set VSSTART by connecting a diode asshown in Figure 23. Using this configuration, the SSTARTcapacitor value to set a 15 ms soft−start duration (tSSTART)is calculated using Equation 1:

CSSTART �ISSTART � tSSTART

Iratio�

20 � � 15 m3

� 0.1 �F

(eq. 1)

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/Iratio

+ −

latch reset

sensedcurrent

SSTART

UVLO reset

Currentcomparator

peak currentsetpoint control

D21N4148

Figure 23. The Soft−start Block Configuration to Set the Peak Current Setpoint

CSSTART

ISSTART

VSSTART(open)

VILIM

tstart(delay)Timer reset

Constant Off time GeneratorThe controller operates with a constant off time technique.

The off time technique is implemented by forcing a constantoff time with the on time being set by the combination of the

peak current threshold, the inductor value, and the inputvoltage. Unlike traditional peak current mode control, thefixed off time technique is not susceptible to sub−harmonicinstability as shown in Figure 24:

constant

constant

on off

Figure 24. The Constant Off Time Technique is Immune toSub−Harmonic Instabilities without Ramp Compensation

�IL

IL(t)

In Figure 24, the perturbation is corrected in one switchingcycle, despite a duty ratio greater than 50%. This benefitenables the designer to exclude slope compensation whenoperating the inductor in a deep continuous conductionmode.

The constant off time generator follows the principlesketched in Figure 25 where an internal timer is started at theend of each on time. Once the off time generator has elapsed,it begins the next DRV pulse. The off time is programmedby connecting a resistor from the toff pin to ground. The offtime range is from 0.5 �s to 10 �s.

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adjustable

constant

off

onDrive

Internaltimer

Figure 25. A Timer is Started at the End of the On Time Duration

ProtectionThe NCL30105 includes several methods of protection.

One of the protection features is the maximum on timelimitation, which protects the system if the CS pin does notreceive a signal. The on time is internally limited to

ton(MAX). The maximum on time limitation may occur if theinput voltage is too low or if the CS pin is shorted to ground.After 8 consecutive maximum on times events, thecontroller is latched as shown in Figure 26.

Faultoccurs

1 2 1 2 3 4 5 6 7 8Count

Figure 26. The Protection Feature Limits the Maximum On Timeand Disables the Controller During a Fault

hereton(MAX)

Smaller pulse:countdown

Controller islatched afterthe 8th event

In latched mode, the controller consumes a low currentand waits for a complete VCC cycle (VCC decreases to lessthan VCC(off) and then increased to greater than VCC(on)) toresume operation. The tracking of the fault events isimplemented with an up/down counter. The counter isincremented by 1 when the ton(MAX) duration ends thedriving pulse. The counter is decremented by 1 when anormal reset occurs via the current comparator. When thecounter reaches 0, it stores this value and waits for an uppulse to change state.

The NCL30105 includes Leading Edge Blanking (LEB)circuits to prevent inadvertent triggering of the current andovercurrent comparators. When the DRV pin goes high,noise is generated on the CS pin due to the parasitic elements

in the circuit. The LEB circuit “blanks” the noise to ensurethat the current and overcurrent comparators are notinadvertently triggered. If the LEB circuit is omitted, thenoise causes the DRV to turn off before the required peakcurrent is reached as shown in Figure 28. This causes thesystem to operate erratically. When the LEB circuit isincluded, the noise is “blanked” by blinding the currentcomparator for the LEB duration (tLEB) and the requiredpeak current is reached as shown in Figure 29. The inclusionof the LEB circuits prevents the erratic operation of thesystem.

Another protection feature is the overcurrent detection.The overcurrent detection activates when a short−circuitoccurs in the inductor and LED string. To prevent false

NCL30105

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detection during surge tests, the controller uses the samecounter as the maximum on time limitation. Due to the twodifferent LEB circuits (tLEB and tLEB(fault)) configuration, ifthere is a severe overload, the overcurrent comparator istriggered first and the counter is incremented. If theovercurrent comparator is not triggered during the nextclock cycle, the counter is decremented by the currentcomparator. Figure 27 depicts the logical arrangementinside the controller. In the presence of a fast rising signal,the overcurrent comparator is triggered first since tLEB(fault)

< tLEB. When the overcurrent comparator output goes high,it resets the PWM latch and increments the counter. Thecounter can no longer increment or decrement until the nextswitching cycle. If during the time the overcurrentcomparator output is high, tLEB elapses and causes thecurrent comparator output to go high, the output of thecurrent comparator is ignored due to the AND gateconnection. Figure 30 illustrates the operation of the CSlogic during an overcurrent fault. Only one up count or onedown count is made per switching cycle.

CS

+

−up

down

+

−

PWM reset

Q

latchoff

OvercurrentComparator

CurrentComparator

Figure 27. CS Internal Logic

tLEB

tLEB(fault)

VILIM(fault)

VILIM

ton >ton(MAX)

Nfault

Count to Nfault

DRV

down

t

t

t

Inadvertant trigger

DRV turned off

peak current is

Required peak current

Figure 28. Circuit without Leading Edge Blanking

down

t

t

t

Noise “blanked”

Figure 29. Circuit with Leading Edge Blanking

VCS(t)

VILIMComparator

Output

tILIM

VILIM

tLEB

before required

reached

DRV

VCS(t)

VILIMComparator

OutputtLEB

tILIM

VILIM

NCL30105

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up

down

DRV

down

t

t

t

t

off

Ignored

Figure 30. The Overcurrent Comparator Increments the Counter during a Fault

VILIMComparator

VILIM(fault)Comparator

VCS(t)

tLEB(fault)

tLEB tLEB

tILIM

VILIM

VILIM(fault)tILIM(fault)

Minimum Dimming Duty CycleDuring each DIM cycle if the max on time limit is reached

a certain number of times, the current comparator must betriggered the same number of times to reset the fault counter.For each DIM cycle, if the maximum on time limit is reacheda greater number of times than the number of times thecurrent comparator is triggered, the fault counter is not resetand is incremented each DIM cycle until the fault count isreached (Nfault = 8). This results in a minimum dimmingduty cycle for a particular LED string voltage and inductor

combination. The minimum dimming duty cycle isdescribed in Figure 31 shown below. The first DRV pulseduring the dimming duty cycle reaches the maximum ontime, but the second DRV pulse does not and is turned off bythe current comparator. If the dimming on time (duty cycle)is reduced, the second DRV pulse is turned off by the DIMpin voltage, the current comparator is not triggered, and theNCL30105 latches after 8 dimming cycles.

Figure 31. Minimum Dimming Duty Cycle

NCL30105

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Example CalculationThe design begins with the system requirements. The

following are the system requirements of an examplesystem:

Input Voltage (Vin) = 80 V

Number of LEDs = 18

LED forward Voltage = 3.33 V

LED string Voltage (VLED) = 60 V

LED average current (ILED) = 350 mA

LED ripple current (�ILED) = 150 mA (±75 mA)

Operating frequency = 100 kHzThe switching period is calculated using the target

operating frequency:

TSW � 1fSW

(eq. 1)

TSW � 1100k

� 10 �s

The off time (toff) is calculated using the LED stringvoltage, input voltage, and switching period:

toff � �1 �VLEDVin� � TSW (eq. 2)

toff � �1 � 6080� � 10 �s � 2.5 �s

To set toff, the following calculation is used based on theon the approximation of the linear region of the toff vs. Rtofftransfer function as shown in Figure 17:

Rtoff [k�] �toff [�s] � 0.1214

0.1864

Where toff is entered in �s and Rtoff is calculated in k�.

Rtoff �2.5 � 0.1214

0.1864� 12.76 k�

Rtoff is selected as 12.7 k�.The inductor value is calculated using the off time:

L �VLED � toff

dILED(eq. 3)

L �60 � 2.5 �

150m� 1 mH

The LED peak current (ILED(peak)) is also the inductorpeak current and is calculated using the average LED currentand the LED ripple current:

ILED(peak) � ILED � dILED2

(eq. 4)

ILED(peak) � 350m � 150m2

� 425 mA

It is critical that the inductor saturation current is greaterthan the peak current. Sufficient margin is generally set to20%. For 20% margin, the inductor should be selected tohave a saturation current greater than 510 mA. The senseresistor (Rsense) value is calculated using the peak current:

Rsense �VILIM

ILED(peak)(eq. 5)

Rsense � 10.425

� 2.35 �

NCL30105

http://onsemi.com18

Typical Application Schematic:

Figure 32. Typical Application Schematic

NCL30105

http://onsemi.com19

Thermal Considerations:The designer must ensure that the junction temperature of

the NCL30105 remains less than the value of the maximumoperating junction temperature in the Maximum RatingsTable for the worst−case operating conditions. Themaximum junction temperature is calculated using theestimated current consumption. The estimated currentconsumption is calculated using the following assumptions:

1. The switching frequency is at the maximum of500 kHz (fSW(MAX)).

2. The Vcc is at the maximum of 22 V (VCC(MAX))3. The gate of the MOSFET is modeled using a 1 nF

capacitor (Cg)4. The non−switching bias current is at the maximum

of 1.56 mA (ICC2)

Using these assumptions, the current consumption iscalculated:

ICC(TJMAX) � �Cg � VCC � fSW(MAX)� � ICC2

ICC(TJMAX) � (1 n � 22 � 500 k) � 1.56 m � 12.56 mA

The power dissipation of the NCL30105 is calculated:

P(TJMAX) � ICC(TJMAX) � VCC(MAX)

P(TJMAX) � 12.56 m � 22 � 276 mW

The junction temperature is calculated using themaximum thermal resistance (R�JA(MAX)) with theminimum PCB copper area from the maximum ratings table:

TJ(rise) � P(TJMAX) � R�JA(MAX)

TJ(rise) � 0.276 � 178 � 40oC

Assuming a maximum ambient temperature of 70°C(Tambient), the maximum junction temperature is calculated:

TJ(MAX) � TJ(rise) � Tambient

TJ(MAX) � 49 � 70 � 119oC

Since this is less than the TSHDN parameter with sufficientmargin, the design is acceptable.

Layout Tips:Careful layout is critical for all switch−mode power

supply design. Successful layout includes specialconsideration for noise sensitive pins of the controller IC.For the NCL30105 the following pins should be carefullyrouted:

1. Vcc: This pin requires a ceramic decouplingcapacitor (typically 100 nF) and a electrolyticcapacitor (typically 10 �F) to ensure that IC supplyis constant and decoupled from high frequencynoise generated by switching currents.

2. toff: This pin requires a resistor connected toground to set the off time. It is not recommendedto leave this pin open or shorted to ground to setthe off time. The connection from the toff pin tothe resistor and from the resistor to ground must bemade as short as possible and connected directly tothe NCL30105 GND pin. High noise nodes andtraces must be routed as far away from this pin aspossible.

3. SSTART: A capacitor is connected to this pin toset the Soft−Start time. The connection from theSSTART pin to the capacitor and from thecapacitor to ground must be made as short aspossible.

4. DIM: A decoupling capacitor may need to beconnected to this pin if it coupled to high noisetraces. The connection from the DIM pin to thecapacitor and from the capacitor to ground must bemade as short as possible. The addition of thecapacitor may affect the response of time of theDIM signal to the DRV output.

5. CS: If LEB period is not long enough to ensurepredictable operation, a small RC filter may needto be connected to this pin. The addition of the RCfilter affects the current set point accuracy.

6. DRV: The trace that connects the DRV pin to theMOSFET must be made as short as possible toreduce the parasitic inductance of the trace. TheDRV pin switches high currents and the parasiticinductance can cause higher than expectedvoltages to be applied to the gate of the MOSFET.A small resistor is recommended to be connectedin series with the DRV pin to the gate. The resistorreduces the effect of the parasitic inductance. Theaddition of the resistor may affect the switchinglosses of the MOSFET.

NCL30105

http://onsemi.com20

Recommended Layout:

Figure 33. Top Layout

Figure 34. Bottom Layout

NCL30105

http://onsemi.com21

The critical components for layout are the following:

1. R2 (Rtoff): This resistor sets the off time. Theplacement of this resistor is such that the distanceto the pin and IC ground is minimized. Thefootprints R1 and R3 are optional to increase theprecision of the resistance value.

2. C5 (CVCC): This is the Vcc supply decouplingcapacitor. The placement of this capacitor is suchthat the distance to the pin and IC ground is

minimized. The recommended minimum value forthis capacitor is 100 nF.

3. C8 (CSSTART): This capacitor sets the soft−starttime. The placement of this capacitor is such thatthe distance to the pin and IC ground isminimized.

The layout includes options to use a surface mountinductor (footprint L2) and MOSFET (footprint M2).

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

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