Naohiko Shimizu Department of Communications …labo.nshimizu.com/AUN.pdfNaohiko Shimizu, Tokai...

Digital Applications and Education with SFL and FPGA

Naohiko ShimizuDepartment of Communications Engineering,Tokai University, Japan

http://shimizu-lab.dt.u-tokai.ac.jp/

1

Naohiko Shimizu, Tokai Univ., ASEAN Microelectronics 2003, Aug. 28-29 2003, Manila, Philippines


Agenda

Education/Research Projects with SFL at Shimizu Laboratory in Last Ye

Undergraduate Project Example -- Video GameUndergraduate Project Example -- PDP11 Compatible CPUUndergraduate/Master Project Example -- USB Device ContolerResearch Project Example -- MP3 Hardware EncoderResearch Project Example -- USB 2.0 High Speed ControlerResearch Project Example -- Java ProcessorResearch Project Example -- Latency Tolerant Processor

Undergraduate Curriculum for Microelectronics in our department

Demonstration of SFL development environment

Conclusion

Last year, I have no doctorial students, no research assistant, 5 master students, 8 undergraduates.All of these projects are carried out with 3 master and 4 undergraduates.

Studnet A

Studnet B

Shimizu

CPU proto-type

Apr. May Jun. Jul. Aug. Sep. Oct. Nov. Dec. Jan. Feb.

CPU Simulation/Debug

Software LicensingNegosiation

Composit Sync. Cirucuit

NTSC Color Modulation

CRT Controler

Demonstrationat EmbeddedTechnology 2002

Project Thesis Paper

Multiple Audio Signal Modulation

Parthenon Society,ASIC Design Contest

They had many lectures, and not fully contributed

Undergraduate Project Example -- Video Game

Contracted

Debug on FPGAJoint Simulation

Video D/A Conversion

F

ALU

AB CD E

H L

SP

PC

MUX, DMUX

INC,DEC

OP0 OP1 OP2

CONTROL UNIT

INTERNAL BUS

SYSTEM BUS

RAM ROM

DMUX

JOYPAD

RAM ROM

CPU

Write_enable

Read_enable

Clock_1.7MHz

Read_Data

Address-decoder

CSYNC

Master_Clock14.318MHz

Reset

Controller

AnalogCircuit

Memory

Master_Clock

My80_Clock

Video Controler

CSYNC

C_BURST

CHROM_2

CHROM_1

Data

Address

Write_enable

ROM_access

ROM_access

JOYPAD

NT

SC

to TVJOYPAD DATA

SOUND

Write_Data

Address

SOUND 1bit SO

UN

D

WhiteNoise

7th semester 8th semester

start to learn SFL

Device name logic elementsMax Freq. 20MHz

EPF10K30E-3

1503


Studnet C

Apr. May Jun. Jul. Aug. Sep. Oct. Nov. Dec. Jan. Feb.

CPU Specification/Logic/Simulation GCC/RTOS poring


Undergraduate Project Example -- PDP11 Compatible CPU

Debug on FPGA

7th semester 8th semester

MMU/UNIX

ALU

InstructionUnit

RegisterFile

(memory mapped)

AddressingModeUnit

InstructionDecode

Unit

Memory controlUnit DATA

ADDRESS

DATA

On-chipMemory

On-chipMemory

ALU BUS

SOURCE BUS

DESTINATION BUS

ADDRESS BUS

OP-CODE BUS

ADDRESS

POP11 CPU core

InterruptControler

Priority

Interrupt/Acknowledge

Timerinterrupts

Cas

cade

d C

onne

ct

Vector

On-chipPeripheral

On-chipPeripheral

HIG

H P

RIO

RIT

Y

RS-232Ccontroler

UNIX V6 boot and working

POP-11/10 1678 LCs 9 MHz EPF10K30EQC208-3

POP-11/40* 2687 LCs 20 MHz EP1K100QC208-1

CPU Logic Cells Max Freq. FPGA

POP-11/10for Embedded

POP-11/40*



Master A

Studnet D

Apr. May Jun. Jul. Aug. Sep. Oct. Nov.

USB specification/IF logic

USB spec./MPU Firmware



Undergraduate/Master Project Example -- USB Device Contoler

Debug on FPGA

dataMEM

USBIF

MIC2550

GamePadIF

GamePad

data-d

addr-d

data-i

addr-i

1616

16 16

Host or Hub

MPU

InstructionMEM

ALTERAAPEX

Modules

Transfer

Transaction

Packets

CRC

NRZI EncodeStuff bits

SYNC Pattern

MPUFirmware

USBLogic

USB Protocol Engine

Device name EP20K1000CF672C7total logic elements 1617

Max Freq. 52.52MHz

Dec. Jan. Feb. Mar.

USB specification/IF logic

USB 2.0 Project started

Original MPU SN/Xwith Original I/F Logics


Research Project Example -- MP3 Hardware Encoder

Input In Buffer Filter Bank MDCT

MPU

D-BUSI-BUS

InstructionMemory

OutBuffer RAM

HuffmanEncoder

QuantizeBuffer

QuantizerOutput Huffman

Table

inhouse PCII/F

PCI_BUS

PC

quantize

IN BufferMemory

OUT BufferMemory

FPGA

TableMemory

real

Software with quantize logic

user

sys

44m59s

43m22s

0m03s

9m59s

6m39s

2m59s

MP3 Encoder Performance Comparisonto encode a music song on a PC.

Target Configuration

We are implementing all of thefeatures within an FPGA.

4 times speedup achieved with hardware quantizer

Current Status: demonstrate quantizer implemented in an FPGA, on a PCI board.

807LogicElements Max frequency 108MHz Total MemoryBits 49152

With new hardware algorith,we will build a high speed,low power MP3 encoder LSI.


Research Project Example -- USB 2.0 High Speed Controler


DMAcontroller Data

MEMInst.MEM

MPUsnx2pu2

CRC5

CRC16

HASH

Tag00rom

DATA00rom

Tag01rom

DATA01rom

Device Controller

DataIn

RxValidIn

RxActiveIn

TxValidOut

TxReadyIn

DataOut

BITUNSTUFFER

NRZIDECODER

RCV State Machine

TX State Machine

BITSTUFFER

XCVR

LINESTATE

DP

DM

RXSHIFTREG

RXHOLDREG

TXSHIFTREG

TXHOLDREG

NRZIENCODER

UTMI

to H

OS

T

TAG SET BLOCK7bits 2bits 3bits

Tag_rom00

Tag_rom01 Data_rom01

Data_rom00

Compare

Compare

Hit?

Hit?Address Size

16bits

Key

Designing High Speed USB 2.0 Controlerwith Hash controler for packet descrimination. Hash Controler

System Block Diagram

UTMI controler for USB1.1 is inhouse.UTMI for USB 2.0 is in market.

Current Status: Begining to debug on an FPGA

Inst.MEM

DECODER

R0-0R1-0R2-0R3-0

R0-1R1-1R2-1R3-1

AL

U

Data MEM

PC

intadd

IncmINST

maluo

repc

IO Device

Original MPU

Research Project Example -- Java Processor


PCIF

MEMORY

+4

New Program Counter

branch

ADD

InstructionPrefetchBuffer

IDATA0

IDATA1

IDATA2

IDATA3

New Program Counter

EXDATA0

EXDATA1

EXDATA2

EXDATA3

Execution

Data

Buffer

Instruction

Data

IRSHIFT

OPOPERAND?

OPOPERANDV PC

OPL

Execution Data1

PC WCOUNTER

0

branch

ADD

Determine

entries to fetch

and release

ADD

1,2folding_oc

folding_oc

IRSHIFT

OPOPERAND?

OP OPERANDV PCNEXT

PCNEXT

OPL

ADD

PCNEXT2

folding_id

Execution Data2

folding_id

folding_id

OP OPERANDPC

ADD

0,4,8,12

VARS

EXCOUNTER

EXOP

EXOPERAND

EXOPERAND2exvexv2

nop

EXPC

branch

exv,exv2

exrls

0

ADD

1,2folding_oc

OP OPERAND PC

folding_oc

ocforwardfp

folding_oc

ocop

ocforward2

STACKCASHEUNIT

forward2cmp

ex3opdata

STACK CACHEUNIT

ALU

scinst

branch

...

scv

MEMORYscma

NewProgramCounter

exrls

CONTROL UNIT

IF ID OC EX

TRAJA Processor: Queued Pipilining Java Processor

JOLAB: Java Object Look Aside Buffer

TRAJA Block Diagram JOLAB Benchmark based on Kaffe

Designing state of art Java processor

Reduce Resolution Overhead for Embedded ApplicationsIt is also working for software JVM. v

comparecompare

comparecomparecompare

head constant pool index

tag

index

Hit

Data

hashing

JOLAB Block Diagram

Research Project Example -- Latency Tolerant Processor


BranchPrediction

PC

InstructionCache

InstructionTLB

Decoder 1

Decoder 2

GeneralPurposeRegisters

DataCache

DataTLB

SCALTBuffer

Load/StoreBufferRefill Unit

Branch Unit

ForwardingUnit

Memory busAccess Unit

CommandAddress

tagData

SDRAMAccess

tagData

Return Queue Access Queue

SDRAM Controller

+8

SCALT Processor

System Controler

Cache misses

tag

Data

BF or BS instructions Cache miss Load / Store

SCALT Block Diagram

Scalable Latency Tolerant Processor (SCALT) Project

Dual Issue Alpha Compatible Instruction set with SCALT extensions.

0

5e+06

1e+07

1.5e+07

2e+07

Clo

ck c

ycle

Memory access latency = 50 Cycle

Load/StoreBuffer Instruction

COPY SCALE SUM TRIAD

High performance processor with simple organization.

5000

10000

15000

20000

25000

30000

35000

40000

10 20 30 40 50 60

PE

RFO

RM

AN

CE

(256

BA

NK

S)

Num of BUFFER ENTRY

VC-SCALT(16CPU)VC-SCALT(8CPU)

SCALT(16CPU)SCALT(8CPU)


Undergraduate Microelectronics Education at Tokai University

Semester Lectures (credit)1-4 Pulse Circuit(4), Digital Circuit(4)

5 Computer Engineering(4), Integrated Circut Engineering(4)

6 Computer Systems(4), VLSI Design Seminar I(2)

7 VLSI Design Seminar II(2)

8 none

CMOS circuit, Schematic Diagrams

Spice Simulation and LSI Layout with Magic

CPU Design with SFL

Join to Lab.


Demonstration


ConclusionSFL benefit for research/education in ASEAN

Fast Startup of StudentsMost undergraduate students start to design original processor within 2 months.

Cost EffectivePARTHENON Society can provide access to CAD system.FPGA vendors provide web version of FPGA fitter/placer.

Competitive Design Language for VLSIWe can take different approach than US or EU.

With SFL, I had designed 6502 compatible MPU within 2 days.Four people at NTT designed DLX compatible MPU in 4 days.

SFL benefit for startup companies in ASEANAt this time, C based design is far from practical.

Same as above, and we sould not pay to much money on tools!

I believe that the microelectronics activity in ASEAN will lead 21st Century.

There is no silver bullet, but most US engineers only started with Mead and Conway(1980).It is only 20 years experience. We will be able to beat them with strategic alliance in ASEAN.

Naohiko Shimizu Department of Communications …labo.nshimizu.com/AUN.pdfNaohiko Shimizu, Tokai...

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