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Transcript of Nanotechnology for Future Generation Devices for Computation and Communication Computation (Magnetic...
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Nanotechnology for Future Generation Devices for
Computation and Communication
Computation (Magnetic Data Storage, CMOS Technology)
Communication (Interconnects)
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Nanotechnology: Magnetic Data Storage
History of the Hard Drive
Nanomagnetic Devices and Technologies
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01/18/08 3
Magnetic Storage technologies
Tape: serial storage, serial access Disk Drive: semi-serial storage, semi-random
access. RAM: “addressable” Random access memory
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01/18/08 4
Magnetic Tape based storage
From the Poulsen’s telegraphone: Magnetized piano wire on a
cylinder.
To the modern cassette tape.
Biggest drawback is it is serial storage, serial access.
(ca. 1898)
(ca. 2006)
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01/18/08 5
Magnetic Core Memory
Developed in early 1950’s at MIT
write: Ampere’s Law read: Faraday’s Law
Early example of magnetic cross-point memory
Core memory stack$10k/8kb
(52 Kb in 8x8x8 inch cube)
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01/18/08 6
The hard disk drive
Moving read-write head Magnetic media platter Nonvolatile, slow but for
large amounts of cheap storage
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01/18/08 7
The read-write head
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01/18/08 8
The present: hard drive media
Longitudinal recording media, deposited by PVD.
Areal density limited by bits placed end-to-end.
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01/18/08 9
Progress in HDD vs DRAM
(cf. Hitachi)
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01/18/08 10
The future: patterned media
50nm patterned CoCrPt nanopillars with perpendicular anisotropy for > 250Gbits/sqin.
(M. Sharma, IIT Delhi)
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01/18/08 11
The Future: Magnetic RAM
Nonvolatile No cycle limitation (not so in Flash) Low power (and low voltage) Fast (nsec speeds) Simple bit cell
thin film memory cell small area can use multiple memory layers
CMOS compatible low processing temperatures embedded applications
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01/18/08 12
Circuitry
Nonvolatile
No cycle limitation (not so in Flash)
Low power (and low voltage)
Fast (nsec speeds)Design at HPL, Fab external @0.35um1Mbit array in 1999, 18 column slices (16 data, 2 parity)
Process for 130nm MRAM bits most aggressive in industry. => 1Gb MRAM in 2003. includes Cu cladded conductors.
HP MRAM
3-conductor MRAMFinished CMOS die
Final CMOS wafer
(M. Sharma, work done at HP Labs)
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Nanotechnology: CMOS Technology
CMOS Scaling for transistors
Lithography for sub-100nm devices
Gate Oxide Issues
Capacitors for Memory
Interconnect Scaling
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Introduction
The ITRS Roadmap as a “how-to” guide for preserving Moore’s Law
These “how-to’s” have included improved photolithography and some device and process modifications; there are some new ones!
The first fundamental physical limitation encountered in device scaling has been hit; gate oxide thickness.
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Moore’s Law
The number of transistors per chip quadruples
every two years (1965)
every three years (1975)
every four years (1995)
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Why scaling ?
Pstatic = Ileakage · VDD
Pdynamic = CL ·VDD · f2
PDP = CL · VDD2
Power-delay product
Example: CMOS inverter
GND
VDD
GND
CL ~ Cox*W*L
VOUTVIN
CL VDDtox
Scaling improves density, speed and power consumption of digital circuits
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Minimum Feature Size Trend: Limited by Photolithography
LGATE
0.18um0.25um
0.35um0.5um
0.8um1.0um
1.5um2um
3um
0.01
0.1
1
10
1970 1980 1990 2000 2010 2020
Year
Micron
0.7x per generation
LGATE
Reproduced from "MOS Transistor Scaling Challenges, " M.Bohr, in ULSI Process Integration II, The Electrochemical Society Proceedings Series, PV 2001-2, p. 466 (C. Claeys, et al., Editors). Reproduced by permission of the Electrochemical Society, Inc.
DRAM half-pitch (dense)
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Roadmap-driven Process and Device Development Needs (IEDM 2001) High-k gate dielectrics
Performance-power consumption tradeoff
Lightly doped, depleted channels: SOI Reduced off-state power loss, higher mobility
Raised, low-resistance source-drains Lower parasitic on-state power loss
Tunable work function metal gate electrodes
Dual-gate MOSFET’s
Limiting power consumption is the watchword!
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Gate Oxide
Need to use High-k gate dielectricsNeeds to be very thinAnd extremely uniform
Poly/2.5 nm SiO2/Si Al/ 1nm HfO2/Si(M. Sharma, work in collab. with HP Labs)
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ITRS Roadmap EOT Projections*
1
10
Eq
uiv
ale
nt
Ox
ide
Th
ickn
es
s (n
m)
Technology Generation (nm)
350 250 180 130 90 65 45 32 22
Trend
1994-2001
1 molecular layer of SiO2
1994
1999
1997
2001
Trend 1994 – 2001
* 2001 EOT values developed jointly by Osburn with ITRS PIDS TWG
Targets become more aggressive with each new Roadmap. For 1997 and beyond, a physical limitation in the use of SiO2
appears.
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Multi-metal-layer capacitors
• Hirad Samavati et al., “Fractal Capacitors”, IEEE Journal of Solid-State Circuits, vol. 33, no. 12, December 1998, pp. 2035-2041.• R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors”, IEEE JSSC, vol. 37, no. 3, March 2002, pp. 384-393.
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Hierarchical Interconnect scaling
Delay is limited by wire size.Need different sized wires
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Optical Interconnects
Chip-Chip Comm. (cf. Intel)On-chip Optical Antennas (M. Sharma)
VCSEL's for on-chip comm.
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Adding it all up...
Metal Gate / High-k dielectric
Multilayered capacitors
SiGe/Si channel
Transistor of the future
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Thank You!