Nanostructures for Tera-bit Level Charge Trap Flash Memories · Nanostructures for Tera-bit Level...

NanoForum'09

Nanostructures for Nanostructures for TeraTera--bit Levelbit LevelCharge Trap Flash MemoriesCharge Trap Flash Memories

Byung-Gook Park, Il Han Park, Jung-Hoon Lee,Gil Sung Lee, Jang-Gn Yun

Inter-University Semiconductor Research CenterSchool of Electrical Eng. and Computer Sci.

Seoul National University

NanoForum'09 SNU SNU SoEECSSoEECS & ISRC& ISRC

Outline

I.I. IntroductionIntroduction

II. NAND Cell Structure

III. NOR Cell and Array Structure

IV. AND Cell and Array Structure

V. STAR NAND Flash Structure

VI. Conclusions


Flash Memory and Mobile Equipments

32


Expedited Growth Theory Expedited Growth Theory -- NAND FlashNAND Flash

q Expedited growth theory of NAND flash memoriesè Year 2011 1Tb capacity with 20nm feature size

2002 2004 2006 2008 2010 2012 2014 2016 2018

10

100 ITRS (2008)Hwang’s law

Year of Development

Tec

hn

olo

gy

No

de

(nm

)

10

100

1000

Cap

acity (Gig

a Bit)


Hard Disk Drive and Flash MemoryHard Disk Drive and Flash Memory


Growth of Storage CapacityGrowth of Storage Capacity

1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 20101k

10k

100k

1M

10M

100M

1G

10G

100G

1T

10T

Capa

city

(bi

t)

Year

HDDODDFGFCTFFeRAMMRAMPRAM


Floating Gate vs. Charge TrapsFloating Gate vs. Charge Traps

Ø No floating gate- FG-FG space- FG-active space- Single gate structure

Gate

Floating Gatestructure

SONOSstructure

Gate

P-Si P-Si

ONOCompositeDielectrics

n+ n+ n+ n+

Gate

Floating Gatestructure

SONOSstructure

Gate

P-Si P-Si

ONOCompositeDielectrics

n+ n+ n+ n+

Tunnel Blocking

Si SiO2 Si3N4 SiO2Poly Si

3.1

3.8

8.0

1.05

1.85

3.1

3.8

e eeh hh

Tunnel Blocking

Si SiO2 Si3N4 SiO2Poly Si

3.1

3.8

8.0

1.05

1.85

3.1

3.8

e eeh hh

Ø Defect immunity - Non-conductive trap layer- Discrete trap storage

Ø 3D structure compatibility - Insulating storage node- Simple fabrication


Outline

I. Introduction

II.II. NAND Cell StructureNAND Cell Structure




VI. Conclusions


Arch Structure (1)Arch Structure (1)

q Utilization of curved surfaces for field enhancement- fast “program”and “erase”- increased effective area

SiO2

Si

Poly

ONO

r2

r1

r2

r1

0 2 4 6 8 10 12 140.0

2.0M

4.0M

6.0M

8.0M

10.0M

12.0M

Bottom OxideSilicon Nitride

Ele

ctric

Fie

ld (V

/cm

)

Position (nm)

Arch type Planar type

Top Oxide


Arch Structure (2) Arch Structure (2)

Hard mask

Si Si SiO2

Si

q Fabrication procedure



q Utilization of HSQ mask characteristicq Planarization by TEOS, HSQ and etch back



<Programming characteristics> <Erase characteristics>

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101-0.50.00.51.01.52.02.53.03.54.04.55.05.5

Initial

20V 22V 24V

∆Vth (

V)

Time(s)10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101

-6.0-5.5-5.0-4.5-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.00.5

Initial

-18V -20V -22V -24V

∆Vth (

V)

Time(s)

q Radius of Si channel = 15 nm


Outline

I. Introduction


III.III. NOR Cell and Array StructureNOR Cell and Array Structure



VI. Conclusions


Cone Structure (1)Cone Structure (1)

q Utilization of field and current concentration- field concentration in the horizontal direction- current concentration in the vertical direction

Drainr1

r2

ErER

Source

Cut line

Gate

Drain junction

ONO layer

flux

Electric field

high flux density

low flux density

Cut line

Gate

Drain junction

ONO layer

Gate

SiOO N

high flux density

low flux density



q Simple array structure- common source architecture- word line connection through small spacing of cones



q Electrical characteristics

1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 10

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

CHEI Program( VG: 6 V, V

D:4 V)

VT

H (

V)

Time (s)

CHEI Program( VG: 6 V, V

D:3 V)

FN Erase ( VB : 11 V)

100

101

102

103

104

105

106

107

1080.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.160 V

Erase stateV T

H(V

)

Time (s)

Retention Characteristics(150oC)program state

2.363 V

<Program/erase characteristics> <Retention characteristic>


Outline

I. Introduction

II. NAND Cell and Array Structure


IV.IV. AND Cell and Array StructureAND Cell and Array Structure


VI. Conclusions


lowlowhighdensity

highhighlowsensing speed

highLowhighprogram efficiency

ANDNORNAND

W/L

F-Poly

LSL LBL Active

Schematic Top View

< NAND > < NOR > < AND >

Conventional Flash Memory StructuresConventional Flash Memory Structures


q Memory cell device with vertical and double gate structures- vertical structure, S/D junctions connected by diffusion layerà High integration density.

- double gate structure.à High device performance, high sensing speed.

N

N

P

N

N

P

P

N

N

P

N

N

P

N

N

P

P

N

N

P

N

N

P

N

N

P

P

N

N

P

Vertical AND Structure (1)Vertical AND Structure (1)


N

N

P

N

N

P

N P

P

N

P

P

N

N

P

N

N

P

P

N

N

P

N

N

NN

N

P

P

N

N

P

N

N

P

P

N

N

P

N

N

N

P

P

N

N

P

N

N

P

P

N

N

P

N

N

N

N

P

N

N

P

P

N

N

P

N

N

P

N P

N

N

P

N

N

P

P

N

N

P

N

N

P

N P

N

N

P

N

N

P

P

N

N

P

N

N

P

N P

N

N

N

P

N

N

P

P

N

N

P

N

N

P

N P

N

(a) (b) (c) (d)

(e)(f)(g)(h)





10-7 10-6 10-5 10-4 10-3 10-2 10-1

2

3

4

5

6

7

Th

resh

old

Vo

ltag

e [V

]

Programming Time (sec)

VG = 13 V

VG = 15 V

VG = 17 V

10-5 10-4 10-3 10-2 10-1 1002

3

4

5

6

7

Th

resh

old

Vo

ltag

e [V

]

Erasing Time (sec)

VG = 13 V

VG = 15 V

VG = 17 V

<Program characteristics> <Erase characteristics>

q Program/erase characteristics


Outline

I. Introduction




V.V. STAR NAND Flash StructureSTAR NAND Flash Structure

VI. Conclusions

NanoForum'09 SNU SNU SoEECSSoEECS & ISRC& ISRC24

q Stacked bit-linesà high density

q Cylindrical channel and gate-all-around cell structureà high performance

q Single-crystal Si channelà high performance,

uniformity, reliability

STAR NAND Flash Structure (1)

Si substrate

Si

oxide

Si

oxide

gate

cylindrical channel

ONO dielectrics

gate

body

WL direction


Si substrate

SiGe

Si

SiGe

Si

SiGe

nitride

Si substrate

SiGe

Si

SiGe

Si

SiGe

nitride

Si substrate

SiGe

Si

SiGe

Si

SiGe

nitride

maska > b

Si substrate

SiGe

Si

SiGe

Si

SiGe

nitridea > b

Si substrate

Si

Si

nitride

SiGe

Si substrate

Si

Si

nitride

SiGe




Si substrate

nitride

Si

Si

ONO

Si substrate

Si

ONO

SiGe

Si

gate

Si

Si substrate

Si

oxide

Si

oxide

gate

cylindrical channel

ONO dielectrics

gate

body

WL direction


q Fabrication procedure (continued)

NanoForum'09 SNU SNU SoEECSSoEECS & ISRC& ISRC27


q Components of stack and nanowire implementation

<Selectively etched SiGe> <Rounded Si nanowire>


Conclusions (1)

q Charge trap flash memory including SONOS structure is a promising candidate for the next generation high density flash memories.

q For NAND application, arch SONOS flash memory is proposed for field concentration and suppression of back tunneling and is successfully demonstrated.

q For NOR application, cone SONOS flash memory is proposed for field and current concentration, and the fabricated cell shows superb electrical characterics.


Conclusions (2)

q For AND application, vertical AND structure is proposed for drastic reduction of cell size and the feasibility is demonstrated.

q For further increase of density, STacked ARray (STAR) NAND array is proposed.

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