Multiport Serial Communication Interface Controller

Multiport Serial Communication Interface Controller

ABSTRACT:

Most digital messages are vastly longer than the just a few bits. Because it

is neither practical nor economic to transfer all bits of a long message

simultaneously the message is broken into small parts & transmitted sequentially.

This project deals with the designing of the Programmable Serial Communication

Interface IP core. In general, micro controllers have a single non-programmable serial

port. The project here designs a multi-channel (eight serial ports) serial port

interface to the host processor/controller which contains the logic for multiplexing

many serial ports on one side to the available single serial port of the micro

controller/processor other side. This design even includes the Synchronization

between Transmitter and Receiver blocks, Accessing the devices with software

programming(Masking/Unmasking),Programmable number of channels and baud

rate generator, Data integration-Error handling method (CRC

generation/check),TXFIFO and RXFIFO data buffering mechanism and Packet based

transmission and reception with protocol implementation. Serial Port Architecture

mainly consists of the blocks Such as Transmitter framer Block Receiver framer

Block, Transmitter State Machine Controller (TSMC), Receiver State Machine

Controller (RSMC), Tx/Rx Control & Status Logic, TX & Rx FIFO interfacing Logic, Baud

Rate Generator, and Receiver Synchronization.

The overall System Architecture will be designed using HDL language

and simulation, synthesis and FPGA implementation (Translation, Mapping, Placing

and Routing) will be done using various FPGA based EDA Tools.

INDEX

Dept Of ECE, SITS, Khammam 1


P.NO

1. INTRODUCTION 3-20

1.1 Data Communication 3

1.2 Parallel Communication 4

1.3 Serial Communication 8

1.4 SPI Devices 15

2. INTRODUCTION TO VERILOG & VLSI 21-42

3. ARCHITECTURE OF THE PROJECT 43

4. MODULES 44-59

4.1 FIFO 44

4.2 Multiplexer/De Multiplexer 46

4.3 Parallel to Serial converter 49

4.4 Serial to Parallel converter 51

4.5 CRC 53

4.6 DLC 56

4.7 SMC 56

5. RESULT DISCUSSION 60-78

5.1 Simulation Result

5.2 Synthesis Result

5.3 RTL Schematic View

6. ADVANTAGES & DISADVANTAGES 79

7. CONCLUSION & FURTHER SCOPE 80

8. REFERENCES 81

1. INTRODUCTION:



1.1 Data Communication:

The distance over which data moves within a computer may vary from a few

thousandths of an inch, as is the case within a single IC chip, to as much as several

feet along the back-plane of the main circuit board. Over such small distances,

digital data may be transmitted as direct, two-level electrical signals over simple

copper conductors. Except for the fastest computers, circuit designers are not very

concerned about the shape of the conductor or the analog characteristics of signal

transmission. Frequently, however, data must be sent beyond the local circuitry that

constitutes a computer. In many cases, the distances involved may be enormous.

Unfortunately, as the distance between the source of a message and its destination

increases, accurate transmission becomes increasingly difficult. This results from the

electrical distortion of signals traveling through long conductors, and from noise

added to the signal as it propagates through a transmission medium. Although some

precautions must be taken for data exchange within a computer, the biggest

problems occur when data is transferred to devices outside the computer's circuitry.

In this case, distortion and noise can become so severe that information is lost. Data

Communications concerns the transmission of digital messages to devices external

to the message source. "External" devices are generally thought of as being

independently powered circuitry that exists beyond the chassis of a computer or

other digital message source. As a rule, the maximum permissible transmission rate

of a message is directly proportional to signal power and inversely proportional to

channel noise. It is the aim of any communications system to provide the highest

possible transmission rate at the lowest possible power and with the least possible

noise.

1.1.1 Communications Channels:



A communications channel is a pathway over which information can

be conveyed. A physical wire that connects communicating devices may define it, or

by a radio, laser, or other radiated energy source that has no obvious physical

presence. Information sent through a communications channel has a source from

which the information originates, and a destination to which the information is

delivered. Although information originates from a single source, there may be more

than one destination, depending upon how many receive stations are linked to the

channel and how much energy the transmitted signal possesses.

In a digital communications channel, the information is represented by individual

data bits, which may be encapsulated into multibit message units. A byte, which

consists of eight bits, is an example of a message unit that may be conveyed

through a digital communications channel. A collection of bytes may itself be

grouped into a frame or other higher-level message unit. Such multiple levels of

encapsulation facilitate the handling of messages in a complex data communications

network.

1.2 Parallel Communication:

In parallel communications there are more wires running between the

two systems and therefore both the spatial (which wire) and temporal (when)

dimensions are available for the data. In a parallel communication problem there is

just as great a need for a protocol and flow control as in the case of serial

communications. Parallel communications however tends to have a greater

emphasis on flow control or "handshaking" for a variety of reasons. The need for

handshakes is really a property of the fact that two devices are running

asynchronously to each other and therefore it is necessary to be able to

communicate the fact that the data is ready/taken to the other device. A handshake

may be "tighter" or "looser" depending upon the circumstances. The simplest idea

of a parallel handshake is a device which puts a line up when it is ready with data

(Data Ready or DR) and then waits for the interrogating device to take the data. It

must then immediately remove the request; otherwise the interrogator may well try



to read the data again. Thus the regime is as shown in the diagram. Now in some

devices it is reasonably easy to see whether the data has been read, particularly if

you have access to the computer bus signals and can see whether a read has been

done on the appropriate location. However if the bus signals are not available then

some other means must be invoked, i.e. another communication line, "Data Taken"

(DT), to tell the device that data has been taken.

Figure: parallel communication (http://googlepages/parallelcommunication)

Parallel ports were originally developed by IBM as a way to connect a printer to a PC.

When IBM was in the process of designing the PC, the company wanted the

computer to work with printers offered by Centronics, a top printer manufacturer at

the time. IBM decided not to use the same port interface on the computer that

Centronics used on the printer. Instead, IBM engineers coupled a 25-pin connector,

DB-25, with a 36-pin Centronics connector to create a special cable to connect the

printer to the computer. Other printer manufacturers ended up adopting the

Getronics interface, making this strange hybrid cable an unlikely de facto standard.

When a PC sends data to a printer or other device using a parallel port, it sends 8

bits of data (1byte) at a time. These 8 bits are transmitted parallel to each other. The

standard parallel port is capable of sending 50 to 100 kilobytes of data per second.

1.2.1 Types of parallel port:

At the present time it is known four types of parallel port:



Standard parallel port (SPP)

Parallel port PS/2 (bidirectional)

Enhanced Parallel Port (EPP)

Extend Capability Port (ECP)

SPP/EPP/ECP:

The original specification for parallel ports was unidirectional, meaning that

data only traveled in one direction for each pin. With the introduction of the PS/2 in

1987, IBM offered a new bidirectional parallel port design. This mode is commonly

known as Standard Parallel Port (SPP) and has completely replaced the original

design. Bidirectional communication allows each device to receive data as well as

transmit it. Many devices use the eight pins (2 through 9) originally designated for

data. Using the same eight pins limits communication to half-duplex, meaning that

information can only travel in one direction at a time. But pins 18 through 25,

originally just used as grounds, can be used as data pins also. This allows for full-

duplex (both directions at the same time) communication.

Enhanced Parallel Port (EPP):

It was created by Intel, Xircom, and Zenith in 1991. EPP allows for much

more data, 500 kilobytes (KB) to 2 megabytes (MB), to be transferred each second. It

was targeted specifically for non-printer devices that would attach to the parallel

port; particularly storage devices that needed the highest possible transfer rate close

on the heels of the introduction of EPP.

Extended Capabilities Port (ECP):

Microsoft and Hewlett Packard jointly announced a specification called

Extended Capabilities Port (ECP) in 1992. While EPP was geared toward other

devices, ECP was designed to provide improved speed and functionality for printers.

In 1994, the IEEE 1284 standard was released. It included the two specifications for

parallel port devices, EPP and ECP. In order for them to work, both the operating



system and the device must support the required specification. This is seldom a

problem today since most computers support SPP, ECP and EPP and will detect which

mode needs to be used, depending on the attached device. If you need to manually

select a mode, you can do so through the BIOS (Basic Input/output System) on most

computers.

1.2.2 Advantages of Parallel Data Transmission:

Fastest form of transmission -- able to send multiple bits simultaneously

Doesn’t require high frequency of operation

1.2.3 Disadvantages of Parallel Data Transmission:

Requires separate lines for each bit of a word

Costly to run long distances due to multiple wires

Suffers from electromagnetic interference

Cable lengths more limited than a serial cable

1.2.4 Applications:

Parallel ports can be used to connect a host of popular computer peripherals:

such as prints, scanners, CD burners, external hard drives, Iomega zip, network

adapters, and tape backup drives.

1.3 Serial Communication:

Serial is a device communication protocol that is standard on almost

every PC. Do not confuse it with universal serial bus (USB). Most computers include

two EIA-232 based serial ports. Serial is also a common communication protocol for

instrumentation in many devices, and numerous GPIB-compatible devices come with

an EIA-232 port. Furthermore, you can use serial communication for data acquisition

in conjunction with a remote sampling device. Note that EIA-232 and EIA-485/422.

The concept of serial communication is simple. The serial port sends and receives



bytes of information one bit at a time. Although this is slower than parallel

communication, which allows the transmission of an entire byte at once, it is simpler

and you can use it over longer distances. For example, the IEEE 488 specifications

for parallel communication state that the cabling between equipment can be no

more than 20m (65ft) total, with no more than 2m (6.5ft) between any two devices;

serial, however, can extend as much as 1200ft. typically, engineers use serial to

transmit ASCII data. They complete communication using three transmission lines --

ground, transmit, and receive. Because serial is asynchronous, the port can transmit

data on one line while receiving data on another. Other lines are available for

handshaking but are not required. The important serial characteristics are baud rate,

data bits, stop bits, and parity. For two ports to communicate, these parameters

must match:

1) Baud rate is a speed measurement for communication that indicates the number

of bit transfers per second. For example, 300 baud is 300 bits per second. When

engineers refer to a clock cycle, they mean the baud rate, so if the protocol calls

for a 4800 baud rate, the clock is running at 4800 Hz. This means that the serial

port is sampling the data line at 4800 Hz. Common baud rates for telephone lines

are 14400, 28800, and 33600. Baud rates greater than these are possible, but

these rates reduce the distance by which engineers can separate devices. They

use these high baud rates for device communication where the devices are

located together, as is typically the case with GPIB devices.

2) Data bits are a measurement of the actual data bits in a transmission. When the

computer sends a frame of information, the amount of actual data may not be a

full 8 bits. Standard values for frames are 5, 7, and 8 bits. Which setting you

choose depends on what information you are transferring. For example, standard

ASCII has values from 0 to 127 (7 bits). Extended ASCII uses 0 to 255 (8 bits). If

the data you are transferring is standard ASCII, sending 7 bits of data per frame is

sufficient for communication. A frame refers to a single byte transfer, including



start/stop bits, data bits, and parity. Because the number of actual bits depends

on the protocol selected, you can use the term "frame" to cover all instances.

3) Stop bits are used to signal the end of communication for a single frame. Typical

values are 1, 1.5, and 2 bits. Because the data is clocked across the lines and

each device has its own clock, it is possible for the two devices to become slightly

out of sync. Therefore, the stop bits not only indicate the end of transmission but

also give the computers some room for error in the clock speeds. The more bits

used for stop bits, the greater the lenience in synchronizing the different clocks,

but the slower the data transmission rate.

4) Parity is a simple form of error checking used in serial communication. There are

four types of parity -- even, odd, marked, and spaced. You also can use no parity.

For even and odd parity, the serial port sets the parity bit (the last bit after the

data bits) to a value to ensure that the transmission has an even or odd number

of logic-high bits. For example, if the data is 011, for even parity, the parity bit is

0 to keep the number of logic-high bits even. If the parity is odd, the parity bit is

1, resulting in 3 logic-high bits. Marked and spaced parity does not actually check

the data bits but simply sets the parity bit high for marked parity or low for

spaced parity. This allows the receiving device to know the state of a bit so the

device can determine if noise is corrupting the data or if the transmitting and

receiving device clocks are out of sync.

Serial communications send a single bit at a time between computers. This only

requires a single communication channel, as opposed to 8 channels to send a byte.

With only one channel the costs are lower, but the communication rates are slower.

The communication channels are often wire based, but they may also be can be

optical and radio. Figure 48 shows some of the standard electrical connections. RS-

232c is the most common standard that is based on a voltage change levels. At the

sending computer an input will either be true or false. The line driver will convert a

false value in to a Txd voltage between +3V to +15V, true will be between -3V to -

15V. A cable connects the Txd and com on the sending computer to the Rxd and



com inputs on the receiving computer. The receiver converts the positive and

negative voltages back to logic voltage levels in the receiving computer. The cable

length is limited to 50 feet to reduce the effects of electrical noise. When RS-232 is

used on the factory floor, care is required to reduce the effects of electrical noise -

careful grounding and shielded cables are often used.

1.3.1 Types of Serial communication:

Any communications channel has a direction associated with it:

Fig: Types of channel (http://googlepages/serialcommunication)

The message source is the transmitter, and the destination is the receiver

Simplex Channel:

A channel whose direction of transmission is unchanging is

referred to as a simplex channel.For example, a radio station is a simplex

channel because it always transmits the signal to its listener and never

allows them to transmit back.

Half-duplex Channel :

It is a single physical channel in which the direction may be

reversed. Messages may flow in two directions, but never at the same time,

in a half duplex system. In a telephone call, one party speaks while the other

listens. After a pause, the other party speaks and the first party listens.

Speaking simultaneously results in garbled sound that cannot be understood.



Full-duplex Channel :

It allows simultaneous message exchange in both directions. It

really consists of two simplex channels, a forward channel and a reverse

channel, linking the same points. The transmission rate of the reverse

channel may be slower if it is used only for flow control of the forward

channel.

1.3.2 Asynchronous vs. Synchronous Transmission:

Serialized data is not generally sent at a uniform rate through a channel.

Instead, there is usually a burst of regularly spaced binary data bits followed by a

pause, after which the data flow resumes. Packets of binary data are sent in this

manner, possibly with variable-length pauses between packets, until the message

has been fully transmitted. In order for the receiving end to know the proper

moment to read individual binary bits from the channel, it must know exactly

when a packet begins and how much time elapses between bits. When this timing

information is known, the receiver is said to be synchronized with the transmitter,

and accurate data transfer becomes possible. Failure to remain synchronized

throughout a transmission will cause data to be corrupted or lost.

Two basic techniques are employed to ensure correct synchronization. In

synchronous systems, separate channels are used to transmit data and timing

information. The timing channel transmits clock pulses to the receiver. Upon

receipt of a clock pulse, the receiver reads the data channel and latches the bit

value found on the channel at that moment. The data channel is not read again

until the next clock pulse arrives. Because the transmitter originates both the

data and the timing pulses, the receiver will read the data channel only when told

to do so by the transmitter (via the clock pulse), and synchronization is

guaranteed. Techniques exist to merge the timing signal with the data so that

only a single channel is required. This is especially useful when synchronous

transmissions are to be sent through a modem. Two methods in which a data

signal is self-timed are no return-to-zero and biphase Manchester coding. These



both refer to methods for encoding a data stream into an electrical waveform for

transmission.

In asynchronous systems, a separate timing channel is not used. The

transmitter and receiver must be preset in advance to an agreed-upon baud rate.

A very accurate local oscillator within the receiver will then generate an internal

clock signal that is equal to the transmitters within a fraction of a percent. For the

most common serial protocol, data is sent in small packets of 10 or 11 bits, eight

of which constitute message information. When the channel is idle, the signal

voltage corresponds to a continuous logic '1'. A data packet always begins with a

logic '0' (the start bit) to signal the receiver that a transmission is starting. The

start bit triggers an internal timer in the receiver that generates the needed clock

pulses. Following the start bit, eight bits of message data are sent bit by bit at the

agreed upon baud rate. The packet is concluded with a parity bit and stop bit. One

complete packet is illustrated below:

The packet length is short in asynchronous systems to minimize the risk that the

local oscillators in the receiver and transmitter will drift apart. When high-quality



crystal oscillators are used, synchronization can be guaranteed over an 11-bit period.

Every time a new packet is sent, the start bit resets the synchronization, so the

pause between packets can be arbitrarily long. Note that the EIA232 standard

defines electrical, timing, and mechanical characteristics of a serial interface.

However, it does not include the asynchronous serial protocol shown in the previous

figure, or the ASCII alphabet described next.

1.3.3 Hand shaking:

Handshaking is a procedure used to check the link between DTE & DCE

before transmitting of data. Data is transmitted and received on pins 2 and 3

respectively (for both types 25 & 9 pin).

1. DTE would request to send data to DCE (RTS).

2. The DCE will indicate to DTE that it is ready and clear to send data (CTS).

Both RTS and CTS therefore used to control data flow between DTE & DCE. Data Set

Ready (DSR) is an indication from the DCE (i.e., the modem) that it is ON. Similarly,

DTR (i.e., the PC) indicates to the Data Set that the DTE is on. Data Carrier Detect

(CD) indicates that a good carrier is being received from the remote modem.

1.3.4 Baud rate :

Baud rate is a measurement of transmission speed in asynchronous

communication, it represents the number of bits that are actually being sent over

the serial link. The Baud count includes the overhead bits Start, Stop and Parity that

are generated by the sending UART and removed by the receiving UART.

1.3.5 Type of cables:

(A) Modem Cable:

A normal modem cable runs straight through with pin 1 to pin 1, pin 2 to pin 2

etc. The end that will be connected to the terminal or PC is a female connector, and

the end that will be connected to the modem is male connector.

(B) Null Modem Cables:



When you need to connect two equipments with both (DTE) or both (DCE), for

example connecting two PC's, then in this case you have to use the cable with below

pin connection (25 to 25). And this is called Null modem cable.

1.3.6 Advantages of serial communication:

One of the advantages is transmission distance, serial link can send data to a

remote device more far then parallel link. Also the cable connection of serial link is

simpler then parallel link and uses less number of wires. Serial link is used also for

Infrared communication, now many devices such as laptops & printers can

communicate via inferred link.

1.4 Serial Peripheral Interface (SPI):

The Serial Peripheral Interface is used primarily for a synchronous

serial communication of host processor and peripherals. In the standard

configuration for a slave device (see illustration 1), two control and two data lines

are used. The data output SDO serves on the one hand the reading back of data,

offers however also the possibility to cascade several devices. The data output of the

preceding device then forms the data input for the next IC.

fig1: SPI slave

There is a MASTER and a SLAVE mode. The MASTER device provides the clock signal

and determines the state of the chip select lines, i.e. it activates the SLAVE it wants

to communicate with. CS and SCKL are therefore outputs.



The SLAVE device receives the clock and chip select from the

MASTER, CS and SCKL are therefore inputs. This means there is one master, while

the number of slaves is only limited by the number of chip selects. A SPI device can

be a simple shift register up to an independent subsystem. The basic principle of a

shift register is always present. Command codes as well as data values are serially

transferred, pumped into a shift register and are then internally available for parallel

processing. Here we already see an important point that must be considered in the

philosophy of SPI bus systems: The length of the shift registers is not fixed, but can

differ from device to device. Normally the shift registers are 8Bit or integral multiples

of it. Of course there also exist shift registers with an odd number of bits. For

example two cascaded 9Bit EEPROMs can store 18Bit data. The micro controller

configured as a slave behaves like a normal peripheral device. The second possibility

works with several masters and is therefore named multi-master protocol. Each

micro processor has the possibility to take the roll of the master and to address

another micro processor. One controller must permanently provide a clock signal.

The MC68HC11 provides hardware error recognition, useful in multiple-master

systems. There are two SPI system errors. The first occurs if several SPI devices want

to become master at the same time. The other is a collision error that occurs for

example when SPI devices work with different polarities. More details can be found in

the MC68HC11 manual.

1.4.1 UART:

The Universal Asynchronous Receiver Transmitter (UART) is a popular and

widely-used device for data communication in the field of telecommunication. There

are different versions of UARTs in the industry. Some of them contain FIFOs for the

receiver/transmitter data buffering and some of them have the 9 Data bits mode

(Start bit + 9Data bits + Parity + Stop bits). This application note describes a fully

configurable UART optimized for and implemented in a variety of Lattice devices,

which have superior performance and architecture compared to existing

semiconductor ASSPs (application-specific standard products).



This UART reference design contains a receiver and a transmitter. The receiver

performs serial-to-parallel conversion on the asynchronous data frame received from

the serial data input SIN. The transmitter performs parallel-to serial conversion on

the 8-bit data received from the CPU. In order to synchronize the asynchronous serial

data and to insure the data integrity, Start, Parity and Stop bits are added to the

serial data. An example of the UART frame format is shown in Figure 1 below.

This design can also be instantiated many times to get multiple UARTs in the same device. For

easily embedding the design into a larger implementation, instead of using tri-state buffers, the

bi-directional data bus is separated into two buses, DIN and DOUT. The transmitter and receiver

both share a common internal Clk16X clock. This internal clock which needs to be 16 times of

the desired baud rate clock frequency is obtained from the on-board clock through the MCLK

input directly. However, when implementing the design into is MACH™ 5000VG devices, the

Clk16X clock can be generated flexibly through the isMACH 5000VG on-chip PLL by using

MCLK as the PLL reference clock input.

1.4.2 USB:

A core team from Compaq, Hewlett Packard, Intel, Lucent, Microsoft, NEC and

Philips is leading the development of the USB Specification, version 2.0 that will

increase data throughput by a factor of 40. This backwards-compatible extension of

the USB 1.1 specification uses the same cables, connectors and software interfaces

so the user will see no change in the usage model. They will, however, benefit from

an additional range of higher performance peripherals, such as video-conferencing

cameras, next-generation scanners and printers, and fast storage devices, with the

same ease-of-use features as today’s USB peripherals.



Impact to Use:

From a user’s perspective, USB 2.0 is just like USB, but with much

higher Bandwidth. It will look the same and behave the same, but with a

larger choice of More interesting, higher performance devices available. Also,

all of the USB Peripherals the user has already purchased will work in a USB

2.0-capable System.

Impact to PC Manufacturer:

USB 2.0 will provide system manufacturers the ability to connect to high

Performance peripherals in the least expensive way. The additional

performance Capabilities of USB 2.0 can be added with little impact to overall

system cost. Indeed, high-bandwidth interfaces such as SCSI adapters may

no longer be required in some systems, leading to a net saving of system

cost. Simple construction will result since only USB connectors will be needed

on many futures PCs. Today’s ubiquitous USB connectors will become USB

2.0, superseding USB 1.1.

Impact to Peripheral Manufacturer:

Today’s USB devices will operate with full compatibility in a USB 2.0

system. Peripherals, while enabling retail products to transition with the

installed base. Support of USB 2.0 is recommended for hubs and higher

bandwidth peripherals. Designing a USB 2.0 peripheral will be a similar

engineering effort to that of designing a USB 1.1 peripheral. Some low-speed

peripherals, such as HID devices, may never be redesigned to support the

USB 2.0 high-speed capability in order to maintain the absolute lowest cost.

The Universal Serial Bus was originally developed in 1995 by many of the same

industry leading companies currently working on USB 2.0. The major goal of USB was

to define an external expansion bus which makes adding peripherals to a PC as easy

as hooking up a telephone to a wall-jack. The program’s driving goals were ease-of-

use and low cost. These were enabled with external expansion architecture, as

shown in Figure 1, which highlights:



PC host controller hardware and software,

Robust connectors and cable assemblies,

Peripheral friendly master-slave protocols,

Expandable through multi-port hubs.

An understanding of the roles of each of the major elements within a USB 1.1 system

will better show the evolutionary step that USB 2.0 provides.

Role of Host PC hardware and software:

The role of the system software is to provide a uniform view of IO system

for all applications software. It hides hardware implementation details so that

application software is more portable. For the USB IO subsystem in particular, it

manages the dynamic attach and detach of peripherals. This phase, called

enumeration, involves communicating with the peripheral to discover the identity

of a device driver that it should load, if not already loaded. A unique address is

assigned to each peripheral during enumeration to be used for run-time data

transfers. During run-time the host PC initiates transactions to specific



peripherals, and each peripheral accepts its transactions and responds

accordingly. Additionally the host PC software incorporates the peripheral into the

system power management scheme and can manage overall system power

without user interaction.

Role of the hub:

Besides the obvious role of providing additional connectivity for USB

peripherals, a hub provides managed power to attached peripherals. It recognizes

dynamic attachment of a peripheral and provides at least 0.5W of power per

peripheral during initialization. Under control of the host PC software, the hub may

provide more device power, up to a maximum of 2.5W, for peripheral operation. A

newly attached hub will be assigned its unique address, and hubs may be

cascaded up to five levels deep. During run-time a hub operates as a bi-

directional repeater and will repeat USB signals as required on upstream (towards

the host) and downstream (towards the device) cables. The hub also monitors

these signals and handles transactions addressed to it. All other transactions are

repeated to attach devices. A hub supports both 12Mb/s (full-speed) and 1.5Mbs

(low speed) peripherals.

Role of the peripheral:

All USB peripherals are slaves that obey a defined protocol. They must

react to request transactions sent from the host PC. The peripheral responds to

control transactions that, for example, request detailed information about the

device and its configuration. The peripheral sends and receives data to/from the

host using a standard USB data format. This standardized data movement to/from

the PC host and interpretation by the peripheral gives USB its enormous flexibility

with little PC host software changes. USB 1.1 peripherals can operate at 12Mb/s or

1.5Mb/s.



2. INTRODUCTION TO VERILOG & VLSI:

2.1 INTRODUCTION TO VLSI:-

The first digital circuit was designed by using electronic

components like vacuum tubes and transistors. Later Integrated Circuits (ICs) were

invented, where a designer can be able to place digital circuits on a chip consists of

less than 10 gates for an IC called SSI (Small Scale Integration) scale. With the

advent of new fabrication techniques designer can place more than 100 gates on

an IC called MSI (Medium Scale Integration). Using design at this level, one can

create digital sub blocks (adders, multiplexes, counters, registers, and etc.) on an

IC. This level is LSI (Large Scale Integration), using this scale of integration people

succeeded to make digital subsystems (Microprocessor, I/O peripheral devices and

etc.) on a chip. At this point design process started getting very complicated. i.e.,

manually conversion from schematic level to gate level or gate level to layout level

was becoming somewhat lengthy process and verifying the functionality of digital

circuits at various levels became critical.

With advent of new technology, i.e., CMOS (Complementary Metal Oxide

Semiconductor) process technology, one can fabricate a chip contains more than

Million of gates. At this point design process still became critical, because of

manual converting the design from one level to other. Using latest CAD tools could

solve the problem. Existence of logic synthesis tools design engineer can easily

translate to higher-level design description to lower levels. This way of designing

(using CAD tools) is certainly a revolution in electronic industry. This may be

leading to development of sophisticated electronic products for both consumer as

well as business. Designing Systems using Hardware always gives best results

when compared to software (like Speed Reliability, performance and etc.,) Using


Specifications

Behavioral Description

r

Simulation

Simulation

avioralSynthesis

Logic Synthesis

Gate Level Net list

Constraints

Constraints

Lib

AutomaticP&R

Layout

Logic simulation

Fabrication

LayOut Management


CMOS VLSI Design methodology designer could design and fabricate ICs without

spending much time when compared to traditional way of designing.

2.1.1 IC DESIGN FLOW:

Fig. 2.1: IC Design Flow


SPECIFICATION

Behavioral simulation

Behavioral

Simulation

RTL Description

Functionlsimulation

Lib

Gate level netlist

Layout

Logic

simulation


2.1.2 FPGA:

A field-programmable gate array (FPGA) is an integrated circuit

designed to be configured by the customer or designer after manufacturing—hence

"field-programmable". The FPGA configuration is generally specified using a

hardware description language (HDL), similar to that used for an application-specific

integrated circuit (ASIC).

FPGAs contain programmable logic components called "logic blocks", and a

hierarchy of reconfigurable interconnects that allow the blocks to be "wired

together"— somewhat like a one-chip programmable breadboard. Logic blocks can

be configured to perform complex combinational functions. In most FPGAs, the logic

blocks also include memory elements, which may be simple flip-flops or more

complete blocks of memory. FPGA provides its user a way to configure:

1. The intersection between the logic blocks and

2. The function of each logic block.

Logic block of an FPGA can be configured in such a way that it can provide

functionality as simple as that of transistor or as complex as that of a

microprocessor. It can used to implement different combinations of combinational

and sequential logic functions. Logic blocks of an FPGA can be implemented by any

of the following:

1. Transistor pairs

2. Combinational gates like basic NAND gates or XOR gates

N-input Lookup tables

3. Multiplexers

4. Wide fan-in AND-OR structure.



Fig: Simplified internal architecture of FPGA(http://googlepages/introduction to vlsi)

Routing in FPGAs consists of wire segments of varying lengths which can be

interconnected via electrically programmable switches.

2.1.3 FPGA Design Flow:

The ISE™ design flow comprises the following steps: design entry, design

synthesis, design implementation, and Xilinx® device programming. Design

verification, which includes both functional verification and timing verification, takes

places at different points during the design flow. This section describes what to do

during each step. For additional details on each design step, click a box in the

following figure.

Fig: FPGA Design Flow (http://googlepages/introductiontovlsi)

Design Entry:

Create an ISE project as follows:



1. Create a project.

2. Create files and add them to your project, including a user constraints (UCF)

file.

3. Add any existing files to project.

4. Assign constraints such as timing constraints, pin assignments, and area

constraints.

Functional Verification:

We can verify the functionality of design at different points in the design flow as

follows:

1. Before synthesis, run behavioral simulation (also known as RTL simulation).

2. After Translate, run functional simulation (also known as gate-level

simulation), using the SIMPRIM library.

3. After device programming, run in-circuit verification.

Design Synthesis:

Synthesize design.

Design Implementation:

Implement design as follows:

1. Implement your design, which includes the following steps:

Translate

Map

Place and Route

2. Review reports generated by the Implement Design process, such as the Map

Report or Place & Route Report, and change any of the following to improve your

design:

Process properties

Constraints

Source files

3. Synthesize and implement your design again until design requirements are met.



Timing Verification:

We can verify the timing of your design at different points in the design flow as

follows:

1. Run static timing analysis at the following points in the design flow:

After Map

After Place & Route

2. Run timing simulation at the following points in the design flow:

After Map (for a partial timing analysis of CLB and IOB delays)

After Place and Route (for full timing analysis of block and net delays)

2.2 INTRODUCTION TO VERILOG :

Verilog HDL is one of the two most common Hardware Description

Languages (HDL) used by integrated circuit(IC) designers. The other one is VHDL.

HDL’s allows the design to be simulated earlier in the design cycle in order to correct

errors or experiment with different architectures. Designs described in HDL are

technology-independent, easy to design and debug, and are usually more readable

than schematics, particularly for large circuits.

Verilog can be used to describe designs at four levels of abstraction:

(i) Algorithmic level (much like c code with if, case and loop statements).

(ii) Register transfer level (RTL uses registers connected by Boolean equations).

(iii) Gate level (interconnected AND, NOR etc.).

(iv) Switch level (the switches are MOS transistors inside gates).

The language also defines constructs that can be used to control the input and

output of simulation. More recently Verilog is used as an input for synthesis

programs which will generate a gate-level description (a net list) for the circuit. Some

Verilog constructs are not synthesizable. Also the way the code is written will greatly

affect the size and speed of the synthesized circuit. Most readers will want to

synthesize their circuits, so no synthesizable constructs should be used only for test

benches. These are program modules used to generate I/O needed to simulate the



rest of the design. The words “not synthesizable” will be used for examples and

constructs as needed that do not synthesize.

There are two types of code in most HDLs:

Structural, this is a verbal wiring diagram without storage.

assign a=b & c | d; /* “|” is a OR */

assign d = e & (~c);

Here the order of the statements does not matter. Changing e will change a.

Procedural which is used for circuits with storage, or as a convenient way to write

conditional logic.

always @ (posedge clk) // Execute the next statement on every rising clock edge.

Count <= count+1;

Procedural code is written like c code and assumes every assignment is stored in

memory until over written. For synthesis, with flip-flop storage, this type of thinking

generates too much storage. However people prefer procedural code because it is

usually much easier to write, for example, if any case statements are only allowed in

procedural code. As a result, the synthesizers have been constructed which can

recognize certain styles of procedural code as actually combinational. They generate

a flip-flop only for left-hand variables which truly need to be stored. However if you

stray from this style, beware. Your synthesis will start to fill with superfluous latches.

This manual introduces the basic and most common Verilog behavioral and gate-

level modeling constructs, as well as Verilog compiler directives and system

functions. Full description of the language can be found in Cadence Verilog-XL

Reference Manual and Synopsys HDL Compiler for Verilog Reference Manual. The

latter emphasizes only those Verilog constructs that are supported for synthesis by

the Synopsys Design Compiler synthesis tool. In all examples, Verilog keywords are

shown in boldface. Comments are shown in italics.

2.2.1 Lexical Tokens:

White Space:



White spaces separate words and can contain spaces, tabs, new-lines

and form feeds. Thus a statement can extend over multiple lines without

special continuation characters.

Comments:

Comments can be specified in two ways (exactly the same way as in

C/C++):

Begin the comment with double slashes (//). All text between these

characters and the end of the line will be ignored by the Verilog compiler.

Enclose comments between the characters /* and */. Using this method allows

you to continue comments on more than one line. This is good for

“commenting out” many lines code, or for very brief in-line comments.

Numbers:

Number storage is defined as a number of bits, but values can be

specified in binary, octal, decimal or hexadecimal.

Examples are 3’b001, a 3-bit number, 5’d30, (=5’b11110), and 16‘h5ED4,

(=16’d24276)

Identifiers:

Identifiers are user-defined words for variables, function names,

module names, block names and instance names. Identifiers begin with a

letter or underscore (Not with a number or $) and can include any number of

letters, digits and underscores. Identifiers in Verilog are case-sensitive.

Operators:

Operators are one, two and sometimes three characters used to

perform operations on variables.

Examples include >, +, ~, &,! =. Operators are described in detail in

“Operators” on p. 6.

Verilog Keywords:



These are words that have special meaning in Verilog. Some examples

are assign, case, while, wire, reg, and, or, nand, and module. They should not

be used as identifiers.

2.2.2 Data Types:

Wire:

A wire represents a physical wire in a circuit and is used to connect gates

or modules. The value of a wire can be read, but not assigned to, in a function

or block. See “Functions” on p. 19, and “Procedures: Always and Initial Blocks”

on p. 18. A wire does not store its value but must be driven by a continuous

assignment statement or by connecting it to the output of a gate or module.

Other specific types of wires include:Wand (wired-AND); the value of a wand

depend on logical AND of all the drivers connected to it. Word (wired-OR); the

value of a word depend on logical OR of all the drivers connected to it. Tri

(three-state ;): all drivers connected to a tri must be z, except one (which

determines the value of the tri).

Syntax

wire [msb:lsb] wire_variable_list;

wand [msb:lsb] wand_variable_list;

Reg:

Declare type reg for all data objects on the left hand side of expressions

in initial and always procedures, or functions. See “Procedural Assignments”

on page 12. A reg is the data type that must be used for latches, flip-flops and

memory. However it often synthesizes into leads rather than storage. In multi-

bit registers, data is stored as unsigned numbers and no sign extension is

done for what the user might have thought were two’s complement numbers.

Syntax

reg [msb:lsb] reg_variable_list;

Integer:



Integers are general-purpose variables. For synthesois they are used

mainly loops-indices, parameters, and constants. See” Parameter” on p. 5.

They are of implicitly of type reg. However they store data as signed numbers

whereas explicitly declared reg types store them as unsigned. If they hold

numbers which are not defined at compile time, their size will default to 32-

bits. If they hold constants, the synthesizer adjusts them to the minimum

width needed at compilation

2.2.3 Operators:

Arithmetic Operators:

These perform arithmetic operations. The + and - can be used as either unary

(-z) or binary (x-y) operators.

Operators

+ (addition)

- (subtraction)

* (multiplication)

/ (division)

% (modulus)

Relational Operators:

Relational operators compare two operands and return a single bit 1or 0.

These operators synthesize into comparators. Wire and reg variables are

positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d110. However for integers

-1< 6.

Operators

< (less than)

<= (less than or equal to)

> (greater than)

>= (greater than or equal to)

== (equal to)



!= (not equal to)

Bit-wise Operators:

Bit-wise operators do a bit-by-bit comparison between two operands. However

see “Reduction Operators” on p. 7.

Operators

~ (bitwise NOT)

& (bitwise AND)

| (bitwise OR)

^ (bitwise XOR)

~^ or ^~ (bitwise XNOR)

Logical Operators:

Logical operators return a single bit 1 or 0. They are the same as bit-wise

operators only for single bit operands. They

can work on expressions, integers or groups of bits, and treat all values that

are nonzero as “1”. Logical operators are

typically use

Operators

! (logical NOT)

&& (logical AND)

|| (logical OR)

Reduction Operators:

Reduction operators operate on all the bits of an operand vector and return a

single-bit value. These are the unary (one

argument) form of the bit-wise operators above.

Operators

& (reduction AND)

| (reduction OR)

~& (reduction NAND)



~| (reduction NOR)

^ (reduction XOR)

~^ or ^~(reduction XNOR)

Shift Operators:

Shift operators shift the first operand by the number of bits specified by the

second operand. Vacated positions are

filled with zeros for both left and right shifts (There is no sign extension).

Operators

<< (shift left)

>> (shift right)

Concatenation Operator:

The concatenation operator combines two or more operands to form a larger

vector.

Operators

(concatenation)

2.2.4 Module Declaration:

A module is the principal design entity in Verilog. The first line of a

module declaration specifies the name and port list (arguments). The next few lines

specifies the i/o type (input, output or in out, see Sect. 4.4.) and width of each port.

The default port width is 1 bit. Then the port variables must be declared wire, wand,

reg (See Sect.4). The default is wire. Typically inputs are wire since their data is

latched outside the module. Outputs are type reg if their signals were stored inside

an always or initial block (See Sect. 10.).

Syntax

module module name (port_list);

input [msb:lsb] input_port_list;

output [msb:lsb] output_port_list;

inout [msb:lsb] inout_port_list;

... statements ...



Endmodule

2.2.5 Continuous Assignment:

The continuous assignment is used to assign a value onto a wire in a module. It

is the normal assignment outside of always or initial blocks (See Sect. 10. ).

Continuous assignment is done with an explicit assign statement or by assigning a

value to a wire during its declaration. Note that continuous assignment statements

are concurrent and are Continuously executed during simulation. The order of assign

statements does not matter. Any change in any of the right-hand-side inputs will

immediately change a left-hand-side output.

Syntax

wire wire_variable = value;

assign wire_variable = expression;

2.2.6 Module Instantiations:

Module declarations are templates from which one creates actual objects

(instantiations). Modules are instantiated inside other modules, and each

instantiation creates a unique object from the template. The exception is the top-

level module which is its own instantiation. The instantiated module’s ports must be

matched to those defined in the template.

Syntax for Instantiation

module_name

instance_name_1 (port_connection_list),

instance_name_2 (port_connection_list),

......

instance_name_n (port_connection_list);

2.2.7 Behavioral Modeling:

Verilog has four levels of modeling:

The switch level which includes MOS transistors modeled as switches.



The gate level. See “Gate-Level Modeling” on p. 3

The Data-Flow level. See Example 7 .4 on page 11

The Behavioral or procedural level described below.

Verilog procedural statements are used to model a design at a higher level of

abstraction than the other levels. They provide powerful ways of doing complex

designs. However small changes n coding methods can cause large changes in the

hardware generated. Procedural statements can only be used in procedures. Verilog

procedures are described later in “Procedures.

2.2.8 Procedural Assignments:

Procedural assignments are assignment statements used within

Verilog procedures (always and initial blocks). Only reg variables and integers (and

their bit/part-selects and concatenations) can be placed left of the “=” in procedures.

The right hand side of the assignment is an expression which may use any of the

operator.

2.2.9 Delay in Assignment (not for synthesis):

In a delayed assignment Δt time units pass before the statement is

executed and the left-hand assignment is made. With intra-assignment delay, the

right side is evaluated immediately but there is a delay of Δt before the result is

place in the left hand assignment. If another procedure changes a right-hand side

signal during Δt, it does not effect the output. Delays are not supported by synthesis

tool

Syntax for Procedural Assignment

Variable = expression

Delayed assignment

#Δt variable = expression;

Intra-assignment delay



Variable = #Δt expression

2.2.10 Blocking Assignments:

Procedural (blocking) assignments (=) are done sequentially in the order the

statements are written. A second assignment is not started until the preceding one is

complete.

Syntax

Blocking

Variable = expression;

Variable = #Δt expression;

grab inputs now, deliver ans later.

#Δt variable = expression;

grab inputs later, deliver ans later

2.2.11 No blocking (RTL) Assignments (see below for synthesis):

RTL (no blocking) assignments (<=), which follow each other in the code, are

started in parallel. The right hand side of no blocking assignments is evaluated

starting from the completion of the last blocking assignment or if none, the start of

the procedure. The transfer to the left hand side is made according to the delays. An

intra-assignment delay in a non-blocking statement will not delay the start of any

subsequent statement blocking or non-blocking. However a normal delays will are

cumulative and will delay the output.

For synthesis

• One must not mix “<=” or “=” in the same procedure.

• “<=” best mimics what physical flip-flops do; use it for “always @ (posedge

clk .) type procedures.

• “=” best corresponds to what c/c++ code would do; use it for combinational

procedures.

Syntax



Non-Blocking

variable <= expression;

variable <= #t expression;

#t variable <= expression;

The following example shows interactions between blocking and non-blocking for

simulation. Do not mix the two types in one procedure for synthesis.

8.5. begin ... end begin ... end block statements are used to group several

statements for use where one statement is syntactically allowed. Such places include

functions, always and initial blocks, if, case and for statements.

Syntax

begin: block_name

reg [msb:lsb] reg_variable_list;

integer [msb:lsb] integer_list;

parameter [msb:lsb] parameter_list;

... statements ...

end

1.if ... else if ... else

The if ... else if ... else statements execute a statement or block of statements

depending on the result of the expression following the if. If the conditional

expressions in all the if’s evaluate to false, then the statements in the else block,

if present, are executed.

There can be as many else if statements as required, but only one if block and

one else block. If there is one statement in a block, then the begin end

statements may be omitted. Both the else if and else statements are optional.

However if all possibilities are not specifically covered, synthesis will generated

extra latches.

Syntax

if (expression)

begin



... statements ...

end

else if (expression)

begin

... statements ...

end

...more else if blocks ...

else

begin

... statements ...

end

2. case:

The case statement allows a multipath branch based on comparing the

expression with a list of case choices. Statements in the default block executes

when none of the case choice comparisons are true. With no default, if no

comparisons are true, synthesizers will generate unwanted latches. Good practice

says to make a habit of putting in a default whether you need it or not. If the defaults

are don’t cares, define them as ‘x’ and the logic minimize will treat them as don’t

cares and save area.

Syntax

case (expression)

case_choice1:

begin

... statements ...

end

case_choice2:

begin

... statements ...



end

... more case choices blocks ...

default:

begin

... statements ...

end

endcase

2.2.12 Test Bench:

A test bench supplies the signals and dumps the outputs to simulate a

Verilog design (module(s)). It invokes the design under test, generates the

simulation input vectors, and implements the system tasks to view/format the

results of the simulation. It is never synthesized so it can use all Verilog commands.

To view the waveforms when using Cadence Verilog XL Simulator, use the Cadence-

specific Simulation History

Manager (SHM) tasks of $shm_open to open the file to store the waveforms, and

$shm_probe to specify the variables to be included in the waveforms list. You can

then use the Cadence cwaves waveform viewer by typing cwaves & at the UNIX

prompt.

Syntax

$shm_open(filename);

$shm_probe(var1, var2, ...)

Note also

var=$random

wait(condition) statement

2.2.13 SIMULATION TOOL:

1) Active HDL Overview:

Active-HDL is an integrated environment designed for development of

VHDL, Verilog, and EDIF and mixed VHDL-Verilog-EDIF designs. It comprises three



different design entry tools, VHDL'93 compiler, Verilog compiler, single simulation

kernel, several debugging tools, graphical and textual simulation output viewers,

and auxiliary utilities designed for easy management of resource files, designs,

and libraries

2) ACTIVE-HDL Macro Language:

The language has been designed to enable the user to work with Active-HDL

without using the graphical user interface (GUI).

a)HDL Editor:

HDL Editor is a text editor designed for HDL source files. It displays

specific syntax categories in different colors (keyword coloring). The editor is

tightly integrated with the simulator to enable debugging source code. The

keyword coloring is also available when HDL Editor is used for editing macro

files, Perl scripts, and Tcl scripts.

b)Block Diagram Editor:

Block Diagram Editor is a graphical tool designed to create block

diagrams. The editor automatically translates graphically designed diagrams

into VHDL or Verilog code

c)State Diagram Editor:

State Diagram Editor is a graphical tool designed to edit state machine

diagrams. The editor automatically translates graphically designed diagrams

into VHDL or Verilog code.

d)Waveform Editor:

Waveform Editor displays the results of a simulation run as signal

waveforms. It allows you to graphically edit waveforms so as to create desired

test vectors.

e)Design Browser:

The Design Browser window displays the contents of the current

design, that is:

a. Resource files attached to the design.



b. The contents of the default-working library of the design.

c. The structure of the design unit selected for simulation.

d. VHDL, Verilog, or EDIF objects declared within a selected region of the

current design.

f)Console window:

The Console window is an interactive input-output text device providing

entry for Active-HDL macro language commands, macros, and scripts. All Active-

HDL tools output their messages to Console.

3)Compilation:

Compilation is a process of analysis of a source file. Analyzed design units

contained within the file are placed into the working library in a format

understandable for the simulator. In Active-HDL, a source file can be one of the

following:

VHDL file (.vhd)

Verilog file (.v)

EDIF net list file (.EDIF)

State diagram file (.asf)

Block diagram file (.bde)

In the case of a block or state diagram file, the compiler analyzes the intermediate

VHDL, Verilog, or EDIF file containing HDL code (or net list) generated from the

diagram.A net list is a set of statements that specifies the elements of a circuit (for

example, transistors or gates) and their interconnection.

Active-HDL provides three compilers, respectively for VHDL, Verilog, and

EDIF. When you choose a menu command or toolbar button for compilation, Active-

HDL automatically employs the compiler appropriate for the type of the source file

being compiled.

4)Simulation:



The purpose of simulation is to verify that the circuit works as desired.

The Active-HDL simulator provides two simulation engines.

Event-Driven Simulation

Cycle-Based Simulation

The simulator supports hybrid simulation – some portions of a design can be

simulated in the event-driven kernel while the others in the cycle-based kernel.

Cycle-based simulation is significantly faster than event-driven.

3. ARCHITECTURE OF THE PROJECT:



Serial communication system has been widely used data communications and

control system because of less hardware resources, anti-jamming ability, and easy to

implement future. A FPGA based high performance serial communication system

interface module which includes full functions of UART16550 is designed and

optimized based communication and the protocol working principle in the paper.

Various technologies are adopted during the design and optimization procedure,

such as the three always block coding style, EDA optimization, circuit optimization,

and so on. The frequency of the optimized design is up to 166MHz, and the power


PtoS

CRC

DLC

Mu

x

StoP

CRC

DLC

DM

ux

Por

t S

ele

ctor

SP0

SP1

SP2

SP3

SP4

SP5

SP6

SP7

TXSMC

RXSMC

Baud Gen

OFDET

TXFIFO

RXFIFO

Registers

HO

ST

Con

tro

ller

Inte

rfac

e

BaudReg

Command

PortSelect

Status

Transmit Data Processing block

Receive Data Processing block

Programmable Multi Port Serial communication interface controller


consumption is reduced to 0.147W by 63.9%. The test data at typical baud-rate of

115200 and the analyzed result by using Mat lab are presented. The test results

indicate that the optimized design can be communicated correctly and steadily.

As the key processing equipment of comprehensive task processing system, Mission

management computer needs to crosslink with various equipments, and the types of

communication interface are different. A serial communication interface based on

FPGA (Field Programmable Gate Array) has been designed in this paper, used for

data communication with other equipment. It guarantees the realization of the serial

communication function under the condition of without any increasing in hardware

resources. It accords with hardware equipment standardization principle. The design

is adopted the Xilinx Company's Virtex-4 series FPGA chip, simulation results indicate

that it satisfies protocol requirements.

4.MODULES:

4.1 FIFO: (FIRST-IN-FIRST-OUT)



FIFO is an acronym for First In, First Out, an abstraction in ways of

organizing and manipulation of data relative to time and prioritization. This

expression describes the principle of a queue processing technique or servicing

conflicting demands by ordering process by first-come, first-served (FCFS) behaviour:

what comes in first is handled first, what comes in next waits until the first is

finished, etc. Thus it is analogous to the behaviour of persons standing in line, where

the persons leave the queue in the order they arrive, or waiting one's turn at a traffic

control signal. In essence, both are specific cases of a more generalized list (which

could be accessed anywhere). The difference is not in the list (data), but in the rules

for accessing the content. One sub-type adds to one end, and takes off from the

other, its opposite takes and puts things only on one end. A priority queue is a

variation on the queue which does not qualify for the name FIFO, because it is not

accurately descriptive of that data structure's behavior. Queuing theory

encompasses the more general concept of queue, as well as interactions between

strict-FIFO queues. FIFOs are used commonly in electronic circuits for buffering and

flow control which is from hardware to software. In hardware form a FIFO primarily

consists of a set of read and write pointers, storage and control logic. Storage may

be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of non-

trivial size a dual-port SRAM is usually used where one port is used for writing and

the other is used for reading. A synchronous FIFO is a FIFO where the same clock is

used for both reading and writing. An asynchronous FIFO uses different clocks for

reading and writing. Asynchronous FIFOs introduce metastability issues. A common

implementation of an asynchronous FIFO uses a Gray code (or any unit distance

code) for the read and write pointers to ensure reliable flag generation. One further

note concerning flag generation is that one must necessarily use pointer arithmetic

to generate flags for asynchronous FIFO implementations. Conversely, one may use

either a "leaky bucket" approach or pointer arithmetic to generate flags in

synchronous FIFO implementations. Examples of FIFO status flags include: full,

empty, almost full, almost empty, etc...The first known FIFO implemented in


http://en.wikipedia.org/wiki/Queue_(data_structure)

http://en.wikipedia.org/wiki/Acronym


electronics was done by Peter Alfke in 1969 at Fairchild Semiconductors. Peter Alfke

is now a Director at Xilinx.

FIFO full/empty

In hardware FIFO is used for synchronization purposes. It is often implemented as

a circular queue, and thus has two pointers:

1. Read Pointer/Read Address Register

2. Write Pointer/Write Address Register

FIFO Empty:

When read address register reaches to write address register, the FIFO triggers the

Empty signal.

FIFO FULL:

When write address register reaches to read address register, the FIFO triggers the

FULL signal.

4.2 DATA MULTIPLEXER AND DEMULTIPLEXER:

In electronics a multiplexer or mux (occasionally the terms muldex or

muldem are also found for a combination multiplexer-demultiplexer) is a device that

performs multiplexing it selects one of many analog or digital input signals and

forwards the selected input into a single line. A multiplexer of 2n inputs has n select

lines, which are used to select which input line to send to the output. An electronic

multiplexer makes it possible for several signals to share one device or resource, for

example one A/D converter or one communication line, instead of having one device

per input signal.

On the other end, a demultiplexer (or demux) is a device taking a single

input signal and selecting one of many data-output-lines, which is connected to the

single input. A multiplexer is often used with a complementary demultiplexer on the


http://en.wikipedia.org/wiki/Circular_queue


receiving end.An electronic multiplexer can be considered as a multiple-input, single-

output switch, and a demultiplexer as a single-input, multiple-output switch. The

schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel

side containing the input pins and the short parallel side containing the output pin.

The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent

switch on the right. The sel wire connects the desired input to the output. In

telecommunications, a multiplexer is a device that combines several input

information signals into one output signal, which carries several

communicationchannels, by means of some multiplex technique. A demultiplexer is

in this context a device taking a single input signal that carries many channels and

separates those over multiple output signals.

Fig(a)

Schematic of a 2-to-1 Multiplexer. It can be equated to a controlled switch.

Fig(b)

Schematic of a 1-to-2 Demultiplexer. Like a multiplexer, it can be equated to a

controlled switch.In telecommunications and signal processing, an analog time

division multiplexer (TDM) may take several samples of separate analogue signals


http://en.wikipedia.org/wiki/File:Multiplexer2.png

http://en.wikipedia.org/wiki/File:Demultiplexer.png


and combine them into one pulse amplitude modulated (PAM) wide-band analogue

signal. Alternatively, a digital TDM multiplexer may combine a limited number of

constant bit rate digital data streams into one data stream of a higher data rate, by

forming data frames consisting of one timeslot per channel.In telecommunications,

computer networks and digital video, a statistical multiplexer may combine several

variable bit rate data streams into one constant bandwidth signal, for example by

means of packet mode communication. An inverse multiplexer may utilize several

communication channels for transferring one signal.

4.3 PARALLEL TO SERIAL CONVERTER:

A parallel-to-serial data conversion circuit includes a control circuit

receiving a load signal, a clock signal and high-order 4 bits of a parallel data of 8-bit

PCM code excluding the MSB bit, for generating a first control signal and a second

control signal, a 6-bit shift register receiving the first control signal, the second

control signal, low-order 4 bits of the parallel data, a store signal and the clock

signal, and a selector for selecting the output of the shift register on the basis of the

MSB bit and the first control signal. A serial input is provided to cascade two E446

devices for 8 bit conversion applications. Note that the serial output data clocks off

of the negative input clock transition.



• 1.5 Gb/s Typical Data Rate Capability

• Differential Clock and Serial Inputs

• VBB Output for Single-ended Input Applications

• Asynchronous Data Synchronization

• Mode Select to Expand to 8 Bits

• Internal 75kΩ Input Pulldown Resistors

• Extended 100E VEE Range of -4.2V to -5.46V

The SYNC input will asynchronously reset the internal clock circuitry. This pin

allows the user to reset the internal clock conversion unit and thus select the start of

the conversion process. The MODE input is used to select the conversion mode of the

device. With the MODE input LOW, or open, the device will function as a 4-bit

converter. When the mode input is driven HIGH the internal load clock will change on

every eighth clock cycle thus allowing for an 8-bit conversion scheme using two

E446’s. When cascaded in an 8-bit conversion scheme the devices will not operate at

the 1.3Gb/s data rate of a single device. Refer to the applications section of this data

sheet for more information on cascading the E446. For lower data rate applications a

VBB reference voltage is supplied for single-ended inputs. When operating at clock

rates above 500MHz differential input signals are recommended. For single-ended

inputs the VBB pin is tied to the inverting differential input and bypassed via a

0.01µF capacitor. The VBB provides the switching reference for the input differential

amplifier.



Fig: Parallel to serial converter

4.3.1 Application:

The MC10E/100E446 is an integrated 4:1 parallel to serial converter. The chip

is designed to work with the E445 device to provide both transmission and receiving

of a high speed serial data path. The E446 can convert 4 bits of data into a 1.3Gb/s

NRZ data stream. The device features a SYNC input which allows the user to reset

the internal clock circuitry and restart the conversion sequence (see timing diagram

A). The E446 features a differential serial input and internal divide by 8 circuitry to

facilitate the cascading of two devices to build a 8:1 multiplexer. Figure 1 illustrates

the architecture for a 8:1 multiplexer using two E446’s; the timing diagram for this

configuration can be found on the following page. Notice the serial outputs (SOUT) of

the lower order converter feed the serial inputs of the the higher order device. This

feed through of the serial inputs bounds the upper end of the frequency of operation.



The clock to serial output propagation delay plus the setup time of the serial input

pins must fit into a single clock period for the cascade architecture to function

properly. Using the worst case values for these two parameters from the data sheet,

TPD CLK to SOUT = 1480ps and tS for SIN = 200ps, yields a minimum period of

1280ps or a clock frequency of 780MHz. The clock frequency is somewhat lower than

that of a single converter, to increase this frequency some games can be played with

the clock input of the higher order E446. By delaying the clock feeding E446A

relative to the clock of E446B the frequency of operation can be increased.

4.4 SERIAL-TO-PARALLEL CONVERTER: 4.4.1 Shift register:

In digital circuits, a shift register is a cascade of flip flops, sharing the same

clock, which has the output of anyone but the last flip-flop connected to the "data"

input of the next one in the chain, resulting in a circuit that shifts by one position the

one-dimensional "bit array" stored in it, shifting in the data present at its input and

shifting out the last bit in the array, when enabled to do so by a transition of the

clock input. More generally, a shift register may be multi dimensional, such that its

"data in" input and stage outputs are themselves bit arrays: this is implemented

simply by running several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are

often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out

(PISO). There are also types that have both serial and parallel input and types with

serial and parallel output. There are also bi-directional shift registers which allow

shifting in both directions: L→R or R→L. The serial input and last output of a shift

register can also be connected together to create a circular shift register.

Serial-in, parallel-out (SIPO):

This configuration allows conversion from serial to parallel format.

Data is input serially, as described in the SISO section above. Once the data has



been input, it may be either read off at each output simultaneously, or it can be

shifted out and replaced.

Parallel-in, serial-out (PISO):

This configuration has the data input on lines D1 through D4 in parallel format. To

write the data to the register, the Write/Shift control line must be held LOW. To shift

the data, the W/S control line is brought HIGH and the registers are clocked. The

arrangement now acts as a PISO shift register, with D1 as the Data Input. However,

as long as the number of clock cycles is not more than the length of the data-string,

the Data Output, Q, will be the parallel data read off in order.

fig:4-Bit PISO Shift Register


http://en.wikipedia.org/wiki/File:4-Bit_SIPO_Shift_Register.png

http://en.wikipedia.org/wiki/File:4-Bit_PISO_Shift_Register.png


4.4.2 Uses:

One of the most common uses of a shift register is to convert between serial

and parallel interfaces. This is useful as many circuits work on groups of bits in

parallel, but serial interfaces are simpler to construct. Shift registers can be used as

simple delay circuits. Several bi-directional shift registers could also be connected in

parallel for a hardware implementation of a stack. Shift registers can be used also as

a pulse extender.

4.5 CYCLIC REDUNDANCY CHECK:

A cyclic redundancy check (CRC) or polynomial code checksum is an insecure

hash function designed to detect accidental changes to raw computer data, and is

commonly used in digital networks and storage devices such as hard disk drives. A

CRC-enabled device calculates a short, fixed-length binary sequence, known as the

CRC code or just CRC, for each block of data and sends or stores them both together.

When a block is read or received the device repeats the calculation; if the

new CRC does not match the one calculated earlier, then the block contains a data

error and the device may take corrective action such as rereading or requesting the

block be sent again, otherwise the data is assumed to be error free (though, with

some small probability, it may contain undetected errors; this is the fundamental

nature of error-checking. CRCs are so called because the check (data verification)

code is a redundancy (it adds zero information to the message) and the algorithm is

based on cyclic codes. The term CRC may refer to the check code or to the function

that calculates it, which accepts data streams of any length as input but always

outputs a fixed-length code.

4.5.1 CRCs and data integrity:

CRCs are specifically designed to protect against common types of errors on

communication channels, where they can provide quick and reasonable assurance of

the integrity of messages delivered. However, they are not suitable for protecting

against intentional alteration of data. Firstly, as there is no authentication, an



attacker can edit a message and recalculate the CRC without the substitution being

detected.

This is even the case when the CRC is encrypted—this was one of the design

flaws of the WEP protocol. Secondly, the linear properties of CRC codes allow an

attacker even to keep the CRC unchanged while modifying parts of the message this

also makes calculating the CRC adjustment for small changes more efficient.Both

CRCs and cryptographic hash functions by themselves do not protect against

intentional modification of data. Any application that requires protection against

such attacks must use cryptographic authentication mechanisms, such as message

authentication codes.

4.5.2 Designing CRC polynomials:

The selection of generator polynomial is the most important part of implementing

the CRC algorithm. The polynomial must be chosen to maximize the error detecting

capabilities while minimizing overall collision probabilities. The most important

attribute of the polynomial is its length (largest degree(exponent) +1 of any one

term in the polynomial), because of its direct influence of the length of the computed

checksum. The design of the CRC polynomial depends on the maximum total length

of the block to be protected (data + CRC bits), the desired error protection features,

and the type resources for implementing the CRC as well as the desired

performance. A common misconception is that the "best" CRC polynomials are

derived from either an irreducible polynomial or an irreducible polynomial times the

factor (1 + x), which adds to the code the ability to detect all errors affecting an odd

number of bits. In reality, all the factors described above should enter in the selection

of the polynomial.

The advantage of choosing a primitive polynomial as the generator for a

CRC code is that the resulting code has maximal total block length; in here if r is the

degree of the primitive generator polynomial then the maximal total blocklength is

equal to 2r − 1, and the associated code is able to detect any single bit or double

errors. If instead, we used as generator polynomial g(x) = p(x)(1 + x), where p(x) is a



primitive polynomial of degree r − 1, then the maximal total block length would be

equal to 2r − 1 − 1 but the code would be able to detect single, double, and triple

errors. A polynomial g(x) that admits other factorizations may be chosen then so as

to balance the maximal total blocklength with a desired error detection power. A

powerful class of such polynomials, which subsumes the two examples described

above, is that of BCH codes. Regardless of the reducibility properties of a generator

polynomial of degree r, assuming that it includes the "+1" term, such error detection

code will be able to detect all error patterns that are confined to a window of r

contiguous bits. These patterns are called "error bursts".

4.6 DATA LENGTH COUNTER:

In digital logic and computing, a counter is a device which stores (and

sometimes displays) the number of times a particular event or process has occurred,

often in relationship to a clock signal. In practice, there are two types of counters.

Up counters, which increase (increment) in value

Down counters, which decrease (decrement) in value

Each is useful for different applications. Usually, counter circuits are digital in nature,

and count in natural binary. Many types of counter circuit are available as digital

building blocks, for example a number of chips in the 4000 series implement

different counters. A simple way of implementing the logic for each bit of an

ascending counter (which is what is depicted in the image to the right) is for each bit

to toggle when all of the less significant bits are at a logic high state. For example,

bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic

high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high.



4.7 STATE MACHINE CONTROLLER:

In this section we will take a look at the implementation of finite state

machines from broader perspective. We will investigate how a finite state machine

can be implemented, and take a look at a framework that can facilitate multiple

FSMs in a simulated real-time environment. A single FSM on its own is of little use;

therefore we need to investigate implementations from a broader view to

understand where a single FSM plugs in. We will analyze portions of the finite state

machine framework from the computer game Quake, in attempt to understand how

to make use of the technique in a real world application.

One possible way to implement finite state machines is to have a controller of

some type which acts as switch box. When the thread of execution swings around to

execute code of the FSM, it is pointed at the controller which evaluates or

determines the current state, usually through the use of a switch (case) statement or

if-then-else statement.

Once the current state is determined, the code for that state is executed,

actions performed and possibly state transitions for the next time the FSM is

executed. The controller may be a simple switch statement evaluating an integer,

but an implementation may see the controller performing some pre-processing of

inputs and triggering of state transitions before-hand.

Fig: state machine controller

A FSM implementation where the controller acts as a switch box to determine which

state to run. The red line denotes the thread of execution. The implementation that

the programmers at id Software have chosen could almost be considered to have



Object-Oriented (OO) feel (though the implementation is not OO). As mentioned

before, the game world is populated by entities, and as such a generic entity

structure is used as their basis. Each entity in the collection of entities is provided

with some execution time by calling its "think" function. The entity is executed by

the game code in what could be described as a polymorphic manner. Entities have a

common interface (because they are all the same data structure), and this interface

consists of function pointers which are used to execute entity specific and entity

non-specific code as either action outputs or input events for the FSM.An example;

most entities are affected by damage. Damage can be inflicted by many things like a

rocket projectile for example. When a damage trigger is transmitted to another

entity, its pain function pointer is called, thus triggering a state transition of the

effected entity into possibly a death or attack state. Key point: The damage inflicted

is an input to the FSM, which may act as a trigger for a state transition. In essence

the same switch-box technique described in is used, where the entities base data

structure provides function pointers which act as the "switches". When an entity is

given a chance to execute its state, its "think" function pointer is called. If previously

a damage input was received, the entity may have had a state transition into its "die

state". When the thread of execution runs, the objects "die state" code is then run

(via a polymorphic call of the entities think function), removing the entity instance

from the game world.

Transmitter :



Receiver:



5. RESULT DISCUSSION:



5.1 FIFO:

Block diagram

Input-Output Ports Description:

s.no Port name Mode Size Port description

1 Data Input [7:0] Input data port

2 Fifoena Input 1 bit Input enable signal for fifo

3 Fiford Input 1 bit Input fifo read enable signal

4 Fifowr Input 1 bit Input fifo write signal

5 Rdclk Input 1 bit System read clock

6 Rst Input 1 bit Input asynchronous reset

7 Wrclk Input 1 bit Input write clock signal

8 Datao Output [7:0] Output data

9 Empty Output 1 bit Output empty signal

10 Full Output 1 bit Output full signal

Wave forms:



5.2 MUX:

Input-Output Ports:

s.no Port

name

Mode Size Port description

1 CrcL Input [7:0] Crc input signal

2 CrcM Input [7:0] Crc input signal

3 Data Input [7:0] Data signal

4 Datasel Input [2:0] Input data signal

5 Dataval Input [7:0] Input value signal

6 Muxdata Input [7:0] Mux data output

WAVE FORM:




BLOCK DIAGRAM

Input-Output Ports:


1 Dataval Input [7:0] Data values

2 Clk Input 1 bit On board clock signal

3 Datacntena Input 1 bit Data count enable signal

4 Rst Input 1 bit On board reset signal

5 Datacntovr Output 1 bit Data out signal

WAVE FORM:



5.4 Tx CRC:

Input-Output Ports:

S.no Port name Mode Size Port description

1 Clk Input 1 bit On board clock

2 Crcena Input 1 bit Crc enable signal

3 Din Input 1 bit Input data signal


6 Crcl Output [7:0] Lower 8 bit crc

7 Crcm Output [7:0] Most significant 8 bit

WAVEFORM:



4.5 TXSMC:

BLOCK DIAGRAM

Input-Output Ports:



2 Datacntovr Input 1 bit Data count over signal


4 Serovr Input 1 bit Serial over signal

5 Txena Input 1 bit Transmitte enable signal

6 Datasel Output [2:0] Output data select signal

7 Crcena Output 1 bit Output crc enable signal

8 Datacntena Output 1 bit Output data count enable

signal

9 Fiford Output 1 bit Fifo resd signal

10 Serena Output 1 bit Serial enable signal



11 Serld Output 1 bit Serial load signal

WAVEFORM:

5.6 OSDETECTOR:



BLOCK DIAGRAM

Input-Output Ports:



2 Rst Input 1 bit Asynchronous reset signal

3 Rxd Input 1 bit Receive data strerms

4 Sopdetena Input 1 bit Sopdet enable signal

5 Sopdetovr Output 1 bit Sopdet over signal

WAVE FORM:

5.7 PARALLEL to SERIAL:


ClkRstlk

SIPOEna

Sin SIPO

Pout[7:0]



S.N

0

Port

Name Mod

e

Size

Port

Description

1 Clk In Entity function

synchronized for Rising

edge of the Clk

2 Rst In Clk

3 SIPOEna In Entity function


edge of the Clk

4 Sin In Entity function


edge of the Clk

5 Pout Out [7:0] Entity function


edge of the Clk



WAVE FORM:

5.8 SERIAL to PARALLEL:


s.no Port

name

Mode Size Port description

1 Deserena Input 1 bit Derserial enable

2 Deserrd Input 1bit Deserial enable

3 Rst Input 1 bit Reset signal

4 Rxclk Input 1 bit Receive clock signal

5 Rxd Input 1 bit Receive clock



6 Data Output [7:0] Data output signal

7 De serovr Output 1 bit De serial over signal

WAVE FORM:


BLOCK DIAGRAM





1 Dataval Input [7:0] Data values

2 Clk Input 1 bit On board clock signal

3 Datacntena Input 1 bit Data count enable signal


5 Datacntovr Output 1 bit Data out signal

WAVE FORM:

5.10 CRC:

BLOCK DIAGRAM


S.no Port name Mode Size Port description




2 Crcena Input 1 bit Crc enable signal

3 Din Input 1 bit Input data signal


6 Crcl Output [7:0] Lower 8 bit crc

7 Crcm Output [7:0] Most significant 8 bit

WAVE FORM:

5.11 DEMUX:

BLOCK DIAGRAM



1 Data Input [7:0] Data values

2 Dsel Input [2:0] Data select signal



3 Addr Output [7:0] Output data

address

4 Crclsb Output [7:0] Crclsb signal

5 Crcmsb Output [7:0] Crcmsb signal

6 Datao Output [7:0] Data output signal

7 Dlbyte Output [7:0] Output databyte

WAVE FORM:

TRANSMITTER:



Wave Forms:



Synthesis Report:

Device utilization summary:

---------------------------

Selected Device : 3s100etq144-5

Number of Slices: 0 out of 960 0%

Number of IOs: 33

Number of bonded IOBs: 2 out of 108 1%

Total memory usage is 148728 kilobytes

RTL Schematic View:



RECEIVER:



Wave Forms:

Synthesis Report:



Device utilization summary:

---------------------------

Selected Device : 3s100etq144-5

Number of Slices: 20 out of 960 2%

Number of Slice Flip Flops: 21 out of 1920 1%

Number of 4 input LUTs: 26 out of 1920 1%

Number used as logic: 10

Number used as RAMs: 16

Number of IOs: 19

Number of bonded IOBs: 15 out of 108 13%

Number of GCLKs: 2 out of 24 8%

Minimum period: 2.568ns (Maximum Frequency: 389.431MHz)

Minimum input arrival time before clock: 3.521ns

Maximum output required time after clock: 4.040ns

Total memory usage is 149752 kilobytes.

RTL Schematic View:



6. ADVANTAGES AND DISADVANTAGES:

6.1 Advantages:

Serial links offer significant flexibility over parallel buses in terms of the

media used.



Serial communication can span longer distances than parallel

communication.

Set-up is very fast, so well suited for applications where messages are

generated at irregular intervals, for example data entry from the keyboard.

Point-to-point links have greater efficiency than shared buses like PCI.

It is less expensive.

6.2 Disadvantage:

Disadvantage is that the transmission lines are idle during the time

intervals between transmitting characters.

The disadvantage includes the possible in accuracy. Because when a

receiver goes out of Synchronization, loosing tracks of where individual characters

begin and end. Correction of errors takes additional time

6.3 Applications:

Security in public data network (hardware and software) applications.

Electronic transaction and audio/video communication applications.

Secured data storage systems

Modems

7. CONCLUSION:

7.1 Analysis:

Serial communication is the process of sending data one bit at a time,

sequentially, over a communication channel or computer bus. This is in contrast

to parallel communication, where several bits are sent as a whole, on a link with

several parallel channels. Serial computer buses are becoming more common even


http://en.wikipedia.org/wiki/Parallel_communication

http://en.wikipedia.org/wiki/Bit

http://en.wikipedia.org/wiki/Data


at shorter distances, as improved signal integrity and transmission speeds in newer

serial technologies have begun to outweigh the parallel bus's advantage of

simplicity. No need for serializer and deserializer, or SerDes and to outstrip its

disadvantages like clock skew, interconnect density. .

Conclusion:

Serial communication between components is a vital part to reducing size of

circuitry, and is used in almost every gadget in today’s world. Knowing how to take

advantage of bus systems such as SPI. It can be implemented with low cost.

7.1 FUTURE SCOPE:

Serial communication system has been widely used in data communications

and control system because of less hardware resources, anti-jamming ability, and

easy to implement features. A FPGA-based high performance Serial communication

system interface module is designed Various technologies can be adopted for the

design and optimization procedure, such as the three always block coding style, EDA

optimization, circuit optimization, and so on. The frequency of the optimized design

is up to 166MHz, and for the low power consumptions.

Baud rates of the connected ports can be programmed according to the

requirement of the user.

For specific applications which need reception of the transmitted data in

controller, orthogonal sequence detector may be used for correcting errors.

Receiver acknowledgement for erroneous transmission can be provided.

8. REFERENCES:

IEEE Base Paper:

WEBSITES:

BOOKS:

References:

International Technology Roadmap for Semiconductors 2005 [Online].

Available: www.itrs.net/Links/2005itrs/Home2005.htm


http://en.wikipedia.org/wiki/Clock_skew

http://en.wikipedia.org/wiki/SerDes

http://en.wikipedia.org/wiki/Signal_integrity


W. J. Dally and B. Towles, “Route packets, not wires: On-chip

interconnection

Networks,” in DAC, 2001, pp. 684–689.

A. Lines, “Asynchronous interconnect for synchronous SoC design,”

MICRO, vol. 24, no. 1, pp. 32–41, 2004.

G. De Micheli and L. Benini, Networks on Chip. San Mateo, CA:

Morgan Kaufmann, 2006.

H. O. Johansson, J. Yuan, and C. Svensson, “A 4 Gsamples/s line-receiver

in 0.8 um CMOS,” VLSI Circuits, pp. 116–117, 1996.

[9] C. Svensson and J. Yuan, “High speed CMOS chip to chip

communication

Circuit,” in Proc. Proc. IEEE Int. Symp. Circuits Systems (ISCAS), 1991, pp.

2228–2231.


Multiport Serial Communication Interface Controller

Engineering

Transcript of Multiport Serial Communication Interface Controller