Multicore Challenge Presentation - Test and Verification Solutions

© Imagination Technologies Bristol Multicore June 2013 p1 www.imgtec.com

Tony King-Smith

EVP Marketing

Portable Native Performance: The Rise of Heterogeneous Platforms

© Imagination Technologies Bristol Multicore June 2013 p2

Agenda

What is really driving heterogeneous platforms

What are heterogeneous processors?

What does this mean for SoCs?

What does this mean for apps – portability with performance

Some related trends

Conclusions


We design IP for heterogeneous platforms Our IP portfolio stretches beyond silicon to the cloud and M2M

Each processor is a class leader Together they deliver class-leading solutions

PowerVR GPU Graphics processor

PowerVR VPU Video & Vision processo)

EnsigmaRPU

Radio comms processor

MIPS CPU General

processor

Unified Memory

Other devices & the

Internet


Consumers are everything

Products are only successful if consumers buy them

And generally they do if it

Makes their lives easier

Makes them happier

Makes them healthier

Saves the planet

But

Expectations are changing

Cultures are different

and value things differently

You need apps that always work,

and use all the processor resources available to them


On-chip “accelerators” have come a long way And have become new category of processors

Wi-Fi

CPU

Video Decoder

Graphics

Bus

One architecture (ISA) does not fit all applications

The “off-load” engines have become processors as important as the CPU

BT

TV

Sensor

Video Encoder

Bus

Bu

s


Heterogeneous SoCs is the future Processors for each key function optimises programmability, area, power

Designing SoCs relies on optimising the capabilities of each processor (performance), while minimising memory bandwidth, area and power

GPU

VPU

RPU

CPU Unified Memory

Other devices & the

Internet


Each processor’s architecture highly tuned Optimised blend of programmable, configurable and fixed function hardware

MIPS CPU

Programmable Software Execution

Fixed Cache

Ensigma RPU

Programmable Control

Configurable Filters

Configurable Coding Engines

Programmable Modulation

PowerVR VPU

Programmable Control

Configurable Motion

Configurable Quantisation &

Transform

Configurable Post Processing

PowerVR GPU

Programmable Shaders

Configurable Data Engines

Programmable Shaders Programmable

Shaders Programmable Shaders

Fixed Cache

Programmable uKernel


Each processor designed to be the best

CPU: control Serial compute for complex sequential heuristics

System level management and control

Supports multiple operating systems

GPU: graphics Both graphics & parallel compute

Maximum processing on-chip

High memory latency tolerance

VPU: video Multi-standard video decode and encode

Configurable hardware for ultra-low power and size

RPU: radio Programmable + configurable engines for highest performance

Complex dataflow at high data rates

Multi-standard: Wi-Fi; TV/radio; M2M sensors

Class-leading functions that join together to create optimal system solutions

CPU

GPU

RPU

VPU


Innovation in GPUs: ray tracing The behaviour of light is not yet inherently supported in conventional graphics

• Current graphics use

simplistic techniques to

emulate basic reflections,

shadows etc

• Never looks realistic; each

scene “pre-baked”

• Ray tracing models light

inherently, so every scene

delivers rich image realism

New API’s (new OpenRL™, Brazil™ renderer) to abstract new processor capabilities


What does this mean for hardware platforms?

Developing a new PCB for each new chip limits time to volume

But as performance increases, so do memory, power etc

Software BSP bring-up must be quick

We don’t have time to rebuild everything!

For high performance, choice of memory will be critical

For lower performance, power and cost dominate

app & comms compatibility will be key

Bus fabric and SoC infrastructure needs standardising

HSA is a key activity for that – Imagination is a founder;

Bristol University one of the earliest academic partners

Fast upgrades are the key for volume; importance of SoC infrastructure is rising


Platforms will vary massively Low end to high end, silicon node, application domain, and much more

PowerVR GPU

PowerVR VPU

Ensigma RPU

MIPS CPU

Unified Memory

Flow Cloud



PowerVR GPU

PowerVR VPU

Ensigma RPU

MIPS CPU

Unified Memory

Flow Cloud



PowerVR VPU

Ensigma RPU

MIPS CPU

Unified Memory

Flow Cloud


GPU performance: faster yet lowest power M

ob

ile

GP

U p

roc

es

sin

g p

ow

er

(lo

g)

Time

12GFLOPs

2013

128GFLOPs

2014 2015

256GFLOPs

24GFLOPs

48GFLOPs

Widening GPU

performance envelope – but power

budget remains static!

GPU processing increasing >2x per year – for both low and high-end Envelope of GPU performance widening ~2x per year between low and high-end


SoC memory bandwidth: another enabler

Time

25 Gbyte/s

50 Gbyte/s

Today

0

10

20

30

40

50

Gbyte/s

Wide I/O memory


What does this mean for apps?

Identifying what resources are available

Identifying what performance is available

Apps focus increasingly on their “discovery” phase:

What processors do I have?

What performance capabilities does each processor have?

What resources will each processor allow me to use?

What else is going on in my system that might affect me?

How can the system tell me when my environment has changed?

How do I relate their capabilities to what I want to do?

Portability does not mean loss of performance

App discovery phase should maximise performance, not dumb it down to the lowest common denominator


Portability of apps

Applications must be able to run on any platform

Otherwise the market for a developer is too small

Android NDK has created an unacceptable break in portability

Google know and recognise this

Dependence on GPU ISAs is low

The APIs were well designed

Performance at higher levels of abstraction is better understood

Abstracting away from the CPU ISA is essential

Portable APIs: OpenCL; Renderscript/Filterscript,OpenGL/OpenGL ES

Portable binaries, e.g. LLVM BitCode

High level runtimes: Java/Dalvik

Legacy binary translation, e.g. MIPS MagicCode, QEMU

Abstraction, abstraction, abstraction…



PowerVR VPU

Ensigma RPU

MIPS CPU

PowerVR GPU

Unified Memory

Flow Cloud

Application

Co

mm

s

Co

mp

ute

?

AP

I

LLV

M/J

ava

/Co

mp

ute

AP

Is

Gra

ph

ics

A

PI

Op

en

Ma

x +

Co

de

c A

PIs

GP

U

Co

mp

ute

A

PI

Discover, optimise,

scale, adapt!


Conclusions

Apps are becoming adaptive and scalable

Opportunities to lead this global trend here in the UK

Be realistic

Silicon progress is far from over – but advanced SoCs are expensive!

SoC upgrade rate speeding up due to volume & competition

Breadth of SoC capabilities is broadening

Utilise key skills here in the UK

Compilers & heterogeneous tools;processor architecture & design

Be active in API and other standards development

We are the world leaders in processor architectures

The UK must lead the world in heterogeneous platforms & heterogeneous app technologies!

Platforms and apps must change

© Imagination Technologies Bristol Multicore June 2013 p20 www.imgtec.com

Tony King-Smith

EVP Marketing

Thank You – Questions?

Multicore Challenge Presentation - Test and Verification Solutions

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