Multiband / Multimode Radio - faculty.ece.vt.edu · • Currently in Phase III (Integration) –...

NIJ Communications Technologies Principal Investigator MeetingA PROGRAM OF THE NATIONAL INSTITUTE OF JUSTICE

Multiband/Multimode RadioEllingson – Oct 24, 2007

Multiband / Multimode Radio

Steve Ellingson ([email protected])

S.M. Shajedul Hasan ([email protected])

October 24, 2007



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Selected VoiceChannels

Selected Data Channel

Combine Many Radios into One*At least 13 bands relevant to Public Safety

x Many channels per band = A lot of radios!(*Above figure is just a functional description.)

Frequency Bands:VHF (138-174 MHz)‏220 MHzUHF (406-512 MHz)‏700 MHz P.S.800 MHz P.S.Cellular & PCS2.4 GHz ISM4.9 GHz P.S.

Law Enforcement Mission

Developing a prototype radio capable of operation over a large range of frequency bands now in use for public safety applications.

Goal: Seamless Interoperability



I.M. M

UX

138-174

220-222

406-512

764-862

4.9 GHz Down

UHF

VHF

4.9 GHz Up

~ 10 dB

(BPF)

LO

ShortWhip

Ext.Ant.

~ 30 dB

A/D

A/D

D/A

D/A

FPGA

µP e

mul

atio

n

EmbeddedAntennas

800 MHz / PCS Cellular Chipset

2.4 GHz WLAN Cellular Chipset

CO

DEC

Oth

er I/

O

Touc

hscr

een

Knob

s

PTT

SPKRMIC

Technology Overview

Motorola Direct Conv. RFIC100-2500 MHz

RF Multiplexer

Baseband ADC/DAC

SoPC/FPGA-centric approach; Currently100% Verilog HDL



Timeline for Activities• Formal Deliverables

• Phase I (Concept) Technical Report – Done• Phase II (Design) Technical Report – Done• Phase IV (Evaluation) Technical Report – July 2008 • Final Report – Oct 2008

• Currently in Phase III (Integration) – scheduled to end Oct 2008 but extended to accommodate Motorola RFIC and SoPC mods.

• Demonstrations• Various lab demos available now• Extensive laboratory testing planned as part of Phase IV• Field demos planned ~ June 2008



Criminal Justice Payoff• Interoperability will be enhanced by the availability of radios

capable of accessing any frequency band and mode used by first responders – seamlessly and without prior coordination (i.e., without repeaters).

• Working with several innovations which have applications transcending the original goals – e.g., direct conversion and SoPC– which may significantly improve cost / power / reconfigurability

• Wide dissemination of research results, especially to vendors:• Collaboration with Motorola on direct conversion RFIC• Discussions underway with Tyco (M/A-COM)• Open project – easy access to reports, design data, etc.

through project web site



I.M. M

UX

138-174

220-222

406-512

764-862

4.9 GHz Down

UHF

VHF

4.9 GHz Up

~ 10 dB

(BPF)

LO

ShortWhip

Ext.Ant.

~ 30 dB

A/D

A/D

D/A

D/A

FPGA

µP e

mul

atio

n

EmbeddedAntennas

800 MHz / PCS Cellular Chipset

2.4 GHz WLAN Cellular Chipset

CO

DEC

Oth

er I/

O

Touc

hscr

een

Knob

s

PTT

SPKRMIC

Design Concept

EXT. ANT.

BATT / DC-DC

RF

MULTIBAND PIFAFOR 2-6 GHz BANDS(FLUSH WITH CASE) ‏

BASEBAND / DSP

< 1 GHz ANT.

Current concept for project end-state radio



Current State of Prototype

RF Mux& R/T

RFIC4DemoBoard

ADC/DACBoard

Altera EP2S60 FPGA Board

PowerTI AIC32CODEC(under board)

138-174 MHz 220-222 MHz406-512 MHz764-900 MHz

Motorola SDR RFIC Ver. 4

4 MSPS basebandADC/DAC

Analog FM mode

SoPC approach:No µP; Instead completely implemented in FPGA

31.25 MHz ref DDS via FPGA

7 x 20 in. as shown hereEthernet



Direct Conversion?• Almost always unacceptable!

• I/Q Imbalance is a problem – sideband rejection• 2nd order nonlinearity is a problem• 1/f noise in band is a problem• Initial BPF needs to tune, or a filter bank is required



RF CMOS Changes Everything• Idea: Implement RFICs using same inexpensive process used for

dense, high-speed digital circuitry

• Traditional objection: CMOS is fiendishly difficult to use for RF due to process variations and inaccurate design models

• These problems can now be largely mitigated by:• Implementing design to be robust to variations• Exploiting availability of nearby logic to enable radio to tweak chip

as needed

• Dense (90 nm!): Can put many copies of an RF path on a single chip

• RF and baseband can go on the same chip, if you are very careful about mitigating digital noise in the RF sections



Motorola Direct Conversion RFIC

SPI

FREF

FEXT

RXBB_IP

RX1P

LLOP_B

TX1P

AOC_TXRF

GND

VDD1_2

VDD2_5

1 GHz ReferencePLL / VCO

1 GHzReference

1 GHzReference

AGC_RX

Tx FEEDBACKQuIET

++

++

++

SUB

Chop Clock

RECEIVEQuIET

1 GHzReference

DYNAMIC MATCHING

Chop Clock

DYNAMIC MATCHING

Chop Clock

TxQuIET

QuIETDM

1 GHzReference

RX_QGEN_LOQuadGen

QuadGen

QuadGen

TX_QGEN_FWD_ LO

TX_QGEN_FB_LO

RxMixers

TxMixersTx FBMixers

Chop

Chop

1.2 V

1.2 V

1.2 V

2.5 V

2.5 V

RF_FB_INP

CP_PLL

TANKN

Multiple pads

Multiple pads

Mux

Mux

To Rx B B I

To Rx BB Q

Tx ReverseBB I Channel

Tx ReverseBB Q Channel

SPIControlledFuntions

RX1N

RX2PRX2N

RX3PRX3N

RX4PRX4N

RX5PRX5N

TX1N

TX2PTX2N

TX3PTX3N

LLON_B

RF_FB_INN

TX_BB_QNTX_BB_QP

TX_BB_INTX_BB_IP

RESETMISOMOSI

SPI_CLKCSEL

RXBB_IN

RXBB_QPRXBB_QN

TANKP

Multiple pads

DM

DM

DM

5 RX Paths (1 output) 90 nm CMOS 3 TX Paths (1 input) No inductorsRX F ~ 5 dB QFP-128RX IIP2 ~ +60 dB < 400 mA @ 2.5V (RX+TX)‏RX IIP3 ~ – 5 dBm

Tunes 100 - 2500 MHz (continuous) ‏BW: 6.25 kHz – 10 MHz (many steps)‏Sideband Rejection ~ 40 dB, up to 60 dBInternal DDSs for LO generationExcellent mitigation of 1/f noise

Specs (Verified by VT in Independent Testing)‏

G. Cafaro et al., “A 100 MHz – 2.5 GHz Direct Conversion CMOSTransceiver for SDR Applications,” 2007 IEEE RFIC Symp., June 2007.



VT Implementation of Motorola SDR RFIC (V4)

40 mA (RX) + 40-90 mA (TX) + 80 mA/DDS @ 9V< 25 cm2 to implement on a 4-layer PCBAbout $100 in parts to implement, excluding PCB.

Technical Memo 22



Advantages of RFIC-Based Direct Conversion in this Project

• Scalable – Same architecture works for reduced or increased number of simultaneous channels/bands (just add/remove chips)

• Reduced power (extended battery life) – lower power/channel and unneeded RFICs (or RFIC sections) can be shut down.

• Increased number of channels can be monitored simultaneously, even across bands: Scanner-like capability, “White space” seeker(s) for frequency-agile cognitive radio

• Con: Optimization requires calibration and tweaking of many parameters (over a low-bandwidth serial port)



RF Front End• Meeting selectivity specs is one of the big

challenges once a direct conversion approach is chosen

• Simple 4 channel RF multiplexer intended to demonstrate concept

• 4 bands: 138-174 MHz, 220-222 MHz, 406-512 MHz, 764-1000 MHz

• Independent non-blocking R/T switch per band, coordinated with baseband

• Working now to jointly optimize linearity, selectivity, and sensitivity; will be tailored to antenna/chassis implementation

~ 50 cm2 as shown here



ADC / DAC• ADC: Analog Devices AD9248

2 Ch (i.e., I/Q), 14b, 20 MSPSSample clock sourced by system FPGA; variable over 1-20 MSPS

• DAC: Analog Devices AD97612 Ch (i.e., I/Q), 10b, 40 MSPSSynchronous with ADCMay upgrade to at least 12 bits

130 mA @ 9V, running 4 MSPS< 50 cm2 to implement on a 4-layer PCBADC ~ $21 (1k), DAC ~ $10 (1k)



SDR Baseband Processing• Virtually all modern radios are “software defined” in the sense that

some functionality is implemented in software on a µP

• Modern notion of SDR emphasizes reconfigurability – achieving this in software requires large memory spaces, cache, etc.

• For an all-mode radio, SDR is useful primarily in that it may simplify the design by reducing the number of independent basebandsections, but it is not clear that it is better in any other sense (cost, size, weight, power). Truth here is somewhat application-specific.

• µP-based SDR makes sense if implementation in procedural languages or conformance to an existing architecture/paradigm isrequired. Not clear this makes sense for a “new start” radio which is not so contrained, however.



Alternative SoPC Strategy• SoPC – “System on a Programmable Chip”. Typically refers to use of a

single Field Programmable Gate Array (FPGA) to perform all computing in an embedded system

• Key idea: Dedicated microprocessors are overkill for many applications, whereas FPGAs are often essential for other reasons and can take on many functions traditionally assigned to microprocessors through “soft core” implementation.

• In an SoPC system, compute functions are assigned either to FPGA LEs(via HDL-derived firmware) or software (via a soft-core processor), and the previously awkward partition between FPGA firmware and microprocessor software is eliminated.

• Now relatively simple to implement “soft core” processing on an FPGA (Altera: Nios II, Xilinx: MicroBlaze)



SoPC in Contrast to SDR• In some sense, an SoPC-based radio is the opposite of SDR – we want to

implement as much as we can in efficient firmware (HDL), and strip the (inefficient) µP down to the minimum acceptable functionality

• In another sense, SoPC subsumes SDR, since we are talking about implementing software-defined functionality on firmware-defined processors!

• Potential advantages include cost, power, speed -- because only the functionality which is needed is implemented

• Explicit concurrency (huge advantage over traditional SDR)



Our Baseband Strategy• Prototype currently implemented on an Altera Stratix II FPGA (EP2S60).

Massive overkill (60k LEs) but board familiar and readily available. Implemented directly via FPGA:• Analog FM waveform• From 100 MHz timebase, synthesis of 4 MHz ADC/DAC clocks and

31.25 MHz DDS for RFIC ref. freq • Interfaces to codec and ethernet chips

• In our project, not clear we will ever need to implement a soft-coreprocessor: We are currently 100% Verilog HDL.

• Project end-state processor will probably be an Altera Cyclone III FPGA; 25k LEs, about $50 (chip), power variable and hard to predict.



Challenges Remaining• Front End (Multiplexing/Duplexing). Now: Quite difficult to

design suitable multiplexers. MEMS may eventually make this easy.

• Antennas: Vehicles: Not a show-stopper, but existing solutions are ugly (“porcupine effect”). Handhelds: Need attention. We are at the physical limits; bending metal into new shapes will not help.

• Power amplifiers: Not scary; broadband (100-1000 MHz) ~1W solutions exist. However order of magnitude improvement desirable

• Power supply noise in integrated configuration –Potentially limiting sensitivity

• New operational/security/training issues to manage



Outreach• Technical Reports – available via web site

• 23 since project start• Many include detailed design information, CAD files, etc.

• Public Presentations & Papers• MissionCritical Communications Article, March 2007• IWCE 2006, 2007• SDR Forum 2006

• Liaison with Industry• Motorola Research Labs – RFIC collaboration• Tyco (M/A-COM) – Discussions



Thanks!

Web Sites:http://www.ece.vt.edu/swe/chamrad/http://www.ece.vt.edu/swe/http://wireless.vt.edu/

U.S. Dept. of JusticeNational Institute of Justice

Grant 2005-IJ-CX-K018

Acknowledgements:Motorola: G. Cafaro, B. Stengle, N. CorrealMahmud Harun (Ph.D. Student)

Capstone Demo:Wireless @ Virginia Tech Annual Symposium and Summer SchoolJune 4-6, 2008

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