Multi-level wordline driver for robust SRAM designin nano-scale CMOS technology

Farshad Moradi a,n, Georgios Panagopoulos b, Georgios Karakonstantis c,Hooman Farkhani a,d, Dag T. Wisland e, Jens K. Madsen a, Hamid Mahmoodi f, Kaushik Roy b

a Integrated Circuits and Electronics Laboratory, Department of Engineering, Aarhus University, Denmarkb Nanoelectronic Research Laboratory, Purdue University, USAc Telecommunication Circuits Laboratory, École Polytechnique Fédérale de Lausanne, Switzerlandd Ferdowsi University of Mashhad, Irane Nanoelectronics group, University of Oslo, Norwayf Nano-Electronics and Computing Research Laboratory, San Francisco State University, USA

a r t i c l e i n f o

Article history:Received 20 November 2012Received in revised form23 September 2013Accepted 30 September 2013Available online 29 October 2013

Keywords:SRAMWordline driverLow-powerLeakage-powerDigital circuits

a b s t r a c t

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and writestability. The proposed wordline driver generates a shaped pulse during the read mode and a boostedwordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a shortperiod of time, whereas for the remaining access time, the wordline voltage is reduced to save the powerconsumption of the cell. This shaped wordline pulse results in improved read noise margin without anydegradation in access time for small wordline load. The improvement is explained by examining thedynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time(depending on the size of boosting capacitance), wordline voltage becomes negative and charges up tozero after a specific time that results in a lower leakage current compared to conventional SRAM. Theproposed technique results in at least 2� improvement in read noise margin while it improves writemargin by 3� for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reducedby 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The mainadvantage of the proposed wordline driver is the improvement of dynamic noise margin with less than2.5% penalty in area. TSMC 65 nm technology models are used for simulations.

& 2013 Elsevier Ltd. All rights reserved.

1. Introduction

Aggressive transistor scaling has led to increased process varia-tions leading to major design challenges in the nanometer regime.Process variability stems from systematic effects such as variations incritical dimensions (transistor width and length) [1], oxide thickness[2], and truly random effects like the dopant fluctuations (RDF) [3].Current design methodology hardly distinguishes systematic varia-tions from truly random ones. For digital design (logic and memory),the worst-case corners typically capture 3s variations. To satisfy theworst-case performance requirements, often a large penalty is paidin power and area.

In such cases, satisfying the power budget often requires a trade-offin performance. Memory design presents an extreme example ofcorner-based design. To satisfy the functionality of several tens ofmillions of SRAM cells, the designer has to capture even 5s and 7sstandard deviations of parameter variations. This is becoming increas-ingly challenging to satisfy, and may present a problem for continuedscaling of memory density.

Hence, to achieve the highest possible packing density withhigh parametric yield in CMOS and SOI technologies, designers usea combination of multi-layered ad-hoc and heuristics techniques.They include device sizing, supply and threshold voltage selection,SRAM column height and sense-amplifier optimization, redundantcolumns, and error correction techniques.

Power reduction has also become one of the most challengingdesign issues in every application domain. For SRAM designs, powerreduction has been obtained by lowering the supply voltage [4] or byusing high-Vth (HVT) devices [5,6]. Stability issues in SRAM cells havebeen aggravated using complex peripheral designs such as supplygating [7,8]. Lower voltages and smaller devices cause a significantdegradation in SRAM cell data stability especially in scaled CMOS

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Microelectronics Journal

0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved.http://dx.doi.org/10.1016/j.mejo.2013.09.009

n Corresponding author. Tel.: þ45 418 933 44.E-mail addresses: moradi@cs.au.dk (F. Moradi),

gpanagop@purdue.edu (G. Panagopoulos),georgios.karakonstantis@epfl.ch (G. Karakonstantis), hfa@iha.dk (H. Farkhani),dagwis@ifi.uio.no (D.T. Wisland), jkm@iha.dk (J.K. Madsen),mahmoodi@sfsu.edu (H. Mahmoodi), Kaushik@purdue.edu (K. Roy).

Microelectronics Journal 45 (2014) 23–34

technologies. Another challenge is that SRAM cells are the mainsources of leakage due to the large number of devices in memorybanks that needs to be considered [9]. To improve data stability ofSRAM cells, various techniques have been proposed in literature suchas read/write separation [10,11] (e.g. 8T-SRAM cell), boosted wordline[12,13] (to improve voltage scaling), dynamic wordline driver [14],negative bit-line (to improve writability) [15–18], programmablewordline driver [19], compound device and circuit techniques [20],and adaptive dynamic wordline driver [21]. However, read and writestabilities are both important. For instance, improving the readstability degrades the read access time. Hence, the development ofa memory technology with higher data stability and lower leakagepower with negligible degradation in access time is desirable.Furthermore, a memory with the possibility of improved write andread margin simultaneously can help engineers significantly.

In this paper, we propose a technique with the followingfeatures: (a) boosted voltage level to VDDþα where α is a designparameter and depends on the size of transistors and boostingcapacitance of wordline driver circuit. (b) Fixed voltage at VDD for ashort period of time from the start of the read access and thenlowered voltage than VDD/2 for the rest of read mode. Thisimproves the dynamic noise margin and robustness againstprocess variation that results in a lower read failure rate.(c) Negative level of wordline voltage during standby mode toreduce bitline leakage (partially negative wordline).

The remainder of paper is organized as follows: in Section 2 amotivation example is given. In Section 3 we briefly describe someexisting wordline driver techniques. In Section 4 we present theproposed multi-level wordline driver technique (MLWD) andexplain how read and write stability improvement is achievedbased on dynamic analysis. Simulation results are presented inSection 5. In Section 6, we apply the proposed technique to otherSRAM cell topologies. Finally, in Section 7 the conclusionsare drawn.

2. Wordline drivers for SRAM arrays

In literature, different topologies have been proposed toimprove read or write static noise margins (SNM) [4–20]. Howevermost of these techniques consider only one aspect of the existingchallenge.

In this section, we consider the most recently proposedtechniques that are relevant to wordline driving technique. In thissection, we briefly present some of them.

Fig. 1 shows the schematic of Level-programmable WordlineDriver (LPWD) proposed by Hirabayashi et al. in Ref. [19]. Theyproposed a wordline compensation technique combined with adual power supply scheme. As shown in Fig. 1, there are two globalpower supplies named VSM and VDD. The authors reported that VSMis 200 mV higher than VDD based on their measurements on a512 Kb SRAM block. This technique uses an adaptive wordline (WL)

level-control generated from dual power supplies in theWL driver. InLPWD, the WL pull-up PMOS transistors are split in a binary manner.Even though the cell failure is reduced by 1000� , the usage of largePMOS transistors leads to large area penalty. Besides, this techniqueuses dual power supplies.

A replica access transistor (RAT) is proposed in Ref. [15] thatself-calibrates the WL voltage suppression under dynamic controlvoltage and frequency scaling. The schematic of the design isshown in Fig. 2. The technique reduces the cell current by 83%compared to conventional assist circuits [15]. Furthermore, theminimum operating voltage in the worst case was improved by170 mV, confirming a high immunity against process and tem-perature variations with less than 10% area overhead. However,since the WL voltage is lowered, there is a concern aboutdegradation of the operating speed. Furthermore, this techniqueuses resistances as voltage-divider (implemented by Nþ poly-Si)that imposes area penalty.

In Refs. [15,16], the write capability is enhanced by negative writebiasing without any reduction in the cell current. Furthermore, readcapability is enhanced by cell current boosting. This technique uses anegative voltage booster to boost the selected column's VSS to anegative voltage to enhance the access current. However, in thistechnique the cells are 8T-SRAM cells with separate read and writeoperations. Therefore, these techniques suffer from large area andpower penalties compared to 6T-SRAM array.

In Ref. [17], capacitive coupling is used to generate a transientnegative voltage at the low-going bit-line during Write operationwithout using any on-chip or off-chip negative voltage source. In thistechnique, bitline voltage is lowered to a negative level using acapacitance. Then the bitline voltage gets back to ground after acertain time depending on the design. This technique shows 1000�improvement in Write failures with no impact on the read stability.

In Ref. [22], the authors proposed a Level-programmableWordline Driver for Single Supply (LPWD-SS) design, shown inFig. 3. This design uses a fixed negative voltage using boostingcapacitance that gives better writability to the SRAM cell. Thedesign shows better rise time in WL compared to LPWD design.This design uses 32 nm high-k metal-gate CMOS technology.

In this paper, we propose a technique that improves read andwrite SNM, with comparable read access time compared tostandard SRAM-cell, while showing lower power consumptioncompared to conventional wordline drivers. In addition, it giveslower leakage current due to the negative WL voltage during atimeslot of the standby mode. The main advantage of the proposedwordline driver is the merging of read-assist and write-assistdesigns into one single technique. Furthermore, our design showsnegligible area overhead compared to other techniques such as the

Fig. 1. Read assist circuitry [19]. Fig. 2. RAT scheme [15].

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–3424

RAT and LPWD-SS schemes due to lower capacitance withoutadding any resistance.

3. Motivation example

Process variations lead to fluctuations in transistor parameterssuch as threshold voltage, width and length variations that canultimately lead to memory failures. In general, parametric failures[3] can occur during (a) read: flipping the stored data, (b) write:the data is not stored correctly within the required time and(c) hold: flipping of cell data with the application of a lower supplyvoltage. Fig. 4a and b shows examples of read and write failuresassuming constant wordline (CWL) voltage equal to supply vol-tage. One method to reduce the effect of variability in these casesis the upsizing of the SRAM cell that helps to make the cell morestable. However, since the area of the SRAM cell is crucial for thedensity of the memory array, it is important to consider othertechniques to improve the stability. A promising technique is tochange the shape of the applied wordline voltage. Such technique

is preferable since the stability of the cell can be improved withoutaltering the topology or size of each bit-cell.

In order to explain the effect of changing the wordline voltage,let us consider use of some examples. To begin with, we consider ascenario in which the shape of the applied wordline voltage is notfixed. Fig. 4a, c and b, d show the SRAM function during read andwrite modes respectively. After applying the shaped wordline, asillustrated in Fig. 4b and d, applying such a shaped wordlinevoltage can improve both read and write. Interestingly, we observethat applying such a shaped wordline voltage helps the cell tomaintain the stored data during read as shown in Fig. 4b while inFig. 4a it is shown that the stored data is flipped. During read, byshaping the wordline voltage, data is not flipped and during writeit helps the cell to read the data.

For instance, let us assume a memory with conventional world-line (Fig. 4c) and a cell that cannot write data correctly due toweakened access transistors influenced by parametric variations.Interestingly, by applying the shaped wordline voltage (boosted toa higher level) depicted in Fig. 4d to the same cell (assumed that failsunder a conventional fixed wordline voltage) strengthens the accesstransistor and allows data to be stored correctly.

The above examples show that appropriate wordline shapescan significantly improve the cell stability that results in anincrease in memory yield which is necessary in nanoscale tech-nologies. Motivated by the above examples, in this paper wepropose a scheme that generates an appropriate wordline shapedepending on the mode of operation and we examined itscharacteristics and its effects on a memory array. The details ofthe proposed circuit are discussed in the next section.

4. Proposed wordline driver

In this section we describe the proposed wordline driver indetail and explain how it achieves to improve the read and writeSNM, while maintaining a read access time similar to standardSRAM-cell, and reducing power consumption as opposed toconventional wordline drivers.Fig. 3. LPWD-SS [22].

Fig. 4. The effects of wordline shaping on SRAM cell stability for read ((a) and (b)) and write ((c) and (d)).

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–34 25

The schematic of the proposed wordline driver is shown inFig. 5. The Multi-Level Wordline Driver circuit (MLWD) consists ofthree parts: (1) the delay element that determines the duration ofa read operation and the time during which WL has a negativevoltage level, (2) the pulse generator circuitry that produces aspecial shaped pulse and (3) the boosting capacitance that changesthe voltage level of the MLWD output depending on the opera-tional mode. In order to describe how the MLWD scheme works letus consider its operation at three different modes: (a) hold orstandby mode (b) read mode and (c) write mode.

(a) During hold, the WL of the SRAM is connected to a negativevoltage for a short period of time (�6τinv, where τinv is thedelay of a single inverter) and thereafter WL voltage becomeszero. Note that the main reason behind the applying a negativeWL voltage is the reduction of leakage current through theaccess transistors. Of course the actual improvement in leak-age power consumption depends on various factors such asthe transistor size, the boosting capacitance, and the delay ofthe inverter-chain circuitry as we will show in Section 4.

(b) During write, the MLWD circuit generates a VDDþα voltagewith α40. Higher the WL voltage level (wordline boostingtechnique) is, the better the writability becomes since the gatevoltage of the access transistor becomes higher making it as aconcequence stronger (as we also show in one of the examplesin Section 2). Note that α is a design parameter and it isdetermined by the boosting capacitance, while the rise time ofWL is tuned by the size of the transmission-gate in the MLWDcircuit. Note that larger transmission-gate transistors (TGT)lead to lower rise time of the MLWD output during write orread modes, thus there is no need for dual supply voltages ornegative ground (Vss). A challenging issue in boosted wor-dlines during read is the half select issue in which a cell in anunselected column is disturbed because of the increasedvoltage that is applied on WL for turning-on the pass gatetransistors for writing the required cells. Finding the righttrade-off between the write margin and disturb marginbecomes especially challenging at low VDD (i.e. 0.5 V) [23–28].

(c) During read mode, for a short period of time from thebeginning of the access of the cell (ffi6τinv s, 120–150 ps),the MLWD output voltage is raised to VDD7δ where δ is a verysmall value (up to150 mV), that depends on the transistordimensions of the MLWD circuit, the boosting capacitance, andthe wordline capacitance. For the remaining WL pulse period,

the MLWD output is set at a lower voltage under VDD/2. Byapplying such a voltage, the read noise margin improvessignificantly while the read access time is marginally affected.The negligible degradation on read access time is attributed tothe primary value of wordline voltage that is VDD7δ, where δis a value up to 100 mV depending on the wordline loadcapacitance. Thus the degradation in access current is negli-gible for small loads. However, for larger load capacitances (e.g. 50 fF) the primary level of wordline voltage is lower thanVDD leading to a reduced access time. For instance for an SRAMarray of 4 Kb (256 row and 32 columns), access time isdegraded by 7.5% compared to CWD.

Let us next explain the operation of the proposed MLWD circuitat the three different modes and highlight the enhancements overthe conventional circuit described above:

During write, when WLin is at “1”, for a time equal to 3τinv(delay of three inverters) node A remains at “1”, while node B is“0”. In this case, transistors P1, P2 and N1 turn on charging theboosting capacitance to VDD. After this time (�3τinv), node Abecomes zero while node B remains at zero turning off transistorN1. After 6τinv from the beginning of operation, node B becomesone. Therefore, there is no path between node MLWD and WLin. Atthis point, capacitance Cboost discharges to “0” after a timeconstant equal to RN2Cboost.

During read, for a time equals 6τinv from the beginning of readcycle, the WL voltage level is high depending on the wordlinecapacitance. However, after 6τinv delay, transistors N3 and NR turnon and try to pull down the MLWD node to ground. At this time,TG1 (i.e. N1 and P1) is off and TG2 (i.e. N2 and P2) is still ON (N2turns on, while the drain and the source of N2 are connected to thesame voltage). Under this condition, the final voltage value onCboost in the read cycle is reached after one time constant that isdefined by the on-resistance of the stacked N3 and NR transistors(Rstack) together with RN1. Output voltage is defined as follows:

Vboost ¼ �1þ Rstack

RN2þK1e

� tðRstack jjRN2 ÞCboost þK2e

� tRN2Cboost ð1Þ

where, Rstack and RN2 are the equivalent resistances for stackedN3–NR and N2 devices, respectively. As it can be seen from Eq. 1,since Rstack4RN2, the final value of Vboost is larger than zero.Upsizing the stacked NMOS transistors lead to Vboost to approachzero. In this case, the size of the boosting capacitance determinesthe discharging time of Cboost to its final value.

During hold mode, when WLin becomes zero, for a delay equalsto 3τinv, TG1 is OFF while N2 is still on. In this case, during the 3τinvtime, voltage at node MLWD goes towards a negative value equalto �1 V with a time constant of τ¼RN2Cboost. Note that thenegative voltage is determined by the boosting capacitance Cboostand RN2. After an extra elapsed time equal to 3τinv (total delay of6τinv from the beginning of standby mode), the Cboost is charged upto zero with a time constant determined by RP2||RN1. This affectsthe leakage power of the whole row, but its influence in the totalleakage is very small. On the other hand, the lower WL voltageduring read reduces the total leakage power significantly as it isalso shown in next sections. MLWD scheme results in 2% leakagecurrent reduction for an SRAM array.

In our simulations we assumed that 25% of wordline pulsewidth is enough to sense a voltage difference of 50–70 mVbetween two bitlines depending on the sense amplifier design.However, the number of columns and rows define the sensingtime. Increased number of rows leads to larger bitline capacitance(CBL) results in a longer sensing delay (access time). After theshortened wordline pulse (that is enough to sense the bitlinedifference), the level of wordline voltage is lowered to lower thefailure rate at presence of process variation.

Fig. 5. MLWD circuit topology.

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–3426

There is a possibility to make WL pulse wide enough to enablesensing the voltage at a cost of lower dynamic noise margin. Let uslook at an example, at Fast–Fast corner (Fast NMOS and FastPMOS) discharging the BL to the desired level is fast enough to besensed during 6τinv. This is attributed to a 150 μA current throughaccess transistor that is enough to discharge the bitline to a levelto be sensed by sense-amplifier. However, for Slow–Fast corner(Slow NMOS and Fast PMOS) this time is not enough to dischargeBL to the desired level because of lower current, 80 μA, throughaccess transistors. Therefore, the rest of discharging the bitlineshappens at lower level of WL with a lower access current. It isclear that access time is degraded with an improved noise margin.In case, the pulse width is designed in a way to work at all corners(widening wordline pulse width), lowered level of wordlinevoltage is not necessary. However, by assuming different processvariation effects and reliability issues such as NBTI, PBTI, and HCIand their effects on threshold voltage, the rest of wordline pulse(lowered level of wordline voltage) can help to prevent any failure.This is the main difference between proposed wordline driver andpulsed-wordline driver.

5. Simulation results

To show the efficacy of the proposed MLWD technique, weperformed HSPICE simulations on a 6T SRAM cell and 128 Kbmemory array using the proposed MLWD wordline driver schemeas well as a conventional wordline in TSMC 65 nm processtechnology.

Before going into the details of the results we would like tomention that for comparison we used the technique that isreferred as conventional wordline driver (CWD)[26]. However inRef. [26], a custom layout for NAND is performed while in thispaper a standard layout for NAND is assumed. CWD is implemen-ted using a NAND gate that takes inputs read/write signal and therow decoder's output. In addition, note that the conventionalwordline driver (CWD) design requires large buffers to drive therows in an SRAM array. As we mentioned in the previous section,the proposed MLWD circuit generates three different voltageshapes one for each operation mode. The output of MLWD duringwrite is a boosted wordline voltage to a VDDþα value. During hold,the wordline voltage becomes negative reducing the overallleakage current while in read mode the wordline voltage reachesto VDD7δ. In the following paragraphs we consider the differentoperational modes of the SRAM cell, and later on we discuss aboutpower savings as well as the behavior of the proposed MLWD inpresence of process variations.

5.1. Read mode

Voltage waveforms showing the operation of a 6T-SRAM cellusing the proposed MLWD are illustrated in Fig. 6 for a smallwordline capacitance. As it can be seen the shaped wordlinevoltage during read enables SRAM to read the data through senseamplifiers. In Fig. 7, we plot the results for BLs with conventionalwordline driver (CWD) and MLWD. As it is shown, the bitlinedischarging time is faster in case of MLWD than CWD. Note that,for small loads, due to the boosted WL provided by MLWD (evenvery small), the BL is discharged faster than the conventional caseand hence shows a better read access time. The main reason offaster discharge of BL voltage is due to the small bump in thewordline voltage during read for MLWD design. Furthermore,since the MLWD has a delay and its value changes slower thanCWD counterpart. During this time, access transistor connected toBLB has no effect on the cell for a longer time that results in astrong OFF-state for corresponding transistor connected to BLB.

For CWD design, BLB starts to discharge a little from the beginningof read cycle and results in a slower discharge in BL.

For lower supply voltages, due to the delay of MLWD designthat is attributed to the transmission-gate transistors drivability,read access time is degrades by few percent compared to CWD.This is attributed to lowered level of wordline voltage duringthe read.

The value of Cboost¼1 fF is chosen for aforementioned results.However, for an SRAM array, a larger boosting capacitance isrequired to keep the level of WL voltage close to VDD at the primarytime of reading (for few ps). For larger WL capacitance the level ofWL voltage is lowered results in a degraded access time. Forinstance, for a 64 column SRAM array, the wordline capacitance islarger than 100 fF that requires a Cboost at least larger than 50 fF toachieve similar waveform in Fig. 7. For our simulations, a 10 fFboosting capacitance is used that results in lowered level of WLvoltage and leads to an improvement in SNM while degradation inaccess time. The results for wordline voltage level during read areincluded in Section 5.4.

Lowering the WL voltage level is a way to make the accesstransistors “weaker” and thus to improve read SNM. However, thistechnique degrades the access time due to weaker access transis-tors. Fig. 8 shows a family of butterfly curves and the correspond-ing read SNM of a conventional wordline driver for differentsupply voltages. It is known that lowering the supply voltage,SNM degrades significantly. Fig. 9 explains how read SNM andaccess time are affected by lowering the WL voltage. It is apparentthat lowering the WL voltage to �0.6 V, read access time degradesby 40% while the read SNM improves by 2� . By applying the

Fig. 6. MLWL outputs during read.

Fig. 7. Simulation results for MLWD and CWD (Cboost¼1 fF, single SRAM cell).

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–34 27

MLWD technique, read access time does not get degraded whilethe read SNM improves by more than two times. Table 1 shows theresults for read SNM using MLWD and CWD topologies. Interest-ingly, MLWD design improves read SNM by at least 2.14�compared to the CWD scheme.

In case that the sense amplifier senses a voltage difference(ΔVBL) between the bitlines, the WL voltage is lowered to suppressthe access current for the remaining read cycle (ffi90% of TWL,where TWL is the WL period). The sense amplifier (SA) used in ourSRAM array design that can sense ΔVBL less than 100 mV [29].Fig. 10 shows the access current flowing through the pass-transistors of the SRAM cell during read for MLWD and CWD. Itis evident that our MLWD design can provide more than 50%current savings during read compared to CWD technique. As aresult, MLWD reduces the power consumed by the SRAM cellduring read. This is attributed to decreased current flows throughthe access transistor (IAX). However, since the access time isdegraded for larger CWL (wordline capacitance), the power savingis decreased.

The power saving of proposed MLWD can be considered fromtwo aspects. In case we measure read power consumption whenone of the bitlines is fully discharged in which the proposedMLWD results in a high power saving. But when the difference

between bitlines' voltages is considered, the saved power is onlyfor the rest of cells in the row with WLs enabled.

During read, as mentioned, the level of wordline voltage islowered to a voltage lower than VDD/2 instead of ground (pulsed-wordline driver). The main advantage of proposed design com-pared to pulsed wordline driver is its better robustness againstprocess variations that results in a much lower read failure. Toclarify this concept, let us bring an example. Assume that, due tothe process variation, the shortened pulse is not adequate to readthe data. In this case, for MLWD, the level of WL has been loweredto VDD/2 instead of “0”, giving this benefit to the circuit todischarge the bitline with a slower pace. This results in a lowerfailure rate in the proposed circuit.

5.2. Write mode

Fig. 11 shows the MLWD operation during write and holdmode. As it can be seen, during write, the wordline voltage isboosted to VDDþα, where α is the boosted value that was discussedin Section 4.

Writability of MLWD improves due to boosted WL voltage. InFig. 12, we compare the write delay for different wordline drivertechniques. Since, the MLWD design shows less rise in voltage atlower supply voltages, write delay is less affected by using thistechnique. At lower supply voltages, the negative BL technique(e.g. LPWD [7] or LPWD-SS [12]) results in a smaller delay comparedto MLWD technique. Fig. 13 shows the waveforms of the MLWDoutput during write under different supply voltages. We observethat the write speed degrades which takes place due to the delayadded by the MLWD circuitry. By upsizing the transistors in theMLWD (transmission-gate transistors), this problem can be miti-gated for lower supply voltages. However, we have to mention thatfor higher supply voltages, the MLWD exhibits lower write delay

Fig. 9. Lowering the WL voltage effect on SNM and read access time.

Table 1SNM comparison for MLWD and CWD.

VDD (V) Read SNM (mV) (CWD) Read SNM (mV) (MLWD) Improvement

1 140.8 305.9 2.17�0.9 132.6 284.2 2.14�0.8 119.1 254.9 2.14�0.7 101.0 219.4 2.17�0.6 82 180.5 2.2�0.5 63.6 141.3 2.22�

Fig. 10. Current saving of MLWD during read.

Fig. 8. Read-SNM for 6T-SRAM at different operating voltages.

Fig. 11. Output of MLWD during the write.

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–3428

compared to the negative BL methods (LPWD and LPWD-SS). Theproposed design also includes read-assist circuitry compared to theLPWD-SS design to improve read margin. Instead of shutting off theinput wordline signal to ground (during read), we lowered thewordline voltage to a level less than VDD that helps to lower theleakage through access transistors.

The results of write margin for the negative bitline design(LPWD) compared to CWD and MLWD schemes are depicted inFig. 14. By lowering the supply voltages lower than 0.6 V, usingCWD for SRAM cells is not possible. However, both LPWD andMLWD are able to help SRAM array to work with a reasonable WMdown to 0.25 V and 0.3 V respectively.

These simulation results show that the LPWD design providesbetter write margin compared to the MLWD technique. However,the MLWD achieves 2.75� improvement inwrite margin comparedto the conventional design. Furthermore, our design shows betterwrite delay at higher supply voltages compared to the LPWD design.

By utilizing the MLWD design, Vmin is reduced from 166 mV to96 mV at VDD¼1 V (CBL¼400 fF, CWL¼50 fF) while the final Vmin forMLWD is reduced to 31 mV. All in all, Vmin is improved by at least43% compared to CWD.

5.3. Power consumption

In Fig. 15, we have plotted IAX (Access transistor current) duringread and write modes for MLWD and CWD schemes. To calculatepower savings, we performed HSPICE transient analysis for read,write, and hold modes. The results show that MLWD designreduces the total power of SRAM cell during read and standbymode while write power consumption is increased. Table 2 sum-marizes the results for power consumption of a 4 Kb SRAM array.

Due to boosted wordline voltage during write, the MLWDscheme shows 37% increase in the IAX current compared to CWD.However, as we mentioned, read current is reduced by more than50% compared to using CWD technique. It is known that thenumber of read accesses is three times larger than the number ofwrite accesses based on test-benchmarks [30]. This suggests thatthe total savings will improve for common applications, whereread is more prevalent. However, read power consumption canbe measured in two ways. In case, only the bitline voltage differenceis considered, the power saving is different from when the bitline isallowed to be discharged to a lower level (e.g. fully discharged).

To clarify the power saving of the proposed MLWD technique,we simulate a 4 Kb SRAM array and measure the average powerconsumption using CWD and MLWD. Simulation results show390 μW and 395,33 μW read power consumption at VWL¼0.9 Vand VWL¼1.0 V, respectively. Write power consumption is calcu-lated as 395 μWat VWL¼1.2 V while 392 μW at VWL¼1.0 V. Leakagepower consumption for this array is calculated as 55.92 μW and50.14 μW for CWD and MLWD, respectively. These results do notconsider the precharge power consumption and the power con-sumption of read and write circuitry. During read, by consideringthe required ΔVBL to be sensed by sense-amplifier, there is no powersaving during read. This is attributed to this fact that, the time

Fig. 13. Level of MLWD at different operation voltages.

Fig. 14. Write margin comparison.

Fig. 15. Current saving during write and read at VDD¼1 V.

Table 2Power and area for proposed MLWD (4 Kb SRAM array).

Capacity 256�32

Read power at VDD¼1.0 V 395.33μWWrite power at VDD¼1.0 V 392 μWRead power at VDD¼0.9 V 390 μWWrite power at VDD¼1.2 V 395 μWLeakage power for CWD 55.92 μWLeakage power for CWD 50.14 μWCell area 0.9282 μm2

Read power at VDD¼1 V (ΔBL) 375 μW

Fig. 12. Write delay for MLWD compared to CWD and LPWD.

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–34 29

required to discharge the bitline adequately increases for loweredwordline voltage level. As a result, the total read power consump-tion is not changed. The total power saving of the proposed designdepends on the number of read and writes for a specific time. Thehigher the number of the writes, the lower power saving will beachieved. However, the lower number of writes improves the powerconsumption of the SRAM array.

5.4. Process and temperature variations

In case of process variations (higher Vth value for accesstransistors) by applying the CWD design, SRAM fails to read thedata from storage nodes during the specified pulse width. How-ever, for the proposed MLWD design, if the specified pulse is notwide enough to read the data, the SRAM still have the chance ofreading the data at a slower rate when wordline voltage is at VDD/2level. As a result, our design is less prone to process variations andmore robust.

In order to study the proposed scheme under variations weperformed Monte-Carlo simulations for both read and write modesand the results are summarized in Figs. 16 and 17, respectively. Incase of read mode, we observe that the effect of process variations ismore prominent under the lowest WL voltage. As it can be seen, μand s are 0.53 V and 17.4 mV, respectively. Furthermore, we observethat the mean of α during write is 0.11 V and equal to the designedvalue. Therefore, our circuit demonstrates robust behavior in pre-sence of transistor process variations and mismatches due to smallvariations of α value in presence of process variations.

Considering the effect of temperature on WL voltage duringread and write cycles is crucially important. The effect of raisedtemperature on WL voltage for proposed MLWD technique is

shown in Fig. 18a and b. As it is shown in Fig. 18a, by increasingthe temperature the value of read wordline voltage does notchange significantly (0.97-0.96) while the lowered VWL valuechanges from 0.44 V to 0.39 V. However, by raising the tempera-ture, wordline voltage during write changes from 1.196 to 1.15 V.As a result, the change in read noise margin versus temperature isnegligible while the change in write margin is more due to thelowered VWL. The effect of raised temperature on access time isnegligible too.

To explore the effect of process variations (VWL change ) on readnoise margin, write margin, and access time, we sweep VWL duringread and write. Fig. 19 illustrates the degradation trend in readnoise margin due to the lowered VWL at different VWL. As it can beseen, in case the wordline voltage level changes from 1 V to 0.9 V,the read noise margin is degraded by 24%. However, as shown inFig. 18a, temperature does not change the VWL value significantly.Therefore, read noise margin change versus temperature is negli-gible. However, write margin is more affected by temperature asillustrated in Fig. 19. The lowered boosted VWL from 1.2 to 1.1(equivalent to VWL versus temperature) lead to a write margindegradation by 22%.

5.5. Dynamic noise margin comparison

When we perform static noise margin (SNM) we suppose thatthe word-line pulse width is infinite. Even though this assumptiondoes not represent the reality, it provides an easy, fast andcomprehensive way to measure the stability of a SRAM cell. Hence,in order to capture the real behavior of the SRAM cell, dynamicstability analysis and dynamic noise margin (DNM) [30,31] isneeded to perform. In our case, the use of DNM for SRAM cellanalysis is necessary in our proposed technique the wordline is not

Fig. 16. Process variations effect on WL voltage during the read.

Fig. 17. Effect of process variations on WL voltage level during write.

Fig. 18. (a) Read wordline voltage and (b) write wordline voltage versustemperature.

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–3430

constant. Thus, our goal is to capture the transient states which arenot considered during DC static analysis.

Before we present our results, it will be more convenient tointroduce some terms that help explain our results appropriately.A more detailed discussion can be found in Ref. [32]. By runningtransient analysis using a numerical simulator like SPICE we getthe voltage waveforms (VL, VR and WL) with respect to time as theyare shown in Fig. 20a and c. Their trace in the VL–VR plane (phaseplane) is called trajectory. The representation of the solutions inthe phase plane is more convenient because some points andcurves on it have some special properties and play a significantrole on SRAM analysis and stability. For instance the cross points ofthe butterfly curves are the equilibrium point (EP) of the SRAMcell. It is obvious that the metastable point is also an EP (for thehold mode). The first two are stable but the last one is unstable.Note that these EPs are moved to different locations during readand write operation since the shape of butterflies and their crosspoints change. Furthermore, the curve that plays a significant role

in our analysis is the separatrix [32]. Separatrix is a curve thatsplits the VL–VR plane into two sub-planes one for each stable EP.All the trajectories that start from one of these sub-planesconverge to one of the two equilibrium points. In addition,separatrix passes through the metastable point. All these conceptsare depicted in Fig. 20.

Let us now use DNM for the analysis of cells that are staticallyunstable, that is cells for which their butterflies cross in only onepoint during read mode (see Fig. 21). In the example of Fig. 21 if atrajectory starts from the EP (VDD, 0) after some finite time it willcross the separatrix and then it will reach the unique read modeEP. When the access transistor turns off, this trajectory will reachthe EP (0, VDD). It is obvious that this cell is dynamically unstablebecause the stored data is not the same before and after readoperation. Let us suppose now that the time the WL is high is shortenough then the trajectory may not have enough time to cross theseparatrix and reach the other EP, thereby, retaining the data. Inthis case, the cell is dynamically stable. These two scenarios are

Fig. 19. (a) Read noise margin and (b) write margin versus temperature.

Fig. 20. Simulation results for CWD and MLWD designs.

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–34 31

shown in Fig. 22. Hence, we understand that the use of DNM isnecessary for the study of non-conventional wordline drivers suchas the proposed MLWD driver.

5.6. Implementation-area

We have implemented the layout of a thin-SRAM cell asdepicted in Fig. 23. As it is shown the area of this layout is largerthan the standard SRAM layout design due to using logic designrules to draw the SRAM layout results in 1.09 μm2 that is 2� largerthan standard SRAM layout. The layout of the MLWD and CWDdesigns is shown in Fig. 24. Note that the capacitor Cboost isimplemented using a MOSCAP device which shows differentcapacitance values at different biases, for instance Cboost¼17 fF,10 fF and 2 fF for capacitance voltage equal to 1 V, 0 V, and �1 Vrespectively. To drive larger wordline loads, larger MOSCAP isrequired. Although the area overhead for a the proposed MLWDcompared to CWD design is 46%, the total area overhead due toMLWD circuitry compared to CWD is less than 2.5% for a 128 Kb

memory array that is shown in Fig. 25. This is attributed to thesmall area of a whole wordline driver circuit compared to the totalarea of SRAM array. The whole area of a MLWD array is 7.9% of thearea of a 128 Kb SRAM array without lateral circuitry (128 KbSRAM array area: 144,300 μm2, MLWD array: 12451 μm2, and CWDarray: 8493 μm2). By assuming the standard layout of SRAM arrayas half of our SRAM array layout in this paper, the area overhead is4.9%. As a result, the area overhead of the proposed design is smallcompared to modifying SRAM cell circuit that gives significantlylarger area overhead such as 10T-SRAM gives 2� larger areaoverhead compared to 6T-SRAM cell.

6. MLWD in other SRAM topologies

Fig. 26 shows the schematics of the 8T-SRAM and SchmittTrigger SRAM (ST-SRAM) cells proposed in Refs. [33,34], respec-tively. By applying MLWD to 8T-SRAM cell, access time degradesdue to single-ended bitline for the 8T-SRAM cell. Since read andwrite wordlines are separated in 8T-SRAM cell, the trade-offbetween read and write has been resolved. Therefore, our pro-posed technique can be applied to 8T-SRAM cell to improvewritability of the circuit due to the boosted write wordline.However, since in MLWD, wordline voltage is pulse-shaped, theaccess time degradation is inevitable. However, conventional 8T-SRAM cell still suffers from the half select disturb similarly to the6T-SRAM cell due to the boosted wordline voltage.

Fig. 22. Simulations results for CWD and MLWD.

Fig. 23. Thin-cell 6T-SRAM cell layout.

Fig. 24. Layout of (a) MLWD and (b) CWD designs.

Fig. 25. Layout of 128 Kb SRAM array including MLWD and CWD layouts.

Fig. 21. Simulation results for MLWD at different levels of VF (WL).

F. Moradi et al. / Microelectronics Journal 45 (2014) 23–3432

The ST-SRAM cell improves read SNM by 1.47� compared tothe 6T-SRAM cell. Therefore, considering the effect of MLWD onthis design can be interesting. By applying MLWD technique, bothread and write margins are improved. The main reason of suchimprovement is due to lowered level of wordline voltage duringread. For instance, the level of voltage for primary time of readcycle is at 0.96 V for a load CWL¼10 fF showing that access time isdegraded by few percent while SNM is improved. However, as itwas explained previously, for larger CWL values, such as 30 fF, theread wordline voltage is reduced to 0.92 V that results in animproved SNM. Moreover, as it was mentioned, the proposedtechnique, MWLD, improves DNM significantly. Write margin isimproved, also, due to the boosted wordline to a level up to 1.184 Vfor CWL¼10 fF.

By applying MLWD to the ST-SRAM cell we can get at least1.94� read SNM improvement compared to using the CWDscheme.

This technique can be applied to a transmission-gate pass-transistor SRAM (TGPT-SRAM) cell as shown in Fig. 27a. As it canbe seen, by the use of high-Vth (HVT) devices for the write-assistaccess-transistors, leakage through access transistors can bereduced when the data is read. Furthermore, by using Low-Vth

devices for access transistors, the access time degradation at lowersupply voltages can be compensated. However this comes with apenalty in read noise margin degradation. Furthermore, similar to

the 8T-SRAM cell non-selected columns are affected by highvoltage of the wordline during write. The use of TGPT-SRAM cellleads to 25% area penalty compared to 6T-SRAM cell. As it is clearfrom the SRAM topology shown in Fig. 27a, the trade-off betweenread and write can be solved due to independent access transistorsfor read and write. For instance, to improve the write margin,access transistor with gate connected to WWL, can be upsizedwithout any effect on read noise margin and access time. Inanother side, the access transistor for read is weakened to improvestatic noise margin while access time degradation is inevitable.

Another configuration that can be used is to separate RBL (readbitline) and WBL (write bitline) as shown in Fig. 27b. This SRAMtopology provides a further improvement in read SNM and accesstime. Note that in this case, we should use separate wordlinedrivers for read and write. Due to this fact, there is an areaoverhead due to the required separate lines for read and write.The main advantage of this circuit is that it is not necessary toprecharge bitlines for each write/read. In this case, there is apossibility of using write bitlines floated that gives a higher writetime and write margin to the proposed SRAM cell. Furthermore,this topology is not suffering from the dummy-read due to theseparated read and writes lines.

7. Conclusions

In this paper, we proposed a multi-level wordline driver(MLWD) to improve write margin and leakage power keepingthe degradation in read access time low. Furthermore, the pro-posed MLWD scheme improves the read noise margin by at least2� compared to the conventional wordline driver (CWD). Whenapplying the proposed MLWD to an 8T-SRAM and a Schmitt-trigger SRAM cell, the read-SNM is improved by at least 1.96�compared to conventional wordline driver. Total power reductionrate depends on the number of reads and writes in an SRAM array.In general, leakage power is reduced due to the negative level ofwordline during hold mode. Furthermore, we proposed an 8T-SRAM cell (TGPT-SRAM) using MLWD scheme to separate read andwrite wordlines resulting in improved read SNM. Although theproposed MLWD scheme can be applied to any SRAM cell, it issuggested to accompany in SRAM cells with dual bitlines.

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