Multi-Level Paging

Multi-Level Paging2-Level Page Table & 3-Level Page TableECC3203 - Operating SystemGroup

Lai Chan Weng 163853 Lee Hong Ken 163663 Siti Norazlin Binti Maslan 158953 Muhammad Ahnaf Rabbani Bin Muhamad Radzi 161885 Ros Aina Shuha Abdullah162555 Lee Hock Shiuan161805 Why Multi-Level Page Table?Single-Level Page TableMajor Problem required large memory to hold page table alone.

Example: A processor with 32-bit virtual address space, 4K page sizePage Table: 20 bitOffset: 12 bit

Why Multi-Level Page Table?20 bit of page number = millions of page number in a page table

If 4 bytes/entry, it require 4MB of physical memory to store it page table alone. (WASTE)Most process doesnt use all areas, they only use areas that scattered around the VM.

Solution: Multi-Level Page Table

2-Level Page TableConsists of:Page Directory (Page Table 1) 10 bitPage Table (Page Table 2) 10 bitOffset 12 bit

CPU look up PD to find #PT, then look up PT to find #Page Frame. Now each page table has only 1024 entries.Eg. Intel 80386 architecture

2-Level Page Table

3-Level Page TableConsists of:Page Directory Pointer (Page Table 1) 2 bitPage Directory (Page Table 2) 9 bitPage Table (Page Table 3) 9 bitOffset 12 bit

CPU look up PDP to find #PD, then look up PD to find #PT. Then look up PT to find #Page Frame. (PAE)Eg. Sun Sparc and Motorola 68030 architecture

3-Level Page Table

Single/Multi Page Table?AdvantageDisadvantageindividual page tables are smaller, and easier to allocate space forpage tables themselves may be pagedefficiently represents scattered virtual memoryoverhead when most of the virtual address space is actually used and consume more memoryAdditional InfoDifferent process/application will required different size of page table.32 bit System use 3-Level Page Table with Physical Address Extension (PAE) enabled to provide 4 bit address extension to make virtual address 36 bit wide.PAE always off in default in 64 bit System due to it already have 48 bit wide.