Multi-Gbit/s Capable 65nm CMOS Ser/Des Design Analysis for Space Application Dugoujon, L.1; Hili,...
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Transcript of Multi-Gbit/s Capable 65nm CMOS Ser/Des Design Analysis for Space Application Dugoujon, L.1; Hili,...
Multi-Gbit/s Capable 65nm CMOS Ser/Des Design Analysis for Space Application
Dugoujon, L.1; Hili, L.2; Skoulaxinos, S.3; Papadas, C.3; Baguena, L.4; Childerhouse, M.5; Tonietto, D.1; Ramet, S.1; Badets, F.1; Lavastre, S.1; Briand, P.1
1STMicroelectronics (France); 2ESA (The Netherlands); 3ISD Athens (Greece); 4Thales Alenia Space (France); 5EADS Astrium (United Kingdom)
AMICSA 2008 31 August – 02 September
Sintra, Portugal
2AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
ST Global Presentation
3AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
ST Global Presentation
4AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
ST Global Presentation
5AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
ST Global Presentation
6AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
ST Space & HighRel History & Policy
First space supplier ever SCC-B Qualified (1979)Major ESA QPL contributor1999: Creation of Rad Hard Design Center in ST-Sicily
Expanding product portfolio
ST Space & HiRel Policy:Wide & stable Product Range offerings300krad at High Dose Rate & ELDRS (world leadership).Top level Heavy Ions requirements Top Level Space Quality Develops world business through QML-V Qual (1998)Full support & commitment to Europe national Space Programs:
« GalileoSat », « NGP », « Digital Divide », « COSMO » , « XMM »
Dedication to custom products support
7AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Space Product Portfolio extract
Available:Classical bipolar Transistor 2N2222’s series300krad ELDRS-free Bipolar Linear Regulators: RHFL4913, L7913300krad ELDRS-free Bipolar Op-Amps: RHF43B300krad Bipolar fast Op-Amps RHF300=>RHF350 series100krad Logic series: 54HC00’, CD4000B’s (Escc)300krad Logic serie: 54AC00’s (Qml-V)300krad 16-bit Bus Interfaces: 54VCXH162244’s (Qml-V)300krad 12-bit AD-Converter: RHF1201 (Qml-V)300kRad 14-bit ADC RHF1401 Qml-V in 2008.
In the pipe:Smd Diodes 1N5822-5819-5811-5806 ‘s100 kRad PowerMOS100kRad ELDRS-free 2N Transistors redesign300krad 32-bit Bus Interface 54VCXH322245 EM avail, qual ‘08 300krad ELDRS-free Quad Op-Amp RHF484 300krad ELDRS-free fast Op-Amp RHFS111 of a new RH-SOI technClock Distributor RHFLVDS111, 650MHz, EM avail
8AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Juno Spacecraft
ST INSIDEMSL ROVER
L = ~9’
JWST Telescope
9AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Need & constraints for Gbit/s SerDes
Main application: Next Generation Telecom Satellites Digital Payload
Partnering with European space industry primes:EADS-Astrium, Thales-Alenia Space
Key objectives of KIPSAT project (under ESA contract):Assessment of ST 65nm long term reliabilityDemonstration of SerDes 6.25Gbit/s performancesBaseline for a space-grade ASIC technology
10AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
System Architecture example
11AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Payload ASICs constraints
Payload Processor ASIC requirements:10-30 Millions gates- 3-8Mb RAM - 6Gbit/s Serial I/Os – 200-400MHz Processing Clock – Low dissipation – High-Reliability - RadHard – Hermetic Package – Moderate customization costs for Manufacturers
Such performances are only achievable with Deep Sub Micron
ST proposed its CMOS 65nm, commercially qualified in 2007.
12AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
ESA Requirements / Intrinsic 65nm
10-30 Mgates400MHz clockLow power < 10W>20 x 6.25Gbit/s HSSLAvailable before 2011Non ITARTID > 200krad(Si)No SEL 80MeVcm2/mg
SEE<10-10/b/day in geo15 years opl. lifetimeViable business model
750 kgates/mm22GHz stdcells5.7nW/(MHz x gates)1.25-7.5GBit/s modulesProduction in 2008Made in Crolles (Isère-F)No variation 100krad(Si)OK with process option
Efforts needed for SEUsAchievableMPW/MLR or Platform
13AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
What? 65nm for Space!
Do we risk in such recent technology?
What about:Rad-hard capabilitiesReliabilityCostDesign flow
14AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Rad-hard maximisation
Rad-hard capabilities measured under ESTEC-ST contracts (ST 130nm, 90nm, 65nm and 45nm)Usage of process option for SEL (1mask)Experimental confirmation on worst case supply and TempValidation of « analog » HSLL IP (LC-tank VCO)Re-use of SEU mitigation techniques (ST patented) on Std. Cells and clock-trees specificaly developed for this 65nm platformUsage of a mix of SRAM or rSRAM (ST patent) cuts to be defined with end-usersRH by design ST (+CERN) know-how enriched by end-users cooperation.
15AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Reliability maximisation
Analysis of reliability figures from Std qualification
Systematic application of ST DiR methodology (focusing HCI and NBTI) with dedicated tools for ageing simulations
Eventual specific layout rules for reliability enhancement
Study of tighter controls at process level
16AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Reliability summary for ST 65nm
LEVEL1 (Wafer Level Reliability):Even with Worst Case test conditions, all but two items (NBTI+HCI) exceed 15 years spec on test structures.NBTI + HCI: Accurate simulation methodology + design guidelines provide means to exceed 15 years on actual IC.
LEVEL2 (Early Failure Rate + Over Life Test ) :Qualification step: 8 fails out of ~ 6000 samples. All explained by defectivity/SPC. Post-Qual monitoring: 0 fail (10 years) out of ~4000 samples. Huge enhancement of D0 with the PDF program.
17AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Device Reliability Modeling
Goal: Cover all VG/VD domain
DRAIN
SOURCE
SUBSTRAT
GRILLEDRAIN
SOURCE
BULK
GATE
VG
VD
VG+
VD+
PBTI
Off-state
HCI
VG+
VD+
NBTI
HCI
Off-state
NMOS
PMOS
18AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Transistor-Level Reliability Simulation FlowReliability model (Eldo UDRM)
•Extended models
•Age.lib object Library
Eldo
Nominal Results
Aged Results
Comparison
Stress analysisAging related
commands
Description of Transistor Stress
as function of Activity
SPICE model
Netlist
Simulate Fresh
Model Parameters
(Fresh)
Simulate Aged
Reliability
parameters
Description of SPICE parameters
evolution as function of Stress
Updated SPICE parameters
Stress File
Optional
19AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Reliability Modeling/Simulation Flow
Estimation of degradation ofDifferent transistors
Evaluation of degradedSPICE
Running Simulation with degraded models
Compare
Circuit spice n/l
Input stimuli+
Model describing the degradationf(Ids,Ib,W)-HCIf(Vgs,Vds,T,L,t)-NBTI
Add toSpice model
Extraction of degradation parameters such as Vt, gm andIV curves during stress
ModelSPICEparameter evolution
Reliability Modeling
At designer end
STEP 2
NBTI, HCI stress experimentsMultiple Vgs/Vds conditions
Estimation Different transistors
Evaluation of degradedSPICE
Running Simulation with degraded models
Compare
Input stimuli+
Reliability Simulation
Model describing the degradationf(Ids,Ib,W)-HCIf(Vgs,Vds,T,L,t)-NBTI
Add toSpice model
Extraction of degradation parameters such as Vt, gm andIV curves during stress
ModelSPICEparameter evolution
Reliability Modeling
At designer endAt designer endSTEP 1
STEP 2
NBTI, HCI stress experimentsMultiple Vgs/Vds conditions
Iterative
20AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Silicon Validation
Inverter ring in 65nm technologySimulations similar to HTOL of fab silicon
21AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
NBTI simulation: digital buffer
Note the delay introduced by the NBTI in comprison to the same buffer without NBTI
22AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
NBTI: Vth shift
Illustration of the input threshold shift in I/O buffer
23AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
SERDES principle
Data Slice
Clock SliceData Slice
Data SliceData Slice
4 to
10
dat
a S
lice
s pe
r C
lock
Slic
e
/2I Q
TX
output
RX input
Ref Clk
3.1
25
GH
z
offset Cancellation
24AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
SerDes features
Technology 65nm LP ,7 metal ,triple VT, Dual Gate oxide 50A
Power S. Single 1V2
Data Rates 1.25, 2.5, 3.125, 3.75, 5, 6.25, 7.5Gbps with a single 156.25 ref. clock. (125Mhz ref clock supported )
IO RX equal. adaptive , linear up to 15dB + 4 tap DFE TX: 5 Tap FIR, programmable
Stackability 4 links per macro
Power (mW/Link)
250 max @7.5Gbps, 200 max @ 5Gbps
Area/Bump 900u x 640u /link ( 10 bumps) designed for 2-2-2 FCBGA
Reference CEI-6 LR Use: Long reach backplanes lines
Maturity IP Test chip fully tested, ASIC products in qualification
Doc Data sheet available ; CAD views available
25AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Bump usage
Bump Ball
Signal 1 1
AVDD 4 1
AGND 4 1
VCC TBD 1
Bump to ball ratio
Rate
data slice clock slice
power supply power supply
1.1 1.2 1.3 1.1 1.2 1.3
1.25
2.50
3.125
3.75
5.00 172 200 63
6.25 187 68
7.5 201 250 73
Power consumption table
Require 1 Resistor and 1 Cap on package
Designed for FCBGA build up 2-2-2 substrate.
Package notes
Clock + 4 Data slices Bump out
Core side
Power at Vod peak =400mV
SerDes Packaging constraints
VSS
VCC
VSS
VCC VCC
RXP_LI_3P
TXP_LO_3P
RXP_LI_3N
TXP_LO_3N
CKP CKN
RT
VS
S
VC
C
VS
S
RXP_LI_2P
TXP_LO_2P
RXP_LI_2N
TXP_LO_2P
RX
P
TXP_LO_1P
RXP_LI_1N
TXP_LO_1P
VC
CV
CC
VS
S
VS
SV
SS
VC
C
VC
CV
CC
VS
S
VS
SV
CC
VS
S
VC
C
VS
S
VC
CV
CC
VS
S
VS
SV
SS
VC
C
VC
CV
CC
VS
S
CP
CN
VC
CV
SS VSS
VCC
VSS
VCCVCC
RXP_LI_0P
TXP_LO_0P
RXP_LI_0N
TXP_LO_0P
VS
S
VC
C
VS
S
RXP_LI_1P
VC
CV
CC
VS
S
VS
SV
SS
CN
900u
640u
480u
120
0u
Update : 1clock slice support 8 data slices (tbv) 12 @7.5G (tbv) 16 @6.25
Edge of die
Core side
26AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
SerDes Terrestrial > Space
Organic fcBGA Pkg, 17x17, 2-2-2, 256 Balls, 1.0 mm ball pitch
Hermetic package solution under analysis
Target BER <10-18 (on CAT4K legacy backplane) ESA specs of <10-12 (medias to be defined)
250mW max power @7.5Gbps, 200mW max power @ 5Gbps
ESA spec=200mW, slight power reduction under study
Re-simulations with ageing effects and eventual rework15-20 years verification in worst case conditions
27AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
SEUs mitigation techniques
Analysis of SerDes critical areasReplacement of standard dffs by robust dffs (ST patents)Use of robust clock-trees (ST patents) where criticalImplementation of TMV where necessaryContinuous reading of configuration registers and automatic recovery in case of corruption
28AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Ser/Des Validation (1)Astrium has evaluated and tested Texas and Xilinx Ser/Des systems.Texas TLK2711 – 1.6 to 2.5 Gbps
Tested with parallel clock at 1.6Gbps and 2.5Gbps.Tested with nominal supply voltage (2.5V) +/-0.1V.
No noticeable correlation was apparent.Tested with various lengths of differential stripline traces and 50 ohm matched length coax cable.
Stripline lengths of 10, 15, 20, 30, 40 inches and combinations thereof.Tested using built in PRBS (27 -1) in a loop back configuration.Eye measurementsJitter measurementsBER measurements
Error free, from 1.6 Gbps to 2.5 Gbps, within a determined distance.
29AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Ser/Des Validation (2)Xilinx ML321 – 3.125 Gbps
Tested at 3.125 Gbps and 2.5Gbps using on-board and external oscillator.Tested with various lengths of differential stripline traces and 50 ohm matched length coax cable.
Stripline lengths of 10, 15, 20, 30, 40 inches and combinations thereof.
Tested using built in PRBS generator using various polynomials in a loop back configuration with 33% pre-emphasis.Eye and jitter measurements.BER measurements..
Error free, at 2.5 & 3.125 Gbps, within a determined distance, with short PRBS polynomials.
Xilinx MK322 – 10 GbpsTested at 5 Gbps and 10 Gbps with various lengths of differential stripline traces and 50 ohm matched length coax cable.Tested using built in PRBS generator using various polynomials in a loop back configuration with default and optimised pre-emphasis.Eye and jitter measurements.BER measurements.
Virtually error free, at 10 Gbps, over shorter distances.
30AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Ser/Des Validation (3)
“Quatuor” ValidationTest Quatuor configurations that are likely to be used in telecoms payloads.Test various parametric configurations, e.g. pre-emphasis, output level, equalization.Consider requirements for autonomous link establishment and maintenance in space environment subject to SEE.Prove that unidirectional links can be established, that link performance degradations and link loss maybe detected and that links can be re-established. Test with various media as expected to be used in telecoms payloads.Test impact of clock quality on measured BER.Perform eye and jitter measurements.Estimate best achievable BER (assuming ideal Rx and clock recovery) in the absence of other noise sources.Measure BER.Participate in radiation testing of QuatuorAdvise on the design of evaluation board ensuring direct access to parallel digital data.Consider the design of dedicated test hardware, for BER, for link establishment and maintenance, for SEE testing.Consider hiring dedicated parallel BER Tester.
31AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Validation with TAS (1/1)
Thales Alenia Space has been implementing such kind of components for a long time, starting with first generation of 400 Mbits/s links, that are now in orbitMore recent payloads required far higher
speeds and Serdes components from 1 Gbits/s to over 3 Gbits/s have been evaluated in our labs
We are presently working on last generation of components up to 10 Gbits/s
2 methodologies are being used:Elaboration of our own test/evaluation breadboard including proprietary BER measurement environment on specific breadboardUtilization of commercial tools for BER on breadboard:
BER tester Anritsu 1632A up to 3,2 GbpsBER tester Agilent N4901A up to 12 Gbps
Thales Alenia Space expertise and means will support the present HSSL development
32AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Cost mitigation
FPGA Structured ASIC Full cust. ASIC
Hi-rel Rad-Hard stdcells & IPs selectionMetal-Customizable Logic
Low troughput/powerconsumption
33AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Conclusions
CMOS 65nm provides needed performances for next generation satellite telecom payload processorsNBTI and HCI are well modeled and simulated TID is not an issue, mitigation of SEUs neededHigh performances SerDes derived from a proven IP used in telecom networking productsRobust dff + clock trees available librariesEnd-users participate to demonstrator chip (4x6.25Gbit/s) definition, trade-offs, CDRs and tests2sd phase will target to provide ASIC capability
34AMICSA 2008, September 02STMicroelectroics, ISDEADS-AstriumThales-Alénia Space
Thank you!
See ST Rad-hard products atwww.st.aerospace.com