Multi-Bit Differential Signaling (MBDS) for Next Generation Off-Chip Interconnect
1
Multi-Bit Differential Signaling (MBDS) for Next Generation Off- Chip Interconnect Challenges for Next Generation High Performance Off-Chip Signaling Packaged chip PCB trace Ground plane Packaged chip Example Chip-to-Chip Interconnect • Signal integrity issues • High metal content of off-chip signaling paths contain capacitance and inductance creating low-pass frequency response • Off-chip signals highly susceptible to noise • Synchronization difficult for high-speed signals due to skew/jitter • Off-chip channels must be narrow / serial • I/O pads a precious resource • High-speed drivers must be large due to skin effect (real estate) MBDS Extends Differential Signaling Technology for Higher Channel Code Density Low Voltage Differential Signaling (LVDS) • Data encoded as – {01} or {10} • Advantages – Low switching noise – No reference noise – Coupled transmission lines – Noise rejection => low voltage swing • Disadvantages – Two connections for each bit – Wasteful in I/O pads Multi-Bit Differential Signaling (MBDS) • Data encoded with fixed number of one-bits – N-choose-M (nCm) – Example: 4c2 code set: • {0011}, {0101}, {0110}, {1001}, {1010}, {1100} • Advantages – Same noise rejection as differential – Higher information capacity “N choose M” Channel Encoding m! m)! - (n n! } { nm X Code set size ) ( log , 2 m n eff X bit Effective bits EXAMPLE 6-wire MBDS channel code size = 20 codes effective bits = 4 equivalent to 8-wire differential channel 25% fewer pads (8 versus 6) 25% less power (4 1-bits on versus 3) 125% code capacity (20 Jason Bakos, Donald M. Chiarulli University of Pittsburgh Extending Current-Steering LVDS drivers to Support Arbitrary Channel Widths Bias input 2c1 input 2c1 output 2-wire Differential (2c1) Driver Bias inpu t 4c2 inpu t 4c2 output 4-wire MBDS (4c2) Driver Need Solutions for High- Performance Off-Chip Signaling Core Logic Speed and O ff-C hip B us S peed for IntelP rocessor A rchitectures 0 500 1000 150 0 2000 2500 3000 3500 486 486 P entium P entium P entium II P entium II P entium III P entium III P entium III P entium III P entium III P entium III P entium 4 P entium 4 P entium 4 P entium 4 P entium 4 Processor G e neratio n Speed (M H z) core speed bus speed Source: Intel Corporation Images of fabricated and packaged die Layout of MBDS Test Die Test Results Outputs from Off-the-Shelf LVDS Receiver, 200 Mbps Outputs from MBDS Receiver, 500 Mbps LVDS Receiver LVDS receiver design from: Stefan Hirsch, Hans-Jörg Pfleiderer, “CMOS receiver circuits for high-speed data transmission according to LVDS-standard,” Proceedings of SPIE Vol. 5117 (2003). Test Setup Simulation Setup / Results solder bump model wire bond model solder bump model Chip Package Model PCB Transmission Line Model Parameters Sample inputs Extracted netlists Extracted netlists 2c1 channel at 1 Gbps, 500 bit times, scale +/- 1 V 4c2 channel at 1 Gbps, 500 bit times, scale +/- 600mV 8c4 channel at 1 Gbps, 500 bit times, scale +/- 600mV Eye plots show no significant loss of signal integrity as MBDS channel width is scaled up
description
Need Solutions for High-Performance Off-Chip Signaling. 2c1 input. 2c1 output. 4c2 output. 4c2 input. Layout of MBDS Test Die. Bias input. Simulation Setup / Results. Bias input. Extracted netlists. Extracted netlists. - PowerPoint PPT Presentation
Transcript of Multi-Bit Differential Signaling (MBDS) for Next Generation Off-Chip Interconnect
Multi-Bit Differential Signaling (MBDS) for Next Generation Off-Chip Interconnect
Challenges for Next Generation High Performance Off-Chip
SignalingPackaged chip
PCB trace
Ground plane
Packaged chip
Example Chip-to-Chip Interconnect
• Signal integrity issues
• High metal content of off-chip signaling paths contain capacitance and inductance creating low-pass frequency response
• Off-chip signals highly susceptible to noise
• Synchronization difficult for high-speed signals due to skew/jitter
• Off-chip channels must be narrow / serial
• I/O pads a precious resource
• High-speed drivers must be large due to skin effect (real estate)
MBDS Extends Differential Signaling Technology for Higher Channel Code Density
Low Voltage Differential Signaling (LVDS)
• Data encoded as– {01} or {10}
• Advantages– Low switching noise– No reference noise– Coupled transmission
lines– Noise rejection => low
voltage swing• Disadvantages
– Two connections for each bit
– Wasteful in I/O pads
Multi-Bit Differential Signaling (MBDS)
• Data encoded with fixed number of one-bits– N-choose-M (nCm)– Example: 4c2 code set:
• {0011}, {0101}, {0110}, {1001}, {1010}, {1100}
• Advantages– Same noise rejection as
differential– Higher information
capacity
“N choose M” Channel Encoding
m! m)!-(n
n!}{ nm X
Code set size
)(log ,2 mneff Xbit
Effective bits
EXAMPLE6-wire MBDS channel
code size = 20 codes
effective bits = 4
equivalent to 8-wire differential channel
25% fewer pads (8 versus 6)
25% less power (4 1-bits on versus 3)
125% code capacity (20 codes versus 16)
Jason Bakos, Donald M. Chiarulli
University of Pittsburgh
Extending Current-Steering LVDS drivers to Support Arbitrary Channel Widths
Bias input
2c1 input
2c1 output
2-wire Differential (2c1) Driver
Bias input
4c2 input
4c2 output
4-wire MBDS (4c2) Driver
Need Solutions for High-Performance Off-Chip Signaling
Core Logic Speed and Off-Chip Bus Speed for Intel Processor Architectures
0
500
1000
1500
2000
2500
3000
3500
48
6
48
6
Pe
ntiu
m
Pe
ntiu
m
Pe
ntiu
m I
I
Pe
ntiu
m I
I
Pe
ntiu
m I
II
Pe
ntiu
m I
II
Pe
ntiu
m I
II
Pe
ntiu
m I
II
Pe
ntiu
m I
II
Pe
ntiu
m I
II
Pe
ntiu
m 4
Pe
ntiu
m 4
Pe
ntiu
m 4
Pe
ntiu
m 4
Pe
ntiu
m 4
Processor Generation
Sp
ee
d (
MH
z)
core speed
bus speed
Source: Intel Corporation
Images of fabricated and packaged die
Layout of MBDS Test Die
Test Results
Outputs from Off-the-Shelf LVDS Receiver, 200 Mbps
Outputs from MBDS Receiver, 500 Mbps
LVDS Receiver
LVDS receiver design from:
Stefan Hirsch, Hans-Jörg Pfleiderer, “CMOS receiver circuits for high-speed data transmission according to LVDS-standard,” Proceedings of SPIE Vol. 5117 (2003).
Test Setup
Simulation Setup / Results
solder bump model
wire bond model
solder bump model
Chip Package Model
PCB Transmission Line Model Parameters
Sample inputs
Extracted netlists
Extracted netlists
2c1 channel at 1 Gbps, 500 bit times, scale +/- 1 V
4c2 channel at 1 Gbps, 500 bit times, scale +/- 600mV
8c4 channel at 1 Gbps, 500 bit times, scale +/- 600mV
Eye plots show no significant loss of signal integrity as
MBDS channel width is scaled up
