Multi Annual Strategic Plan1 &

Research Agenda 2010Proposed by the AENEAS association

1The MASP is supplementary to the second edition ENIAC Strategic Research Agenda as launched in November 2007

DRAFT v8

14 October 2009

 

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Table of Contents  

General 5

Strategy in Context 5

Mapping the Future: The SEMIP Strategy 7

Demands 7

Safety 7

Environment 7

Mobility 7

Industry 7

People 7

Response 8

Rationale for Public Funding 8

The need for Public Authorities to play an active role 11

Fundamental Changes in the Semiconductor Industry: 13

European strengths 13

Vision of the European Nanoelectronics Industry 13

Linking SEMIP to the intricacies of the Nanoelectronics Industry 14

Making it happen 15

Automotive and Transport 16

Introduction 16

Relevance for Europe 16

Grand Challenges 17

a) Improvement of the conventional combustion technology: 17

b) Development of advanced hybrid technology and of the full electric car: 17

c) The way towards the safe car: 17

d) General requirements: 18

Conclusions 18

 

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Conditions for success 18

Timeframe 19

Synergies with other SPs 19

Wireless Communications 20

Introduction: Driving Forces in Wireless Communication 20

The three Grand Challenges are: 21

1. Front End & Back End heterogeneous 3D integration Platform: 21

2. Technologies for “Green” Wireless Communication: 23

Adaptive radio 24

Energy Efficiency 28

Introduction 28

Relevance for Europe 28

Market value 28 Social Benefits 28

Grand Challenges 29

a) Power generation 29

b) Power transmission/distribution 29

c) Power consumption – which is to a very high degree linked to the grand challenge “CO2 reduction” 29

d) Technological requirements: 30

Conclusion 30

Conditions for success 30

Timeframe 31

Synergies with other SP 31

Design Methods and Tools 32

Introduction 32

Grand Challenges 35

Design efficiency for functional complexity 35

Reliability and yield by design 35

Energy efficient design 36

 

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Conclusion 36

Timeframe 37

Synergies with other SPs 38

Silicon Process and Integration 39

Introduction 39

Grand Challenges 40

Grand Challenge 1 – “More Moore” technologies 40

Landscape and needs 40 Implementation 41 Expected benefit 41

Grand Challenge 2 – “More-than-Moore” technologies 42

Landscape and needs 42 Expected benefit 43

Grand Challenge 3 – Technologies for “Heterogeneous Integration” 43

Landscape and needs 43 Implementation 44 Expected benefit 44

Conclusion 44

Equipment, Materials and Manufacturing 45

Introduction 45

Grand Challenges 46

Grand Challenge 1 – EUV and complementary 1Xnm patterning 46

Grand Challenge 2 – 450mm supply chain 47

Grand Challenge 3 –”More Moore” innovations 47

Grand Challenge 4 –”More than Moore” innovations 47

Conclusion 48

Conditions for success 48

Executive Summary 49

 

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General Strategy in Context The start of the new millennium brought a new élan to Europe but also many new issues with it.

European citizens demand that key issues such as global warming, an aging society and security be addressed. At the same time, they want to ensure the prosperity of their younger generation by

building a sound economic base.

In our competitive world, business as usual will not address these demands. A top-down strategy based upon innovation is required. The Nanoelectronics industry is a cornerstone industry for innovation. In order to see the bigger picture of the European Nanoelectronics industry’s position in the global market see the www.eniac.eu homepage. It is at the root of solutions for health, medical, environmental and several other developments that will make the difference between positioning Europe as a leader or follower of other regions in the years to come.

A consistent strategy in these fields will allow Europe to set the agenda in respect of Global Warming and Security. It will turn Europe’s aging population into an asset, bringing Europe to the forefront of health and Ambient Assisted Living (AAL) solutions. In return, it will strengthen the European Nanoelectronics ecosystem consisting of world-class scientists, thousands of SMEs and many globally operating semiconductor companies. Investing in R&D for Nanoelectronics is an investment in an industry that contributes to more than 10% of the European GDP and that

Highlights of the Strategy for European Nanoelectronics

The Nanoelectronics industry is a cornerstone industry for innovation but it is exposed to an extremely competitive and rapidly changing global environment.

What we would like to achieve for Europe in the next decade is as follows: • A strong European Semiconductor

industry in technologies serving the Mega-Trends like Mobility, Safety and Security, Energy, Efficiency and Health.

• A stable IP and patent profile in the industry and within institutes and universities.

• Powerful European Nanoelectronics Ecosystems which combine R&D, innovation and applications.

• Control of key technologies for strategic applications as used in aeronautics or for critical infrastructures.

• Autonomy in components for time-critical system developments.

In order to meet these objectives, we need:

• Differentiated and balanced Fab-Strategies which combine own manufacturing sites for differentiated products with foundries for other products.

• Constant improvement of European “More than Moore” production sites and empowerment of European Foundries.

• Strengthening of the aspects of the Value Chain where, through differentiation, Europe can gain competitiveness and new market shares.

• R&D platforms for Si-processes, for Design and for Equipment/ Materials/Manufacturing which combine efforts from industrial partners with academic partners.

Source : IMF, WSTS, ESIA, DECISION, SEMI Note: World GDP estimated at Power Purchase Parity

World GDP = 64900 BUS$ Service

Electronic

Semiconduct

Automotiv IndustriaMedica Spac

Defens

$256

$1500

$6300

Eqpmt$43B

Materials $42B

Internet Service providerGame

Telecom OperatorBroadcas

World GDP = 64900 BUS$ Service

Electronic

Semiconduct

Automotiv IndustriaMedica Spac

Defens

$256

$1500

$6300

Eqpmt$43B

Materials $42B

Internet Service providerGame

Telecom OperatorBroadcast

 

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generates more than 90% of the patents in these fields.

A top-down strategy is required to provide a set of connected challenges to the Nanoelectronics industry which are derived from the demands of European citizens. This document provides such a strategy.

At the same time, Europe needs to design strategies which make it attractive for the Nanoelectronics industry to stay on the continent. These strategies should address conditions like Taxation, Employment and Education. When comparing Europe to Asia or to the USA, Europe needs to ensure that it is on an equal level at least. Ideally, Europe should be the continent of choice for Nanoelectronics activities. These strategies are not addressed in this document. The ESIA Competitiveness Report of 2008 and the ENIAC SRA of 2007 provide an overview of these strategies. The current economic and financial crisis provides a good opportunity for counter-cyclical public funding. Not only will this soften the consequences of the crisis but it will also ensure a position of strength for Europe for when the crisis is over. Times of crisis are also times of reward, especially for those who made bold investments in the future. These investments should be made in the area of industrial research to encourage European developments in lead markets and to prepare the European industry to emerge successfully out of the crisis. The ENIAC funding tool is an enabler for this important objective. The way that ENIAC enables this is to ensure collaborative efforts between the players in the field. It allows for partnerships between large industries, SMEs and knowledge institutes. Thus it increases the attractiveness of the continent for the ecosystem as a whole and defers the need to move to locations that are in competition with Europe.

• Mechanisms to integrate the strengths and capabilities of the academia (“ideas”) and SMEs (“innovations”).

• Support from Public Authorities through Public Procurement, Regulations, Standards and large funded R&D programmes

Europe will continue to build on it’s strengths as follows:

• A strong presence in strategic electronic lead markets (Transportation, Wireless etc.).

• World-class clusters and world leaders in material and equipment.

• Adapted Fab-strategies using IP foundry and IDM.

As a result, Europe will have the capability to:

• Develop and manufacture its own portofolio of proprietary derivative silicon technologies (Analog, RF, Smart Power, Imaging, Memories Systems, MEMS/NEMS and Mmicrofluidics).

The spectrum of possibilities is very broad. In selecting a set number of Grand Challenges that require long-term planning, considerable effort and close cooperation throughout the whole Value Chain, the aim of the ENIAC MASP is to communicate a clear vision across Europe with the goal of enabling and accelerating the adoption of advanced silicon solutions technologies through industry leadership, in synergy with CATRENE and the EC FMWP. We believe that ENIAC is a tool that will provide all the necessary elements to focus on the most important Grand Challenges of the next decade within vertical projects and to develop the abovementioned R&D platforms in horizontal collaborative efforts. Of course, this needs to be further supported by politics and legislation, as part of a real Public-Private partnership that will create a positive environment for the Nanoelectronics industry in Europe.

 

“Semiconductors are crucial to Europe’s competitiveness.”

Enables 90 % of the key technologies and

innovations required to advance a sustainable

information and communication economy

Source: ESIA 2008 Competitiveness Report

Directly contributes to generating approximately

10 % of both European and worldwide GDP

 

 

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Mapping the Future: The SEMIP Strategy

Demands The European demands for innovative solutions can be summarised by a five-letter acronym: SEMIP. It identifies the five most important areas where the innovative power of Nanoelectronics scientists and industry can help: Safety, Environment, Mobility, Industry and People. Each of these five themes call upon Nanoelectronics based innovations in present and future lead markets that will enable the Systems industry, the Nanoelectronics industry and Public Authorities to develop solutions together in order to enhance Europe’s competitiveness. SEMIP provides a top-down strategy to achieve these goals.

Safety A lack of safety or feeling of insecurity has a paralysing effect on a society. Ensuring safety and security is a key task for Public Authorities. The increased complexity of European society calls for innovations with regards to the protection of both goods and privacy. Particular areas of focus are surveillance, defence systems, trustworthy identification systems, as well as, secure and safe transport of people, data, money and goods. These innovations should address the exploding costs and lengthy waiting times associated with safety and security simultaneously.

Environment Climate change and the accompanying challenges to the energy supply have implications for the way we live and do business. It highlights the need for innovative solutions in the areas of renewable energy, energy efficiency, smart grid, tele-presence and improvements in the air and the buildings we live and work in. As such, Nanoelectronics contributes significantly to the “energy efficient buildings” initiatives. Europe’s willingness to address the environment will create the basis for a global environmental industry that is based upon technologies from the field of Nanoelectronics.

Mobility An efficient, omnipresent, “green” and economic network for communication and transport is an important infrastructural enabler. Wireless will be the buzz-word for future communication with GSM being the first success of global proportion, pioneered in Europe. New innvovations in the car industry which are by and large based upon Nanoelectronics are critical to our transportation needs. Nanoelectronics elements, like sensors and power electronics, are important enablers of Green Car projects. Road Pricing and Virtual Offices are other key innovative solutions that address our needs for mobility.

Industry Economic growth and future prosperity are justifiable demands from our younger generation. They require a healthy industrial base. To safeguard the innovative power of Europe in the future, this even further outlines the need for a robust Nanoelectronics industry. Our world-class status in Production Equipment and Materials is envied by many outside Europe. Our capability to produce profitable new semiconductor-based solutions enables future innovations that would otherwise not be possible in Europe. The “factories of the future” initiative will build upon contributions from Nanoelectronics.

People An ageing society, due to a declining birth rate, causes increased competition for a qualified workforce. On the other hand, it also represents an opportunity for technological R&D in medical electronics, intelligent drugs, biotronics, measurements & diagnostics and Ambient Assisted Living

 

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solutions (AAL). People live in social networks. We are only at the beginning of the major role that Nanoelectronics is destined to play in respect of expanding and maintaining our social networks.

Response

The Semiconductor Industry is a key enabling industry in addressing the demands as outlined above. The industry will not present all the required solutions. However, it will provide a significant contribution to the solutions. Since solutions to these problems are of major strategic importance to Europe, the Semiconductor industry should be considered as a strategic industry. It enables Europe to offer solutions that suit its societal and cultural environment. Keeping and nurturing an independent European Semiconductor Industry is the only way for Europe to achieve solutions to the major societal themes of SEMIP without being dependent on other continents. For this reason, the creation and maintenance of an equal level playing field is pivotal. Support in R&D and in a high-quality scientific infrastructure is one of the most effective ways of levelling the playing field and guaranteeing the long-term attractiveness of Europe for this strategic industry. More precisely, the industry can contribute to the SEMIP demands by providing a couple of technological solutions. Some solutions serve several challenges whilst some are more specific. In this MASP we have focussed on those solutions that contribute to the strengthening of the Semiconductor Industry in itself. The solutions should address a market of considerable size and margin. This subset is presented in the MASP as so-called “Grand Challenges” for the Semiconductor Industry. Grand Challenges are designed to address the solutions to the demands imposed by SEMIP. Grand Challenges have at the same time a business importance and their imminent solution will contribute to the strengthening of the total sector. For the structure of the MASP, we grouped the Grand Challenges into 6 technology segments that will be addressed in the chapters hereafter.

Rationale for Public Funding • Addressing the grand challenges as areas of priority will propel the Industry Segment into the

right (commercial) direction. It stimulates realization of Economic growth.

• Fostering cooperation will encourage the inclusion and creation of SMEs in the most demanding and promising fields.

• Collaboration between large industries, SMEs and knowledge institutes enhances the attractiveness for the Ecosystem as a whole. Public funding is a crucial enabler of such collaboration.

• Appropriate governmental support will create a necessary condition for the establishment of a level playing field relative to the rest of the world.

• To achieve appropriate contributions to the SEMIP, R&D actors are asked to be more willing to take. Public funding will lower the barriers to taking these risks.

• The Semiconductor industry, its suppliers and customers operate in a highly cyclical economic environment. In economic downturns public funding must guarantee the continuity of the knowledge infrastructure.

• Not every Grand Challenge needs the support of each public authority. Subsets can be created that fit within the constraints as imposed by the ENIAC rules.

 

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The following quote, taken from the latest Communication from the Commission of the European Communities 512/3, entitled: "Preparing for our future: Developing a common strategy for key enabling technologies in the EU", emphasises Nanoelectronics as a key enabling technology: “Within ICT, specific fields such as micro- and nanoelectronics and photonics deserve immediate policy actions given the situation of the EU industry in global competition and the challenges stemming from the economic crisis.” An extensive motivation for public funding can be found in the document entitled: “COMMISSION STAFF WORKING DOCUMENT”, accompanying document to the Proposal for a COUNCIL REGULATION Setting up the "ENIAC Joint Undertaking" IMPACT ASSESSMENT [COM(2007) 356 final SEC(2007) 852]. The trends predicted in the executive summary of the aforementioned document have become a reality and in spite of the successful start of the ENIAC Joint Undertaking the unbalanced playing field has unfortunately materialised. This valuable eighty-page document is too long to reproduce within the MASP but portions of the executive summary of the document that are particularly relevant to the MASP have been quoted hereunder. “Nanoelectronics is pervasive and the motor for innovation in many areas today including mobile communications, transport, computing, consumer products, and manufacturing automation. This gives it a large economic impact or a high socio-economic relevance as for security, healthcare, aging, energy saving, and environmental monitoring. Europe must safeguard its capability to design and produce its products following its own standards of high quality, sustainability and environmental friendliness. Nanoelectronics is a global market ($265bn in 2005) directly stimulating a larger electronics industry ($1340bn) but Europe is not gaining market share. Europe is a net importer of Nanoelectronics: 12% of the worldwide semiconductor production capacity is located in Europe, while 20% of the worldwide semiconductor products are consumed in Europe. The global competition is fierce, especially by countries like Taiwan, Korea, China and the USA. Business models are changing. Nanoelectronics becomes a global activity. Integrated Design and Manufacturing (IDM) companies are increasingly relying on foundries (third-party fabs) and go fab-lite for their added-value operations or even fab-less, cooperating in ecosystems of knowledge for their R&D and in strategic alliances for their access to the most advanced technologies. This is the result of the growing capital investments (e.g. 5.5 B€ for a typical mega fab) required to research and manufacture the new generations of components. This goes above what individual companies can afford (except Intel) in terms of return on investment and rate (18%) of research. Consequently, generic Nanoelectronics technology research is executed in a few major alliances, while manufacturing of advanced commodity products is done in a few mega fabs. Europe must assure that its companies can play a strategic role in these global alliances and can keep added-value operations including advanced manufacturing in Europe, accessible to European partners (including SMEs active in equipment, support, systems integration and design). One of the main competitive risks is a 'technological lockout'. European suppliers might fall so far behind their competitors that they are unable to catch up. Research models are changing. Europe must further assure that the research can be executed on European soil in order to maintain high added-value jobs in Europe. This requires a shift from the linear model where research results are transferred from universities to institutes and industry, into a

 

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model where research is done in cooperation, deeply embedded in the industrial web supporting the knowledge ecosystems. Moreover the research must produce sufficient critical mass and allow for sharing access to expensive state-of-the-art infrastructures, supporting the European industry and its researchers in acting globally. Delocalization of Nanoelectronics manufacturing holds a real risk of migrating also added value activities to other parts of the world. Some countries have developed special incentives to attract and retain foreign semiconductor investment, whereas the EU lacks a dedicated sectoral approach to support this key industry. Europe must react with comparable measures. Product performance and functionality is growing. Advances in miniaturization allow ICT to be embedded everywhere, providing enhanced functionality, more intelligence and more personalized products and services. These added-value operations are key elements for product diversification and a strong European competence. They form the basis for a European Strategic Research Agenda combining miniaturisation with other system integration elements aimed at key European lead markets. This holds a huge economic potential in the knowledge-based society. Europe can just not afford to miss this future and become dependent for its social progress and well-being on other regions of the world. The semiconductor industry will also have to face the challenge of combining the shortening of the product life cycles with the increasing complexity of those products. In fact, only a significant investment in advanced R&D allows keeping up the pace of innovation in this sector. Technological challenges are manifold. As technologies shrink in the nano domain, research is becoming increasingly multi-disciplinary. Bringing European competencies together is essential for future progress. The rising complexity to overcome the technological roadblocks requires increased human effort and an expensive infrastructure. Mobilisation of all resources and worldwide cooperation is required to realise the milestones. It is also expected that traditional miniaturisation will reach its limits in 10-15 years. Activities have to be started to prepare for beyond the traditional scaling of devices. Part of the R&D will have to focus on improving the efficiency of production. The capabilities to design new products are lagging behind the technological progress. The European research fabric will need to redirect itself to take better account of the technological opportunities and will need to invest more in applied research. This requires a fundamental shift from single science, technology thinking into multi-disciplinary system thinking.” Please find below a further quote from the same report: “What if no action? Europe may run the risk that the competence to integrate new functionalities into smart systems will follow the off-shoring trend of commodity manufacturing, weakening in the long run the capability to produce in Europe added-value in electronic systems. This would result in a dramatic decrease in competitiveness in general, particularly as Nanoelectronics is at the bottom of a wide food-chain forming the basis of the knowledge society and a motor for the future economy at large. This would also have major consequences for the number of high quality jobs, not only in the hardware sector but for all other activities dependent on hardware innovation. In order to avoid such a doom scenario, there is a political will to safeguard more European competence on European soil while encouraging strategic alliances to form knowledge-based ecosystems as well as to strengthen European presence in global alliances.”

 

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The need for Public Authorities to play an active role An active role of public authorities is essential to the success of the ENIAC Joint Undertaking. The role in innovation ecosystems extends beyond the domain of the science and innovation policy alone because of key interdependencies in other domains. Education, Trade and Fiscal policies are important examples. Thus, public authorities must take a holistic approach that addresses the following roles: • Providing the right framework conditions

• Stimulating opportunities

• Role as Launching Customer

• Managing Human Capital

• Assisting in brokerage for new projects

In the following sections, these various roles are further explained. Providing the right framework conditions

The business sector is the engine of innovation and productivity growth. An important role for Public Authorities is to create a favourable business climate stimulating entrepreneurship and innovation in the private sector. This includes stable macro economic conditions, well functioning labour and capital markets, antitrust rules, patent rules and an excellent science and education system that is responsive to business needs. Another important issue in the domain of Nanoelectronics is the role of public authorities in setting standards. This can actually make or break a competitive position in industry. Positive examples in this respect are GSM, Bluetooth and NFC. More recent developments could include DVB-H and 3D-TV. Also public authorities can powerfully support the industry by shortening formal certification procedures necessary for the implementation of new technologies in all kind of business applications. Stimulating opportunities

Studies show that substantial government funding, consistency and long-term commitment is of vital importance to the success of the Public-Private partnership formula [OECD 2003]. This funding strengthens and accelerates the development of the ecosystem. It has two positive effects: It will help to keep and develop the industry in Europe and will help to attract foreign companies to our continent. An important aspect of the success of a Public-Private innovation programme like ENIAC is that it is characterised by private sector and market-pull co-operative ventures. In essence, this means that it must stick close to the industry technology roadmaps and R&D characteristics. The ENIAC community is an international competitive industry and has some very specific R&D characteristics. Typically companies in ENIAC have a very strong R&D focus. The costs of these R&D efforts rise exponentially, because of the growing complexity and level of multidiscipline technologies involved. The continuous time pressure together with the volatility of the industry leads to an increase in the number of partnerships required in order to cope with rising costs and to gain access to complementary knowledge.

 

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These R&D partnerships have different models and can roughly be divided into two categories:

• Large R&D platforms that develop generic technologies are needed as the basics of industry. These projects typically involve many large companies and medium-sized SME’s and universities in Europe.

• Dedicated application platforms: These projects are more targeted towards technologies needed in the different application domains that are outlined in the MASP. Also these projects are at a European level but might be somewhat smaller than the above projects.

Given these different elements, it is important that ENIAC facilitates and accommodates these different forms of R&D. The distinction in the different types of projects/programmes that vary in scale and time enables an optimal fit between the R&D strategy and models of the different players in the ecosystem. ENIAC’s role in linking the various players to each other will strengthen the Nanoelectronics infrastructure in each contributing country and in Europe as a whole. For the programme in general, it is important to monitor progress based on a well-defined set of KPI’s, including the percentage of SMEs and knowledge institutes involved and the leverage factor of the total number of private R&D investments. Role as Launching Customer

Public Authorities can play a significant role as a Launching customer. Although this role is becoming recognised by government, there are still more opportunities available. For industries represented in the ENIAC community several of these projects could be defined as driving business innovation and enhancing Europe’s competitive edge. A good example is for instance a GPS-based road-tolling system. If done on time, Europe will in fact set the standard for an automotive telematics platform that will introduce Internet in the car with several possibilities. Legislation can play a role here. Think for instance about legislation that encourages the use of tire pressure monitoring systems or energy saving lamps. Another example could be to launch a programme on alternative energy sources. This would give a boost to developments like power management etc. The essence here is that government must be more aware of the impact it can have in positive sense and must act in a more integral way to achieve this. Managing Human Capital

Naturally, the need to address this challenge is not directed at the Public Authorities alone. All stakeholders have to share responsibilities in this domain. Lack of human capital is becoming a serious issue at all technical levels (including a lack of academics). All stakeholders of this programme – industry, universities, Public Authorities, educational structures, knowledge institutes, as well as, employees themselves have an important role to play. We must join forces for the greater benefit of all. Of course, the industry will also take responsibility in solving the shortage of human capital. One key role industry has is to raise the overall awareness, level and inflow of human capital. Assisting in brokerage for new projects

Public Authorities also have a critical role to play in nurturing ideas developed in their countries by academia and SMEs by acting proactively to bring them into collaboration with other players where their innovations can potentially flourish. The assembling of the best possible consortiums to effectively address the grand challenges requires mechanisms to identify the best capabilities and to have an active management process to bring them together, rather then relying on chance or networks currently in place within the larger industrial partners.

 

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Fundamental Changes in the Semiconductor Industry: • A slow-down in the semiconductor market which is moving from a double digit average growth

during the last few years to a single structural digit growth. Independent of the economic crisis, this trend is showing that the microelectronics industry is maturing.

• The convergence between wireless, consumer and computer is requesting the development of silicon systems solutions.

• Strong developments of new domains of applications in Automotive and Energy are driving the development of “More than Moore technologies” (power, analog/RF, sensors, Mems).

• Evolution of the customer base which is moving-up in the Value Chain to let industry pool investments in common subsystems and components.

• The requested scale of R&D and manufacturing means that cooperation is becoming vital.

European strengths • World class industrial laboratories and institutes

• World leader in material, equipment, IP, foundry and IDM

• World class clusters ( but challenged by scale)

• World OEM leaders in Telecom, Automotive, Industrial and Energy

Vision of the European Nanoelectronics Industry Delocalization of Nanoelectronics manufacturing holds a real risk of migrating added value activities to other parts of the world. The European Nano-electronic industry has been able to retain in Europe the product and technology development activities with larger added value thanks to the close cooperation with key users in areas where Europe still has a leading position (automotive, telecom, industrial). Following the Aho’s report, the industrial strength of Europe can be promoted by the activation of lead markets, driven by major societal challenges, through a mixture of public procurement and support to innovation. The major challenges are in the field of energy saving, environment protection, safety and security, health and support to an ageing population. The European Nanoelectronics industry is an essential provider of technology solutions which are needed to face the grand challenges. Without an independent European source of key Nanoelectronics components, the capability of Europe to address these issues following its own standards of high quality, sustainability and environmental friendliness and to transform them into an engine for industrial and economical growth will be severely crippled.

 

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The capability of European Nanoelectronics industry to face the competition coming from other areas and to guarantee the required support to European application factors is strongly dependent on its capability to maintain technology leadership through R&D cooperation with Universities and Research Centres and the sharing of research costs, under effective public-private partnerships, and through the activation of an efficient ecosystem covering all the supply chain, from equipment and materials support, systems integration and design. A broad set of measures is required to create an appropriate business and investment climate both for R&D and for sustaining European based manufacturing capabilities. The ENIAC MASP aims to provide the R&D framework that is necessary to support it. By defining a roadmap for the industrial R&D in Nanoelectronics, derived from the requirement to support Europe in facing the grand societal challenges, MASP is providing the guidelines for the public R&D investments. This will ensure that research activity results in economic growth. It also provides a reference framework for the integration of R&D activities of all the actors inside the supply chain thus enhancing the effect of single actions. Following these concepts in ENIAC, MASP technologies have been defined on their enabling potential for lead applications that can have a significant impact on grand challenges. A total of three lead applications and three enabling technologies have been selected to better focus the research activity. Linking SEMIP to the intricacies of the Nanoelectronics Industry The Nanoelectronics industry is not organised in terms of an “aging society” or “environmental needs”. It is organized in terms of the Value Chain: Universities, suppliers, production, customers. It is also organised in terms of product lifecycle: Research, development, manufacturing, sales. Both the Value Chain and the chain of the product life cycle cannot and are not constrained by national borders. They are international by nature and require collaborative efforts that involve multiple European countries. The industry is highly competitive and has for that reason no common strategy. Competition is healthy. It keeps the total ecosystem in efficient conditions. In the Value Chain, competition exists between suppliers. In the product life-cycle, there is a precompetitive part in the very beginning. But the final phases of the Development, and the Sales and Marketing are certainly competitive, making an overall common strategy difficult, if not impossible to achieve. Nevertheless SEMIP poses a number of precompetitive challenges to the industry that have been acknowledged and that require cooperative action between the various contributors in the Value Chain. This chapter translates the SEMIP needs into so-called “Grand Challenges” for the Nanoelectronics industry. Although each “Grand Challenge” is pre-competitive, the link with industry is so strong, that in general terms the business reasons to embark on them, like expected market size, etc. can and will be given in this MASP1. These business reasons have played a role in the selection of the grand challenges. The Nanoelectronics industry describes its pre-competitive activities in terms of technologies and applications. The most important applications are “Automotive and Transport”, “Wireless Communication” and “Energy Efficiency”. The most important technologies are: “Design Methods and Tools”, “Silicon Processes and Integration” and “Equipment, Materials and Manufacturing”. In each application and technology domain “Grand Challenges” need to be solved in order to enable innovative solutions as demanded by SEMIP. Solving the “Grand Challenges” is therefore not only a condition for the strengthening and continuity of the Semiconductor Industry in Europe; it is also to be seen as the contribution of this industry to the major demands of the European Society as                                                             1 Also specific terms exist, but those cannot be communicated within the scope of this MASP, because of existing anti-trust legislation.

 

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formulated by SEMIP. The following chapters will each focus on a specific set of “Grand Challenges” and therefore describe in more detail how and to which aspect of SEMIP each “Grand Challenge” will contribute. ENIAC calls upon all R&D actors in Europe to come with solutions to the “Grand Challenges” and to stimulate collaboration between the Systems industry and the Public Authorities in order to map together Europe’s future, as formulated by SEMIP. Funding should be based upon suitability of the proposals to the “Grand Challenges” as given.

Making it happen The volatility of the field and the medium-term uncertainties in terms of technological evolution and market development prevent the creation of a very focused strategy. A broad array of options needs to be explored and called for. However, this puts larger demands on the evaluation criteria for projects supporting the MASP strategy. Next to technological soundness and proper project management, criteria will be applied that addresses some of the following: Contributing to economic growth in Europe in line with the Lisbon policy, addressing the societal needs of SEMIP, contributing to solutions to the associated “grand challenges”, stimulation of industrial standards, creation of a healthy ecosystem, including a healthy network between corporations and SMEs, including start-ups and promotion of university-industry interaction. This MASP emphasizes large projects combining enabling technologies topics with topics from lead applications. The total ecosystem value will be leveraged by addressing all players along the product and knowledge supply chain (SME, corporations, institutes, education, PA’s). AENEAS will align itself to the decisions of the CATRENE Directors Committee and the ENIAC Governing Board in respect of the effective management of both CATRENE and ENIAC.

 

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Automotive and Transport

Introduction The Grand Challenges of this Sub-Programme are both in the domain of the main economical and technological driver, which the Automotive sector. We have identified two Grand Challenges, which are to an extremely high degree dependent from new achievements in semiconductor technology, one of them covering the environmental aspects, the “Full Electric Car”, the other one covering the security and safety aspects, the “Safe Car”. As shortly described in the next chapter, both are of very high relevance for Europe and address typical European competences, available in companies, institutes and universities. The results of the planned R&D work will also impact Aeronautics and other transportation means.

Relevance for Europe Market value

Environment and safety are clear societal needs for the future intelligent road-traffic. As the volume of traffic on our roads continues to increase, there will be an increased demand for safety, emission control, fuel saving and comfort. The automotive industry represents 3% of Europe’s gross domestic product and 8% of EU government’s total revenues. Electronic components have reached 20% (of which Microelectronics is 44 %) of the car value, and the figure will continue growing after the actual economic crisis (the microelectronics share could even grow up to 55%) in the next years. In total, automotive components represented 19% of European electronic component market in 2006. These numbers include the micro- and Nanoelectronics components for the “Safe Car” challenge. The future market share of the “Full Electric Car” is not easy to predict, but recently announced targets in some European countries allow an expectation of a few million Electric Cars in Europe in the year 2020, which corresponds to a market of around 50 Billion €. Increasing oil price on one side and introduction of the smart e-grid will foster the market penetration of the Electric Car. Car industry is quite widely spread in Europe. Besides traditional main players in Germany, France, Italy and UK, strong car industry exists in Spain, Poland, Czech Republic and Rumania. Automotive industry is even more widely spread among different countries. Nanoelectronics will also give an essential contribution to the integration of all other modes of transport (air, rail and waterways) that are projected to form the largest part of freight transport and to contribute significantly to passenger traffic in year 2020. Social Benefits

The European transport system is a vital element in ensuring Europe's economic and social prosperity. It serves key roles in the transportation of people and goods in a local, regional, national, European and international context. Beside the direct impact on the transport sector, the development of new Nanoelectronics technologies for transport will bring indirect benefits to all European countries. In the first place Nanoelectronics will contribute to the reduction of energy consumption and atmospheric pollution, and help to meet Kyoto Protocol. In Europe, road transportation alone accounts for 21% of fossil fuel consumption, and 60% of all oil (OECD). Sophisticated electronics for engine management have already contributed to strongly reduce both the overall emissions and primary energy use, but much progress is still possible. The move towards hybrid and fully electric cars is the next step and will require a full set of new technologies for power management. Concerning the CO2 emission, the Full Electric Car has the potential for reduction from today’s > 120g/km to around 45g/km. An integrated approach that links all modes of transport (air, rail, road and waterway), is essential for ensuring that sustainable and competitive transport solutions make a visible and positive difference for Europe, its citizens and its industry.

 

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Road safety is another critical issue: there are 5 deadly accidents every hour, and road accidents are the main cause of death in the under-45 age group. The introduction of safety features like ABS, Airbags, and Electronic Stability Control, enabled by the quick evolution of Microelectronics have already significantly contributed to reduce the number of casualties. Nanoelectronics-based enabling technologies will allow a quick move toward the goal of zero road fatalities. In an aging society, the number of senior citizens is continuously growing. Assistive systems, driver monitoring and alerting can be leveraged to mitigate cognitive shortcomings due to age-caused disabilities. Such systems will increase security for all road users, and at the same time extend the mobility and self-determined independence of the elderly.

Grand Challenges The grand challenges as introduced above are – of course – not the only topics of this sub-chapter. On the way to the full electric car, there are different steps starting from the optimisation of conventional combustion machines and also focussing on the development of hybrid cars. These targets require the introduction of Nanoelectronics in all aspects of automotive industry.

a) Improvement of the conventional combustion technology: • More sophisticated engine management units, coupled to sensors and actuators can

further reduce fuel consumption in present internal combustion engines, allowing to a 30% reduction in average CO2 emissions for the new vehicle fleet in 2020.

• Efficiency increase and reduction of pollution in Internal combustion engines will require advanced mechatronics for fuel and air control, coupled with low-cost sensors and highly efficient computing units, based on the most advanced CMOS technology.

b) Development of advanced hybrid technology and of the full electric car: • The process of moving to hybrid and afterwards full electric cars is expected to require

several steps, involving increasingly more sophisticated systems of energy storage (batteries, super-capacitors) and energy management. Europe-made hybrid vehicle could gain a significant part of new registration by 2012, while commercial fully electric cars will start to be available around the same date.

• Hybrids and full electric vehicles will require power electronics and sophisticated and reliable power management systems, able to withstand high voltages and power surges, in order to manage power distribution among engine(s), batteries, super capacitors, and the external power supplies. The same basic technologies could be adapted to power management in industrial applications, and to the exploitation of renewable sources, mainly photovoltaics.

c) The way towards the safe car: • Active safety will see an increased use of detectors (solid state optical and IR cameras,

ultrasonic sensors, radars) coupled to high performance logic for real time obstacle detection and driving assistance. This has to be coupled with high speed, low cost data storage and processing for collision avoidance.

 

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• Passive safety will rely on increased use of sensors distributed through all the car or plane, and connected by RF or power-line. Energy scavenging will be the medium-long term energy source.

• Traffic congestion can be reduced by advancements in navigation systems, based of wireless communications and GPS, to exchange data with road infrastructures and among the cars themselves.

d) General requirements: • Distributed sensor networks, communicating through RF and supplied by energy

scavenging, can strongly reduce car weight and costs, and could be applied to a variety of segments including aeronautics and large structures, like building and bridges. It will require, in addition to reliable technology for sensors and energy scavenging sources, high performance low power logic for sensor data acquisition and handling and low cost RF CMOS technology.

• All electronic systems for automotive and aerospace applications have to withstand very harsh environments, including high temperatures, humidity, vibration, fluid contamination and electro-magnetic compatibility. The safety-critical nature of automotive systems will require extreme reliability and long life time, measured in parts per billion instead of today's parts per million.

• Cost of high performance logic for assisted driving systems must be reduced for a widespread adoption, while reducing energy consumption and increasing frequency capability through development of advanced CMOS logic technology.

Conclusions Conditions for success Regarding the technological competences and market positions, Europe has very good chances for keeping leadership in the domain of (Nanoelectronics for) Automotive and Transport. However, there is still a huge need for specific R&D work, which will represent thousands of person-years and hundreds of M€ per year. In addition to the described specific technological innovations, a few very general points shall be mentioned: • Successful introduction of really energy efficient (like full electrical car) and of safe

transportation media needs world-wide standardisation and interfaces

• It also needs a very high degree of trust in robustness and reliability of the electronic devices – especially under harsh conditions (like close to the engines)

• The new developments must be affordable (only moderate cost allow market penetration)

• The introduction of energy efficient and safe transportation must be supported by the governments by regulations and by public procurement.

 

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Timeframe

Note: Research/Prototyping/Deployment means for mass production. Some of these options are partially available in high end cars, but their social benefits will be effective only if they can be extended to the majority of cars. Synergies with other SPs Possible synergy areas with other priorities are (not exhaustive): • Basic power and power management technology will also find use in the Sub-Programme

“Energy and Environment”.

• Safe design methodology, and Design for Reliability can profit from the results of the priority Sub-programme “Design Methods and Tools”

• Heterogeneous Integration in Si process and integration will profit from the results of the priority “Assembling technology for system-in-package” in the Sub-Programme “Equipment and Materials”, even if it will require a dedicated effort for temperature control and heat management.

2010 2015 2020 2025

Speed control;, brake assistance, adaptive lighting, lane control

Car radar and optical, night vision, car-to-car/car-to-road communication, obstacle recognition

Advanced combustion engines, exhaust control, fuel adaptive engines

Hybrid car engine management, energy storage control, power management

Full electric car, battery power management, fast recharging, engine integration in wheels

Research Prototyping Deployment

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In-car sensors for weather, road conditions, chassis, tyres, lighting – wire-line

Infrastructure sensors, infrastructure-to-car, car-to-car communications

20102010 20152015 20202020 20252025

Speed control;, brake assistance, adaptive lighting, lane control

Car radar and optical, night vision, car-to-car/car-to-road communication, obstacle recognition

Advanced combustion engines, exhaust control, fuel adaptive engines

Hybrid car engine management, energy storage control, power management

Full electric car, battery power management, fast recharging, engine integration in wheels

Research Prototyping Deployment

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In-car sensors for weather, road conditions, chassis, tyres, lighting – wire-line

Infrastructure sensors, infrastructure-to-car, car-to-car communications

 

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Wireless Communications Introduction: Driving Forces in Wireless Communication We are now in a highly moving world where mobility, connectivity and data processing are ubiquitous. The strong position of Europe today in wireless communications needs to be reinforcing in the future to guarantee its competitiveness and make sure the industry based on nanotechnology, and all the Value Chain relying on it, will remain a substantial source of value and employment. On top of this, emergence of new challenges such as global warming, energy saving, population aging, will need more and more nanotechnologies to address these issues efficiently. The strong need for “Machine to Machine” communication (M2M) as well as the “Internet of Things” ranging from actuators, sensors to controllers makes wireless communications and nanotechnologies key technology assets to master.

The wireless communication paradigm is expanding far beyond the pure voice communication systems in becoming multimedia bringing audio, video, data in the picture. The pervasion of wireless communication beyond telecommunication is now a reality, which needs to be taken into account. This has a strong effect of making system definition and development extremely complex as more conflicting parameters have to be very carefully managed, making trade off much more difficult than ever. The connectivity and the number of new devices, on top of standards PC’s, now accessing internet with a wireless link brings as well another dimension in

complexity. The large amount of data, and the various types of data with very different levels of confidentiality that can now be stored or exchange with a mobile device makes consistency, confidentiality and authentication among the major issues that security technologies have to address. The Silicon technology evolution and the progress in embedded SW technology are the cornerstones for the development of mobile terminals adequate for these application domains. Regarding silicon technology, either on the “more Moore” (32nm, 22nm, etc silicon process) or in the “more than Moore” direction” (3D Integration, etc) new areas of investigation in term of architecture and products design open. Likewise, for what concerns embedded SW components, low footprint, high performance, and low power, trust-worthy SW blocks are becoming a necessity. Based on the outcomes of a document issued by a core group of partners and in line with the recommendations expressed by the Public Authorities, the Core Group proposes three Grand collaborative Challenges requesting a long range planning effort and close cooperation along the whole Value Chain. The objective is to spur development of innovative and cost effective technologies enabling designing and manufacturing in high volume silicon systems solutions for the wireless communication market.

 

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The three Grand Challenges are:

1. Front End & Back End heterogeneous 3D integration Platform 2. Technologies for “Green” Wireless Communication: 3. Adaptive radio

1. Front End & Back End heterogeneous 3D integration Platform:

Objective: Enable the development of Materials, design tools and design methodology, Manufacturing equipments and manufacturing process for Heterogeneous integrations.

a) Heterogeneous technologies integration The integration of functions, e.g. sensing, storing, processing, actuation, communication and energy scavenging is one of the most promising techniques for smart Microsystems in volume applications with huge economical and social impact. But the heterogeneous integration, the multiple integration of a variety of technological options is one of the biggest challenges semiconductor industry is facing today.

Novel tuneable metamaterial-based phase-shifter structures utilizing active circuits are another innovative forward-looking building block for heterogeneous integration. MEMS in combination of switches, varactors and resonators with active building blocks are another one. The integration of tuneable pre-select and post-select filters providing high Q and simultaneously tuning over a wide range e.g. for reconfigurable radios is another challenge. Another example is Ultra Wide Band Radar as high-resolution short range sensing technique with a variety of application fields like alerting or non-contact measurement of human body attributes. The

study of antenna designs suitable for heterogeneous module integration is another important aspect. The integration of very heterogeneous blocks of IP makes interconnection issues very critical In terms of power consumption, frequency limitation, signal integrity and thermal management. In this perspective three-dimensional (3D) approaches addressing materials issues and processes solutions including measurement and test have to be developed in close collaboration with the equipment makers.

 

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b) Design Methodology and tools

All the new technologies needed to address issues related to the design of modern wireless communication systems have a strong impact on design methodology and tooling. Globally the

trends in “more Moore” and in “more than Moore” have the effect of coupling domains in term of complexity which were almost disjoints before. For instance moving to 3D packaging techniques tightly link together thermal management system/die partitioning, power management, performance management and hardware/software partitioning. The benefit brought by such technology in term of flexibility has to be supported by the tooling in allowing deep investigation of the new architectural space. For example, these new technologies allow the cohabitation and co-existence of digital and RF parts, the integration of power amplifiers and of RF MEMs.

It is expected that in the near future embedded passives will be part of the landscape. In any case, more than ever, in order to design a coherent system, the level of abstraction has to be raised in order to guarantee a match between productivity of available design resources and system complexity. The evolution foreseen in the memory domain, interconnection area and packaging technology will open new opportunities in term of architecture. In order to take benefit of this it is important that CAD tools allow efficient investigation of these new territories. On top of the large number of additional features needed to support new design techniques, EDA vendors will have as well to address the cost and business model issues attached with new technologies. The explosion of complexity in the design space is as well visible in the EDA space making needs for computing power even more crucial. In such conditions it will be important for EDA firms to think differently in providing their customers with solution optimizing computing resources through a better usage of existing hardware(cloud computing, GPU computing,) in order to avoid skyrocketing IT costs at their customer sites. As a result of the analysis of this grand challenge, the two following areas appear as a primary importance for fostering stronger position of the European industry in designing and manufacturing silicon systems solution for the wireless communication market: • Processes manufacturing for

heterogeneous/3D integration

• CAD -Tools methodology/partitioning for heterogeneous/3D integration

The expected impact is to position Europe as a major player in the design and production of complex silicon systems. This objective will be achieved by placing a priority on the integration technologies of the future, and by encouraging intensive collaborations between ICs industry, CAD tools vendors and equipments makers .In addition, by intensifying the research efforts and by

 

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involving all the players throughout the Value Chain, it will be possible to spur the development of innovative silicon solutions and to strengthen the position of European firms in the global market. This 3D initiative will also be instrumental to keep and foster on the European soil advanced manufacturing facilities.

2. Technologies for “Green” Wireless Communication: The convergence scenario of consumer, computer and communication electronic systems requires an exponential growth of code and data in all electronic systems. This is because more communication protocols should be supported by a single device, more multimedia operations should be executed in the embedded processors, more bandwidth should be allocated to wired/wireless communication channels, more security checks should be performed on the fly, etc. The paradox is that in order to cope with a green policy, the required power dissipation for operating these devices should feature a sub-linear dependence on their complexity, or in other words, the number of operations to be executed per Joule should increase. In order to attain this target, a holistic approach is required and three R&D priorities are essential:

a) System power profiling At system level, well before the realization of the platform, the power consumption profile of the elementary HW and SW components should be estimated and the system architecture should be fine-tuned in order to make the very best balance between performance and power consumption. The Si process to be used for implementing the HW components should be compatible with lower power supply voltages and should feature reduced leakage currents. The design flow should support well-known power saving techniques. To some extend, the introduction of asynchronous features should be also supported. The firmware should be of reduced power and the SW development environment should allow the comparison of SW components in terms of power consumption and performance (power aware SW).

b) Ultra Low power technologies Because of power consumption, and flexibility, size and cost, the next generations of wireless systems will require new technologies and architectures that combine adaptability and performances in a novel way. Technologies to be developed have to cope with the never-ending list of new functions to be embedded in a mobile .The only mandatory limitations are the decrease of the cost per function and the consumption per function. For the digital parts the requirements will still be the increase in density and speed but with a decrease of power consumption. High-k metal gate (HKMG) Technologies will certainly be the best choice further pushing down MOS gate length to 20 nm and lower and to produce high-speed signal processing with very low power consumption. HKMG technologies will be instrumental to extend battery life for the new generations of handset devices. The other key active elements at the forefront of microelectronics end product functionality are the memory chips. This is true for cell phone handsets, broadband devices, and networking. The memory system, with his implications in terms of densities, technology performance, packaging and interfacing, becomes more and more of interest in order to improve the overall electronic system performance. At high-level “convergent” electronic system performance are measured in term of bandwidth, to speed up Internet connection, and power consumption reduction, to enhance the nomadic use. Improvement of Non-volatility solid state is the best way to reduce power consumption.  

 

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c) Energy Harvesting This holistic approach would be of reduced efficiency without the proper management of the battery system. It is expected that energy harvesting will enhance substantially the autonomy of handheld communication devices and will make them much friendlier to the environment. In fact the emerging of more and more wireless autonomous devices will require a lot of improvement in power consumption but as well in energy scavenging and energy storage technology. For examples, RF, thermal or vibration energy harvesting could be an option. This will be strongly reinforced by the various environmental regulations on going about energy management that devices will have to be compliant with, in order to efficiently address the global warming problem. Topics to be addressed: • System power profiling

• More Bits per Joule

• Low leakage process

• Ultra low power design techniques

• Power aware SW

• Energy harvesting.

Adaptive radio Objective: to demonstrate the feasibility single chip cognitive baseband and Application Processor ICs. Co-habitation in a single package of a baseband and Application Processor IC with the RF/IF stage, LNAs, Power Amplifiers, and SAW filters, Antenna Switch and the Antenna via a 3D integration scheme. The next generations of wireless communication systems will be able to communicate with various heterogeneous systems, in this perspective cognitive radio architectures have to be implemented for both RF front end and digital baseband.

a) RF Front end In the past 10 years the wireless connectivity has really exploded as devices are now connected to a large number of systems and networks with very different properties. The main driving factors in this domain are the mobility, continuity/quality of service and the data exchanged Convergence requires that connectivity links developed, targeting originally fixed or pedestrian terminals (802.11 a/b/g W-LAN), can be extended to mobility, e.g. 802.11p Wireless Access in Vehicular Environment. The increased demand for data traffic, for file transfer or Internet application, is driving the need for high data rate, high spectral efficient and low power connectivity. Latest Connectivity technology is moving toward the exploitation of new spectrum region, in the range of mmWave (i.e. across 60GHz), as recently addressed in IEEE 802.11ad or other consortia (Wireless HD, …) with the challenge to develop RF components capable to handle 2GHz bandwidth that could be allocated to each single link. Further consolidated trend is the adoption of Multiple Antennas

NFC

GSM

DVB-H

WLAN

Bluetooth

UWB

GPS

All- Communicating

 

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Transmitting and Receiving (MIMO) with the aim of increasing robustness and or throughput of the link such as recently addressed by IEEE W-LAN 802.11n. The number of antennas or transmitting/receiving nodes in a mobile device is already very important like cellular network, WLAN, GPS, Blue tooth, FM Radio, mobile TV, High data rates are also addressed by wired in house connectivity links as Power Line communications, the next generation addressing from 200MBit/s up to 1GBit/s for Multimedia contents distribution. Due to the number of interfaces to integrate in a low volume device, the RF problem is becoming a real headache in mobile systems. The increasing data throughput linked to multimedia and Internet browsing is making the situation even worst. New solutions are absolutely needed. SDR (Software Defined Radio) are very important, as it is a way to manage diversity in term of radio interfaces while maximizing hardware and software resources. It is also an interesting solution to cope with not yet fully stable standards or standards variants for specific markets. The emergence of new wireless devices on top of mobile phone makes mandatory a better utilization of radio spectrum. This means that wireless devices have to be aware of their environment in order to use at best available resources. Cognitive radios techniques are then crucial, as it is a way to sense the environment and to optimize the quality of service parameters in a crowdie RF spectrum. The increasing complexity of radio sub systems makes their manufacturing very tricky. In order to keep acceptable figures in term of performance and cost, it is mandatory to have systems capable to compensate imperfect radio interface in order to maximize manufacturing yields. Topics to be addressed: • Wireless sensors

• MIMO 802.11n, 802.16

• 802.11ad/WirelessHD mmWave technology for high bit-rate communication (multiple Gbps)

• 802.11p Wireless Access in Vehicular Environment (WAVE)

• HSPA, LTE, LTE Advanced

• Seamless transition between radio’s

• Multiple wireless interfaces in UICC cards or modules (Zigbee, UWB etc.)

• Base stations (BTS,BSC)

b) Digital baseband

Towards cognitive radio the digital baseband processing of such an extremely agile system is a highly challenging task. In fact agility is a key factor in a rapid moving world and more especially in wireless communication. If agility starts to be understood in software or hardware development methodologies, it needs a strong support at architecture level to be able to fully express its efficiency. The new technologies either in term of packaging or on the memory front for instance are adding much more capabilities to be agile. It must be possible to explore much more rapidly the architectural space independently of hardware/hardware portioning (3D integration,), hardware/software partitioning (trade off in power consumption, flexibility etc.) or software/software partitioning (heterogeneous multiprocessors systems etc.).

Modem

Camera

Camcorder

MP3 Phone

Web

Gaming

TV

Radio

GPS 

         All-achieving

 

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The new ways to develop hardware, through reconfigurable hardware or processors arrays to cope with the constraints brought by new silicon process nodes in addition to new memory technology in term of speed, power consumption and non volatility are opening new territories to architecture investigation and then agility. On the software side it is now mandatory to preserve as much as possible the software assets as their development cost is overtaking hardware development ones. To do so it is fundamental to reduce as much as possible hardware dependency for the software. All the techniques such as virtualization, late binding with dynamic compilation, components based design, constrained programming (power consumption, memory footprint, performance etc.), higher programming languages are potential solutions to this problem. The emergence of heavily multiprocessors based systems brings as well additional needs in term of tools, covering development, application parallelization, debugging, profiling, …To ensure Europe competitiveness in wireless communication, the following topics will need to be addressed in the scope of collaborative projects. Topics to be addressed: • Dynamic hardware, software partitioning

• Virtualization, Dynamic compilation

• Components based software re-use and associated specific description language

• Hardware and software re-configurability

• Multiprocessing

• “Evolutive” 3D architecture (at packaging level)

• Memories (speed, power, retention) – new kinds of volatile and non-volatile e.g. SSD PCM, MRAM

• External secure storage

c) Security

As part of the Cognitive radio challenge, a new security paradigm is requested by more and more communicating applications, more mobile users and more distributed data. Thus securing services or data and providing proper protection evidences is becoming increasingly important and difficult in advanced, open wireless and fully mobile devices. End-users, OEMs, ISVs, content owners, service providers and operators have different, sometimes diverging needs and should have differentiated privileges towards terminal resources. Robust stakeholders’ segregation, security policy enforcement and mutual assets isolation is a challenge in increasingly open “computing” devices exposed and vulnerable to everyday new malware, software and hardware attacks. Increasing interoperability, trust and flexibility requirements are bringing standardization and security evaluation challenges. Finally the ever-increasing security complexity should remain transparent to the end-user, which is stressing the security performance and efficiency dimensions. Addressing these security challenges involves:

• Open trusted platforms, with flexible secure boot, securing run time integrity. Logic security plus highly secure peripherals such secure smart cards. Trusted execution environments in hardware and software with trust zone for application processors. Secure access to I/O facilities including radio links

 

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• Identification and authentication

• Secure storage, file system encryption

• Adaptable security features, flexible enough to allow new counter measures and algorithms deployed over time. Multi-factor attack management and prevention

• Incremental certification, software quality measures, formal tools for security and embedded SW test verification

 

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Energy Efficiency

Introduction The Grand Challenges of this Sub-programme serve both today’s certainly most important overarching theme “Environment”. We have indentified two grand challenges, one of them is “CO2-reduction” – a rather general target, which concerns the Automotive, the Industrial, the Lighting and the Mobile Communication sectors. The other grand challenge is the “Smart energy grid”, targeting mainly topics around energy distribution. Generally, the priorities of this sub-programme are reduction of power consumption and very effective ways of power generation and distribution. Advanced Nanoelectronics devices, especially sensor networks could give an important contribution to the monitoring of environmental parameters and to the control of pollution, and much more.

Relevance for Europe Market value Coming from 3.1 million GWh in 2003, Europe will need in 2020, electrical energy of about 3.6 million GWh according to a study by IEA (International Energy Association). By using intelligent, innovative electronic components and systems, 0.7 million GWh can be saved, thereby helping the energy policy and industry competitiveness in Europe significantly. A few examples for the energy saving potential in different applications are: • Lighting - potential savings 22%

• Drive System - potential savings 18%

• Power Supply - potential savings 20%

The World market for power semiconductors is in the range of 10–15 B€/year, not including the control market and also not including the replacement market for breakthrough technology for power-saving equipment. Market penetration is more or less guaranteed due to legal requirements and the evident demand by consumers for “Co2-reduced” products. In most of the addressed topics (industrial, lighting, control and management of energy), Europe has a #1 position. Social Benefits The impacts on the European society are multifarious and will affect all domains (private, industry and public). The goal is to protect the natural resources and the environment in Europe in a sustainable manner. The overall target is to prevent the waste of energy (and thereby the reduction of CO2-emission) by using obsolete equipment and carelessness. An efficient use of energy is the political, social and technical challenge of the next decade. Focusing on micro-/ Nanoelectronics approaches in particular the challenge to save electrical energy consumption in Europe in the range of more than 20% until 2020 is feasible. This will reduce CO2 emission in the same order of magnitude in order to achieve the Kyoto protocol targets and will limit the energy cost increase. The usage of efficient power supply and intelligent energy control in new products could save up to 30% of the power consumption by simultaneous increase of safety, functionality and convenience. The European microelectronic research and development sector is requested to provide innovative technologies as basis for new energy efficient products and intelligent power management. Through consequent and combined efforts at European level there is the historical opportunity to extend the technological leadership of the European industry in this field and to strengthening its competitiveness. This will also have an enormous impact on high-qualification jobs in Europe. Another important benefit for the European economics and welfare is the reduced dependence from foreign and from fossil energy sources.

 

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Grand Challenges The societal benefits as described above can be realised if technological innovations are introduced in those applications, where energy generation, transmission and consumption can be reduced without losing functionality, performance and comfort. There is a long list of “candidates”, from which the most relevant will be described shortly.

a) Power generation • In many cases, power generation – often from alternative sources – produces “raw”

energy in a form, which cannot be transmitted or used without conversion. Examples are non-continuous energy sources like wind-mills and like solar cells. Using old-fashioned electronics for rectifying, transforming or converting (AC/DC or DC/AC) the currents, only about half of the energy could be used. New components will partially be based on SOI technology.

• Recuperation of energy (energy scavenging) will play an increasing role.

b) Power transmission/distribution • An up to now totally underestimated potential for energy saving is the management and

distribution of (electrical) energy. The availability of European wide energy distribution networks is today only realised in case of problems producing large area “black-outs”. The challenge here is to bring intelligence into the power distribution system. The “smart energy grid” – being identified as one of the grand challenges – will combine management of incoming power, of distribution of power and of outgoing power.

• This could include also a network of (at this moment) un-used batteries of millions of electrical cars.

• The smart energy grid will only work, if it is not only a power-network, but at the same time a communication network, which contains security features, grid monitoring and payment features.

• For efficient energy transmission over long distances, very high voltage lines will be needed (e.g. 800 kV). Highly effective AC/DC/AC conversion will be needed for entry and exit of energy.

c) Power consumption – which is to a very high degree linked to the grand challenge “CO2 reduction” • The most visible example is lighting. Most of the actual illumination systems have a

rather limited conversion rate from electrical power to light power; large parts still are converted into heat. There is a huge potential for energy saving in the private domain, in industry and in the public domain.

• Another type of applications, which has still a very large potential for energy saving is the conversion of electrical power into movement, be it in industrial machines, in cars or in motors as used in private households, like in washing machines, motors for pumps etc.

• The third large energy consumer is the “in-situ” supply and conversion of electrical energy. Examples are power supplies as used for portable computers and mobile phones and stand-by switches for TV, recorders and computers.

 

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• Also the electronic equipment itself still uses many components, which are only optimized with respect to performance and price, but not to energy saving.

• Medical applications are a still relative new and small field, but they depend very much on very good energy efficiency - guaranteeing a long lifetime and low weight for the portable units. Improved energy management is also key for cost-effective imaging systems in medicine.

d) Technological requirements: • Innovative systems and architectures for power electronics in order to optimize the

coefficient of efficiency. These technology challenges on system level refer directly to the first three described consumer-applications: controlled drives, lighting and intelligent power supplies and stand-by management.

• Heterogeneous system integration technologies for high power modules and System-in-package technologies taking into account highest currents, voltages, temperature as well as ESD, EMC and robustness aspects (from high power module to high power system in package - SiP). The challenge here is to make the power electronic devices useable for industrial applications and/or for applications under harsh conditions like in transportation (e.g. at the engine of a car or a high-speed train)

• Completely new or improved semiconductor technologies, using leading edge technology knowledge for low power consumption and extended lifetime (e.g. high-frequent and low-loss switching, digital power conversion)

• New semiconductor materials, such as SiC or GaN, and device architectures, thin substrates and interconnect materials to improve performance and reduce cost

• All new devices have to be robust and reliable – also under harsh conditions

Conclusion Conditions for success Regarding the technological competences and market positions, Europe has very good chances for becoming leader in the domain of (Nanoelectronics for) Energy Efficiency. However, there is still a huge need for specific R&D work, which will represent thousands of person-years and hundreds of M€ per year. In addition to the described specific technological innovations, a few very general points shall be mentioned: • Effective energy management needs European wide (or even world-wide) standardisation and

interfaces

• It also needs a very high degree of data security (e.g. for payment features)

• It must be affordable (only moderate cost allow market penetration

• The introduction of energy efficient goods must be supported by the governments by regulations and by public procurement.

 

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Timeframe

Synergies with other SP Possible synergy areas with other priorities are (not exhaustive): • Basic power and power management technology will also find use in the Sub-programme:

“Automotive and Transport”.

• New materials, which allow tailored power parameters for power switches will also be evaluated in the Sub-programme “Equipment, Materials and Manufacturing”.

• Low power devices, very often being used in safety or health relevant applications, will need specific design methodology and Design for Reliability” as developed in Sub-Programme “Design Methods and Tools”

• Failure analysis and reliability procedures related to high temperature, high current/voltage operation will also be an issue for Sub-programme: “Automotive and Transport”

2010 2015 2020 2025

Research Prototyping Deployment

2010 2015 2020 2025

Tran

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efficient power supplies , AC/DC & DC/DC converter, switching power supplies, intelligent stand-by

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regenerative energy (solar, wind, water) , energy recuperation

digital power conversion

energy distribution and transformation systems

daylight linked dimming systems, solid-state lighting devices, HID lamps

smart power management for industrial, consumer, medical appliances

intelligent drive control, intelligent switches and plugs, stand-by solutions

20102010 20152015 20202020 20252025

Research Prototyping Deployment

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efficient power supplies , AC/DC & DC/DC converter, switching power supplies, intelligent stand-by

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regenerative energy (solar, wind, water) , energy recuperation

digital power conversion

energy distribution and transformation systems

daylight linked dimming systems, solid-state lighting devices, HID lamps

smart power management for industrial, consumer, medical appliances

intelligent drive control, intelligent switches and plugs, stand-by solutions

 

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Design Methods and Tools

Introduction Design is the key link between technology and the world of applications, but design capabilities and design cost are also seen as limiting factors for the future technological development. ITRS roadmap is evidencing the increasing gap between the technological transistor density at a given technology node and the practical density achieved by design. An enormous increase of design productivity is necessary to exploit the whole potential provided by the new attractive technologies. In addition, due to the growing difficulty to maintain the pace of progress in performance and area for future technology nodes the profitability of new products is more and more depending on the progress of design and EDA tools. Moreover specific high tech sectors, which are among the strong point of Europe, like Automotive, Telecom and Security, are increasingly requiring specific performances, like reliability, low power consumption and immunity to tampering that can be achieved only through a tight integration between design and technology. The impact of increasing costs of design on device development with new technology generations is clearly shown by the decreasing number of new product start at each technology node. The improvement of design efficiency, the reduction in the cost of design, and the improvement of design quality are important.

 

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Innovations in Nanoelectronics are driven by the leading edge companies, accompanied by high investments in new technologies. Due to the very high benefit for the fast/slow industrial followers which use these technologies and thus for the whole society the support by public funding is more than adequate. Economic Impact The largest economical impact of design efficiency is on chip area, cost of design and especially time-to-market. Price drop for semiconductor devices is in the order of 27%/year. A delay of a few months in designing a new product can have a significant impact in profit margins. There is no clear data about the weight of design resources spent in Europe. Some information can be deduced from the existing data on the market of EDA tools. Total sales (licenses plus assistance) for EDA tools in Europe was around 1 B$ in 2007. Assuming an average investment of 20-25K$ per designer, it gives a total of 40-50 thousand IC designers in Europe, distributed between semiconductor companies, fabless design houses and IP providers, and system companies. With a ratio 1:3 between EDA tool investment and other costs (salary plus design hardware), we can assume that total investment in design by European companies has been around 3.5-4 B$, or 2.5- 2.8 B€ in 2007, which represents an investment of more than 10% of the sales of European semiconductor industry. The role of SMEs in the sector is important, both as pure design houses and IP providers, and as developer of design tools for specific requirements of European industry. Even if the most successful ones are afterward incorporated into the major leading companies, they can be considered to have successfully achieved two objectives: transfer of university know-how into industrial applications, and coverage of the specific needs of European industry. Driving Forces and New Landscape Design gap As discussed above increasing device complexity, and the need to compensate for parasitic effects related to the nanometre scale are increasing the gap between technology potential and design capability. Improvement in design methods and tools is required to take full profit from the huge investment in technology development. Diversification by design With the increasing trend towards standardization of basic CMOS technology, and the business model based on fab-less or fab-lite product companies supported by Silicon foundries, design becomes the main differentiating factor. Tools and methods must be developed to adapt standard

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technologies to specific applications, implementing reliability and manufacturability requirements by design. Role of heterogeneous integration The inclusion of new functions on top of the basic logic and memory functions, like analogue, RF, power, sensing and optoelectronics, and their integration in one package, is adding a novel degree of complexity. Not only design tools are needed to model and simulate properly these functions and even more challenging the reliability of the whole system, but also their integration with control and communication logic requires tools to support the proper system partitioning at high level. State-of-the-Art ITRS 2007 distinguishes two basic types of complexity—silicon complexity and system complexity—that follow from roadmaps for ITRS manufacturing technologies. • System complexity refers to exponentially increasing transistor counts enabled by smaller

feature sizes and to forms of diversity that arise with respect to system-level SOC or SiP integration. Heterogeneous integration is adding a new layer of physical complexity, introducing devices with novel physical properties. Design specification and validation become extremely challenging, particularly with respect to complex operating contexts. As design verification needs up to 80% of the whole design time, a strong improvement in verification methodologies and tools is needed to significantly reduce the verification time as well as the undetected design errors which lead to redesigns (design cost) or even more severe to misbehaviour in use (product quality).

• Silicon complexity refers to the impact of process scaling and the introduction of new materials or device/interconnect architectures. Many previously ignorable phenomena now have great impact on design correctness and value, such as non-ideal scaling of device parasitics, coupled high-frequency devices and interconnects manufacturing variability, process variability and decreased reliability.

European high tech industry has a strong position in the fields of Automotive and Aerospace, Mobile Communications, Security and Industrial, while promising areas, strongly dependent however from Public Procurement for the creation of markets, are in the field of Health, Ambient Assisted Living and Energy Efficiency.

All these segments have strongly specific requirement that require the integration of logic with other functions, like RF or optoelectronic links, power devices, sensors and analogue interfaces. Most of them have also severe reliability and power efficiency requirements.

Therefore 3 “grand challenges” have been identified for research on Design Methods and Tools. For each grand challenge specific research topics have been indicated. These topics need to be addressed in the Application Work Programmes in the next years, with the aim to develop integrated solutions to the grand challenge. Different competences need to be activated at European level, both in the industrial and in the academic world. It is expected that a rational combination of 1-2 projects/year per topic will allow developing integrated solutions, while keeping cost and number of partners within manageable limits. Topics for first year calls have been evidenced in bold.

 

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Grand Challenges Design efficiency for functional complexity The main target is to organize tools and methodology in order to improve the efficiency of design of the complex devices needed for critical applications, often requiring the integration of heterogeneous logic components (microprocessor cores, DSP, memories, dedicated logic) and heterogeneous functions (RF, analogue, power) on chip or in package. Key topics are:

a) Tools for Architecture Exploration and Optimization of Heterogeneous Systems

b) Behavioral models for high level design of heterogeneous functions.

c) Design environment for New Heterogeneous and Homogeneous Architectures and 3-D integration

d) Hardware-software partitioning and verification.

e) Tools for mixed analogue/digital/RF linked to system simulation, including SiP integration

f) Tools for package-IC co-design, multi-chip and 3-D integration, PCB-interfaces, including thermal and mechanical effects.

g) Design environment for constraint driven design for specific applications.

h) Deterministic verification methodologies/tools

Reliability and yield by design Applications in the field of Automotive and Aerospace, Security and Health require very high levels of reliability, often for limited production volumes. At the same time, integration of different functions and increasing weight of parasitic effects and new emerging types of production defects are introducing new causes of malfunctioning that require dedicated new DFT (Design-for-Test) measures for effective detection and screening.. Moreover the possibility to finely tune the process is decreasing with the use of foundries. Therefore testability, reliability and yield must be inserted by design. Main topics are:

a) Electromagnetic Compatibility and Signal integrity

b) Modeling of reliability effects (aging, soft errors, electro-migration, Electrostatic Damage, Electromagnetic coupling, temperature and hot spots, substrate noise)

c) Robust system design, including reconfigurability, redundancy and ECC

d) Yield optimization through statistical design, layout processing, yield-learning DFT – incl. design for diagnosis – to enable product based statistical yield-learning.

e) Advanced DFT, especially for analogue/mixed signal and System Level BIST (Built in self-test), in order to cope with increasing production test costs. (Depending on the application production test costs account for up to half of the manufacturing costs to achieve the requested high reliability for e.g. automotive devices).

f) Verification driven design

 

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Energy efficient design Energy efficiency is one of the most critical aspects of today’s information society. Electronic technologies can play a fundamental role in contributing to energy savings in different domains (see the ENIAC SP on “energy efficiency”). For instance, the introduction of electronic controls, associated with distributed networks of sensors can significantly increase the efficiency of energy utilization. The most impressive example is perhaps the success of automotive industry in reducing the fuel consumption by kilometre, even in the presence of increased car weight. But, as shown in SP2, the further reduction of energy consumption is one of the most important and challenging topics for Automotive Electronics Design and thus for EDA in the short and long term future. Especially e-Mobility requires a lot of innovative solutions. However semiconductor devices themselves are a source of power consumption that can be dramatically felt in battery powered devices for communications and health, but is impacting also critical components of the information society, like servers and data-centres. Reducing energy consumption of electronic devices, circuits and systems, paired to improving energy generation, conversion, storage and management capabilities represent the biggest challenges that engineers and scientists operating in the electronics sector will have to face in the next decade. Solid-state devices, as well as the integrated circuits and systems based on such devices, will have a central role in all steps of the energy production and management pipeline. Therefore, adequate design automation support, offering robust and accurate modelling capabilities and computer-aided design exploration/optimization solutions is needed to avoid that the complexity of the circuits and systems to be handled would make the design process too slow, error-prone and expensive. The main themes to be addressed in the “design methodology” SP include:

• Energy modelling and estimation at different abstraction levels for heterogeneous technologies

• Dynamic and static energy management for heterogeneous systems

• Thermal and variation-aware design under tight energy constraints

Conclusion

R&D Investments In order to have a real impact on European semiconductor industry and on the related application segments, large scale project are needed that can effectively integrated the design methods and tools with the need the system companies that are manufacturing the applications. A project scale of around 200-400 man-year is needed in order to put together research capability in academia with design experience in semiconductor companies and the requirements of system houses. As an order of magnitude it can be given that the present investment in existing design tools in Europe is already in the order of 1B$, while the total investment in design is probably 3-4 times as much. Assuming a 10% funding for research would require around 200-250 million Euro/year. The present economic crisis is making the need of investing in design efficiency even more urgent: • Only those companies that are able to put new products on the market and to renew radically

their product portfolio will survive the crisis.

• Investment in design tools and methodologies are more modular then investment in technology;

 

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• They put more emphasis on the manpower side than on pure equipment side

• They create a know-how base, strictly connected to design community that can hardly be transferred elsewhere.

Assigning a relative weight to the above grand challenges is difficult. However the partitioning of present investment in EDA tools, reported below, can give an idea of where design efforts are concentrated in Europe. The IP tools and VHDL areas correspond to design efficiency and power efficiency, while the PCB/MCM is related to diversification, and the physical design tools are more related to reliability and yield and analogue design. Timeframe The priorities were assigned taking into account also the presence of already running projects under EUREKA or FP7.

VHDL42%

PCB/MCM13%

Physical21%

IP & tools15%

Services9%

 

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Synergies with other SPs Possible synergy areas with other priorities are (not exhaustive): • Safe design methodology, and Design for Reliability can find synergy with application projects

in “Automotive and Transport”.

• Low power devices, very often being used in safety or health relevant applications, will enable application in “Energy Efficiency” and “Wireless Communications”

• Failure analysis and reliability procedures related to high temperature, high current/voltage operation will also be an issue for Sub-programme: “Automotive and Transport” and “Energy Efficiency”

• Design tools for 3-D and heterogeneous integration will used for applications in Wireless Communication” and “Automotive and Transport”

• Verification-driven design will find application especially for “Automotive and Transport”

• Modelling of reliability effects will require a tight cooperation with “Silicon Processes and Integration”

20102010 20152015 20202020 20252025

Energy modeling at different levels , thermal aware design, dynamic and static energy management

Research Prototyping Deployment

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Modeling of reliability effects, EMC and Signal integrity,fFault tolerant design

Advanced DFT, especially for analogue/mixed signal, statistical design, yield-learning DFT

Verification driven design, verification speed matching complexity, full coverage vs. specifications

High level behavioral models, tools for architecture exploration of heterogeneous systems

Tools for mixed analogue/digital/RF, tools for package-IC co-design, multi-chip and 3-D integration

Environment for constraint driven design, environment for heterogeneous architectures and 3-D

 

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Silicon Process and Integration Introduction A significant part of the success of the semiconductor industry in the past decades is due to the fact that generic silicon technologies are used throughout a wide range of applications and that the associated R&D cost can be shared among many different markets. It does translate into the fact that in most cases the silicon process development in Nanoelectronics is driven by pure technological progress and can’t be linked to a specific application domain. There is thus a need to identify the R&D on generic silicon process and process integration as a cross-cutting priority: this programme will allow the appropriation by Europe of generic Si processes which will not only allow progress in terms of cost, scaling, power / energy consumption and functionality, but also serve as key enablers for major European lead markets and societal challenges. Without this appropriation many societal issues can’t and will not be addressed. It is now of common use to classify these enabling silicon technologies in three categories: • “More Moore” (MM) for digital data processing and storage (which represents more than 70%

of the turnover of the IC industry worldwide, i.e. 180B$ in 2008)

• “More-than-Moore” (MtM) for interfacing with the outside world and managing the energy / power consumption of the electronic system (which stands for 15 – 25% of the microelectronics)

• “Heterogeneous Integration” (HI) for bringing chips together in a single package (the associated cost accounts for 5 – 25 percent of the total cost of a complete semiconductor product)

• It is only by combining and mastering these three domains that the European Nanoelectronics industry can offer competitive system solutions addressing the European needs.

More Moorescaling

more Tr/mm²

More-than-Moorediversification

more functionality

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diversificationmore functions/mm3

Overarching challenge:generic process platforms for

more functions / volume at affordable cost

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Grand Challenges Grand Challenge 1 – “More Moore” technologies Vision: Maintain through R&D leadership the ability of the European industry to drive the development and manufacturing of advanced CMOS Landscape and needs This is a domain where major changes are taking place worldwide and are accelerated by the present crisis. Advanced CMOS is the core technology for digital data processing. The evolution of this domain in Europe is characterized by opportunities which need to be capitalized upon and trends which should be addressed to benefit to Europe: • Early research in this area is increasingly done in a multi-partner, consortia-level structure,

because of cost and risk considerations (IMEC, Albany…). In addition, owing to the cost of developing the latest CMOS generation, some European companies which preserve in-house manufacturing capability in advanced CMOS execute the early R&D for these CMOS generations in clusters, such as the IBM cluster (one of the few major consortia worldwide developing the full CMOS process by gathering many US and non-US partners together). Still the preindustrial development and qualification are made in their European facilities: there is thus a need to support the CMOS R&D in Europe for accelerating the technology appropriation in Europe

• Some European companies are going fablite or fabless: for them there is a need to understand the next generation CMOS in order to specify according to their needs the technology nodes which will be implemented in foundries

• While most of the foundries of advanced CMOS are located in Asia one observes the emergence of a Western foundry producing in Europe: there is a new opportunity for Europe to compete with Asia in the foundry business

• Though it is not considered as a European strength in terms of product design, there is significant microprocessor production in Europe (Dublin & Dresden). However at each new technology generation there is a risk that more production moves outside of Europe: it is thus important to enhance the CMOS expertise to attract more production in Europe

• Best in class R&D centres are present in Europe which don’t exist elsewhere in the world: there is a need to maintain the viability and expertise of these R&D centres

• In geographical terms and contrary to other Nanoelectronics technology fields (see “More-than-Moore”) there are few leading regions / clusters in Europe where advanced CMOS technologies are developed. Owing to the cost and time needed to establish such excellence clusters, European programmes and calls should acknowledge this situation and encourage projects to form around the few excellence regions to benefit from the critical mass of expertise. The supply chain linked to these clusters will induce an efficient spill-over effect benefit other European regions.

• A transition to the 450mm platform is foreseen for advanced CMOS technologies at the 32hp / 22hp. Though the exact timing is a matter of debate, ITRS expects the R&D phase taking place in the 2010 – 2014+ timeframe, hence relevant to be included in an ENIAC strategic plan. Developed CMOS processes should be capable at 450mm to maintain Europe at the leading edge of CMOS R&D.

 

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• Advanced memories are critical components in most systems (communication, automotive, consumer…). The associated industrial landscape is evolving fast. It stands for 25% of overall semiconductor market, almost equally divided between DRAM and Flash and there is a strong trend for consolidation. Stand-alone DRAM industry disappeared from Europe, but innovative NVM companies are active in Europe. Furthermore embedded memories are critical parts in a CMOS chip. Europe has significant assets in this field through world-class R&D centres which don’t exist elsewhere in the world and a European company which is the only company on the market with next generation PCM memory.

• While conventional memory technology (Flash and DRAM) is reaching its physical limits in the next few years, there is an opportunity for Europe to take the leadership in disruptive changes in memory technologies. Furthermore memory solutions should take into consideration system constraints (e.g. system bandwidth, power / energy consumption, etc.) which impacts the memory technologies either as stand-alone or embedded components.

Implementation Considering that: • A technology push in “More Moore” technologies enables and drives high value-added

applications

• There is a need to maintain R&D and expertise in Europe to specify and access the latest CMOS and memory technologies

• A critical size is obtained at the European level through the cooperation of the few leading excellence clusters in Europe

• In US and Asia there is a strong involvement of PA’s for supporting this industry

• It is appropriate to propose a major Europe-wide public initiative on core CMOS and on advanced memories in support of a more comprehensive European industrial policy targeting microelectronics. In line with the pace of the technology generations expressed by the ITRS one should programme:

• One major project on core CMOS every 2 – 3 years with a typical size of more than 1,000 p.y.

• Few significant projects on disruptive memory technologies (embedded and/or standalone) every 1 – 2 years with a typical size of 400 p.y.

Expected benefit Innovations in electronics-enhanced systems and applications are enabled by mastering advanced CMOS and memory technologies: a strong European R&D programme on “More Moore” is a prerequisite to specify and access the latest technologies and thus secure further growth in European lead markets. Furthermore supporting this major industry segment will maintain and expand the Nanoelectronics supply chain existing in Europe. Finally progress in “More-than-Moore” is not independent of a strong expertise in “More Moore”: • Progress in MtM is mostly fuelled by the development of advanced “More Moore” processes

• Integrating MtM devices in advanced CMOS needs an in-depth knowledge of the development of the MM devices as the MtM “add-on” will strongly affect the performance of the core CMOS devices

 

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• Having a prescription power in the development of “More Moore” technologies and keeping an expertise in that field is the best guarantee for making “More-than-Moore” happening in Europe.

Grand Challenge 2 – “More-than-Moore” technologies Vision: Make Europe lead the worldwide R&D in “More-than-Moore” technologies Landscape and needs “More-than-Moore” is a domain initially proposed and conceptualized by Europe to stress the value and critical importance of non-digital functions in system solutions. It is not by chance that the ITRS didn’t formalize a “More-than-Moore” roadmap. In contrast to the development of generic digital CMOS and memories, “More-than-Moore” technologies are much diversified. Their performance metrics are multifold, they are often driven by dedicated application domains and the target markets operate through different business models and supply chains. It is thus more difficult to give a simple and unified view of the many and often disruptive “More-than-Moore” technologies which are likely to enable new applications and markets. Europe has key competitive advantages to address this field: • There is a historical synergy in Europe between system / application companies and

component suppliers (incl. SMEs)

• A strong R&D and manufacturing MtM base exist and is widely distributed all over Europe

• In terms of devices and underlying processes which pertain to the “More-than-Moore” field and which are generic to many applications,

• Sensors and actuators are central to the “More-than-Moore” domain, as an archetypal device for interfacing digital processing with the analogue outside world

• RF devices (including passives, RF interfaces, antennas…) enable wireless communications

• power / high voltage devices are key components in automotive and allow innovative solutions for better energy efficiency

• Imaging devices find pervasive applications not only in the consumer field, but also in diversified domains like safe driving or healthcare

• Biochips are likely to have a major impact in the healthcare and biomedical domains, but could also drive new applications in interfacing with the biological world (“wetware”)

• Many of these components rely on new materials, analogue / mixed signal devices (e.g. BiCMOS), passive devices, MEMS / NEMS or photonics on Si.

• Implementation

• To favour the European leadership in “More-than-Moore” many ingredients are needed:

• Generic technologies should be developed for a broad range of applications to leverage the high development cost and time

• Europe should capitalize on the synergy along the Value Chain

• PA’s (including Europe) have a significant responsibility in setting a favourable landscape for the development of a European “More-than-Moore” through:

 

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o Appropriate regulations

o Standards

o Lead market initiative and precompetitive public procurement etc.

Considering the great diversity of generic2 “More-than-Moore” technologies and the potential for innovative breakthrough many projects of a typical size of 250 p.y. should be targeted each year with a wide participation over Europe. Expected benefit By setting the pace of the “More-than-Moore” R&D worldwide Europe can expect the same benefit as US (and recently Asia) did in aligning the world R&D efforts in the “More Moore” domain. By maintaining the synergy between technology and applications all over Europe one can expect to develop new markets as we did in the past in the communication and automotive fields. Grand Challenge 3 – Technologies for “Heterogeneous Integration” Vision: develop an European SiP supply chain for innovative systems integrating advanced CMOS and European “More-than-Moore” Landscape and needs Integrated complex systems need more and more to combine in a single package high performance computing and information storage (“More Moore”) with dedicated devices (“More-than-Moore”) for interfaces and energy / power management. In many cases integrating on a single chip doesn’t bring any competitive advantage in terms of cost and size (e.g. integrating in a single die advanced CMOS having a high cost / mm² with large area sensors). Furthermore integrating heterogeneous part gives an added degree of flexibility in bringing new system solutions to the market and in adapting to evolving standards. Considering the complex interplay between IDM, fables companies and foundries, it is expected that for a given system solution components will be supplied from many sources, part of them outside of Europe, enhancing the need to find cost effective solutions to integrate heterogeneous technologies in a single package. There is a clear opportunity for Europe to develop a European SiP supply chain and take a significant leadership worldwide: • The supply chain of 3D/SiP is not firmly established yet worldwide

• Standards for SiP are underdeveloped

• There is a historical synergy in Europe between system / application companies and technology suppliers (incl. SMEs). As the technological solutions for heterogeneous integration will be driven by classes of applications a strong interaction between technology development and application domains is mandatory

• There are leading R&D centres in Europe

                                                            2 Dedicated processes and technologies addressing only one application domain will be developed in the corresponding application sub programmes of ENIAC or through other R&D programmes.

 

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Implementation In order to develop generic processes and 3D / SiP standards applicable to many applications domains, Europe should address many technologies in a holistic approach, including: • System-level co-design (*)3

• Advanced substrates (incl. embedded devices technologies, printable wiring also on organic substrates, thick copper power lines, etc.)

• Wafer-level integration

• Module integration

• 3D Integration (incl. TSV, thin wafer technologies, bonding, etc.)

• Interconnection (electrical, RF and/or optical) & interposers

• Assembly & packaging (incl. wafer dicing and encapsulation technologies)

• Test (incl. KGD)

• Thermal management

• EMC and reliability

Considering the potential for innovation in many application domains many projects of a typical size of 200 to 300 p.y. should be targeted each year with a wide participation over Europe. Expected benefit 3D/SiP heterogeneous integration is expected to act as a key differentiating factor of complex integrated systems: in mastering its supply chain Europe secure its future in many application domains. Classical assembly and packaging has moved mostly to the Far-East: by setting its leadership in the heterogeneous integration of complex systems Europe can regain a significant role in the worldwide “back-end” market. Finally heterogeneous integration can enhance the synergy between the European leadership on “More-than-Moore” and its expertise on “More Moore”.

Conclusion There is a strategic need for Europe to develop Si process and integration technologies at a precompetitive stage. Mastering the scaling of logic processes (i.e. “More Moore”) gives Europe the ability to steer the development and manufacturing of advanced CMOS worldwide according to its needs. Having a prescription power in the development of “More Moore” technologies and keeping an expertise in that field is also the best guarantee for making Europe leading “More-than-Moore” technologies. Finally there is an opportunity for Europe to develop a European SiP supply chain and take a significant leadership worldwide.

                                                            3 addressed in the chapter on “Design, methods and tools”

 

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Equipment, Materials and Manufacturing Introduction For semiconductor manufacturing, Europe has a long history of successful mechanical engineering, tailor made machinery, optical equipment, and chemical processing tools. In addition, operating supplies, raw materials, auxiliary materials and substrate materials were offered and developed in leading qualities. This history led to a world leading position in several areas, foremost in lithography, metrology and silicon substrates, but also in thermal processing, cleaning and wafer handling. A handicap for this industry is that the front end technology can not be developed with the European Semiconductor Manufacturers, since their business plans do not appear to be based on aggressive shrink roadmaps as the leading companies especially in Asia. However this handicap is largely compensated by the excellence of the process development capabilities at IMEC, LETI and Fraunhofer. Europe should never neglect its capability in the mainstream advanced CMOS, since it could bring this success story to an end. Mainstream CMOS technology is today somewhat a commodity, and the supply chain markets are solidified. Two fields of Grand Challenges The mission of the European Equipment, Materials, and Manufacturing (E&M) industry is to “Provide innovative and superior elements for semiconductor manufacturing”. To fulfill this mission also in the future, Grand Challenges in two fields need to be mastered. In Field 1 “Direct Impact”, the E&M products define a big, self-sustaining global market by themselves. In these global markets, the European E&M industry has achieved a world leading position, and acts as a powerful European engine for economic growth by itself which is underlined by the more than 100.000 individuals working in the European E&M industry today. The future challenges in this field of the E&M industry are so large by themselves that they require a multi-national and multi-lateral approach to be successfully mastered. In Field 2 “Strategic”, small and emerging E&M markets are addressed that exhibit a high leverage to European key industries, e.g. tailored E&M solutions that enable heterogeneous integration for automotive applications. Accordingly, a close interaction of the E&M industry with European chip manufacturers and institutes is required to develop E&M solutions that serve the semiconductor industry. The key role of public funding Public funding is a corner stone to fulfill the mission of the E&M industry also in the future with significant positive repercussions serving societal needs as described by the SEMIP acronym. In Field 1 “Direct Impact”, high upfront invests with a long term perspective and high risks are required. Big chances in the addressed large markets stand opposite. Public funding is indispensable to share the risks that cannot be taken by the E&M industry alone, and to realize the chances. Thus, public funding in this field generates and sustains highly qualified employment in European E&M industry. In addition, the global commercial exploitation of the European E&M developments allows Europe to acquire knowledge about various fields of world wide leading edge technology not accessible otherwise. Finally, the driving role of leading edge E&M developments for other companies, e.g. in the local supply chain, may lead to competitive advantages also there. In Field 2 “Strategic” public funding is an enabler for emerging applications that exhibit a big lever to European key industries. Funded collaboration of E&M industry with European chip manufacturers and institutes is a key factor for the success of these developments. In addition, a better competitiveness of the participants to such funded projects is achieved by the improved cooperation. Finally, also in Field 2, large upfront invests with high risk are required that cannot be taken by the E&M companies alone.

 

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Grand Challenges European Equipment, Materials, and Manufacturing faces 4 Grand Challenges in the coming years. Figure 1 names and groups these challenges in the two fields described above.

Figure 1. The 4 Grand challenges for the European Equipment, Materials, and Manufacturing. The following section describes each challenge more specifically by addressing technology, market impact, necessity for public funding, ENIAC, and its relation to SEMIP. Grand Challenge 1 – EUV and complementary 1Xnm patterning Vision: Realize EUV Lithography as the chip mass manufacturing technology of the next decade and complementary 1Xnm patterning technologies Technology: Extreme Ultra-Violet (EUV) lithography is anticipated to become the key enabler for More Moore chip mass manufacturing beginning at 22nm feature sizes (half-pitch). Major technology solutions need to be developed: a high throughput EUV machine including e.g. high power EUV sources, and optics for high quality imaging at 13.5nm wavelength; EUV infrastructure and metrology including mask fabrication processes, cleaning, inspection and review tools, sensitive resists, defect engineering and process control. Furthermore, the development of complementary 1Xnm patterning technologies as e.g. e-beam lithography is required for mask making, fast prototyping, and low-volume manufacturing. Commercial: EUV lithography addresses a large market with an estimated annual volume of ~3 Billion € in 2015. The upfront invests in EUV lithography exceed 1 Billion €. The substantial markets for the EUV infrastructure and complementary 1Xnm patterning technologies are additional. It is important to note that Europe’s leading role achieved in the 193nm immersion lithography can only be sustained by a successful introduction of EUV lithography. Funding Rationale: The high risk in the huge upfront invest and the long term perspective of realizing EUV lithography and infrastructure require public funding to realize the multi-billion € market potential over the next decade. Furthermore, the funding will allow Europe to gain in-depth knowledge about leading edge semiconductor manufacturing all over the world, and to create and sustain highly qualified employment in Europe. ENIAC: The development of EUV lithography and infrastructure, as well as the complementary 1Xnm patterning technologies are highly involved tasks that require competencies and focused collaboration of large firms, SMEs, and institutes from several European countries. Relation to SEMIP: industry, people (communication, digital content, employment)

 

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Grand Challenge 2 – 450mm supply chain Vision: Enter 450mm arena at an early stage to create new opportunities to increase the European world wide market share in this competitive domain Technology: Key technology target for the European companies and institutes is to develop and set common standards and strategies for 450mm Equipment, Materials, and Manufacturing. Important examples are 450mm substrates and SOI development, and the generation of an open platform for 450mm equipment. Commercial: 450mm E&M may become a dominant segment in the world wide E&M market of total annual volume of ~35 Billion €. Forefront R&D for 450mm creates new opportunities to increase the European market share in this competitive domain. Funding Rationale: Forefront 450mm R&D efforts are only paid back after a long time, and exhibit substantial risks which cannot be taken by the companies alone. Therefore, public funding is prerequisite to enter the 450mm arena at an early stage. ENIAC: To be able to set common standards increased cooperation across several European countries is a necessity which, in addition, enhances the overall competitiveness of European companies and institutes. Relation to SEMIP: industry, people (communication, digital content, employment)

Grand Challenge 3 –”More Moore” innovations Vision: Keep leading position of European E&M companies across the entire Value Chain Technology: “More Moore” innovations will address open issues in the fields of metrology, substrate, SOI, cleaning, deposition, structuring, and manufacturing efficiency in close collaboration of European E&M companies, institutes, and chip manufacturers. In particular, Semiconductor Equipment Assessment (SEA) projects would give a major boost to this programme. Commercial: Significant impact via offering tailored solutions for the European chip manufacturers. Funding Rationale: Public funding is required for the upfront invests with high risk which cannot be taken by E&M companies alone. Furthermore, a better competitiveness will be achieved by the improved cooperation between European E&M companies and chip manufacturers. ENIAC: A multi-national, multi-lateral collaboration with European chip manufacturers and institutes is key for the success of the Equipment, Materials, and Manufacturing developments. Relation to SEMIP: industry, people, mobility Grand Challenge 4 –”More than Moore” innovations Vision: Open new market opportunities for the European E&M industry for diversified technologies (e.g. power, sensors) Technology: “More than Moore” innovations will address open issues in the fields of metrology, substrate, SOI, cleaning, deposition, structuring, and manufacturing efficiency in close collaboration of European E&M companies, institutes, and chip manufacturers. A particular focus will be put on solutions for small volume manufacturing, and highly diversified processes and products. Commercial: Significant impact via tailored solutions for European chip manufacturers with high lever for European key industries as e.g. automotive and telecommunication. Funding Rationale: Funding for “More than Moore” innovations in the E&M industry will enable the development of tailored solutions for the European chip manufacturers that exhibit a large lever to European key industries. Furthermore, public funding is required for upfront invests with high risk which cannot be taken by E&M companies alone. ENIAC: A multi-national, multi-lateral collaboration with European chip manufacturers and institutes is most important for the success of the developments in this field of the Equipment, Materials, and Manufacturing industry. Relation to SEMIP: industry, people, mobility, (safety, environment)

 

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Conclusion Conditions for success Due to its profound competences in mechanical engineering, tailor made machinery, optical equipment, and chemical processing tools, and its world leading market position in several areas, Europe has excellent capabilities to become a leader in the world-wide E&M industry. To achieve this, a huge R&D effort worth several hundred million € has to be invested year by year to create the most advanced enabling solution for the Nanoelectronics industry. It must be pointed out that the E&M companies and institutes have to start these developments probably earlier than any other player in the Nanoelectronics industry. Hence, E&M companies and institutes have to take highest technology risks often many years before a first product reaches the market. This specific situation makes public funding a key success factor for the future of the European E&M industry.

 

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Executive Summary Microelectronics, now rapidly developing into the dimensions of Nanoelectronics, has become the bedrock of innovation in the vast majority of industrial and consumer products. Not only does it provide increasing capability in terms of product performance but it is also central to addressing critical societal issues. Electronics and related technology will form the basis of environmental engineering, medical innovation and other fundamental challenges facing Europe and its citizens. Micro/Nanoelectronics have become integral to life and work – and the trend is ever upward. In many of these fields, Europe has established a leading global position and it is inconceivable that Europe should not continue to play a major role in this area. However, this position must be maintained and continuously strengthened and in addition, core sectors, where we lack capability, must be developed to ensure that a critical mass of electronics competence is retained within European borders. Single companies cannot achieve this on their own. Cooperation is mandatory between large industrial partners, academia and SMEs, complemented by strong relationships with national authorities and the EU. Innovation is a core strength of Europe and mechanisms must be in place to discover, develop and exploit new thinking wherever it may arise. The ENIAC Joint Undertaking represents a new approach to addressing these requirements. This document seeks to map an approach that will see Europe take full advantage of the scientists and engineers working in Nanoelectronics and direct their efforts to selected R&D topics, which are needed to meet the identified key challenges Europe faces. This will help ensure we both maintain & extend our position in global technology and take full advantage of related commercial opportunities.