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1Motorola TMOS Power MOSFET Transistor Device Data

D e s i g n e r ' s D a t a S h e e t

T M O S E - F E T .

P o w e r F i e l d E f f e c t T r a n s i s t o r

NChannel EnhancementMode Silicon GateThis advanced highvoltage TMOS EFET is designed to

withstand high energy in the avalanche mode and switch efficiently.This new high energy device also offers a draintosource diodewith fast recovery time. Designed for high voltage, high speedswitching applications such as power supplies, PWM motorcontrols, and other inductive loads, the avalanche energy capabilityis specified to eliminate the guesswork in designs where inductiveloads are switched and offer additional safety margin againstunexpected voltage transients. Avalanche Energy Capability Specified at Elevated

Temperature Low Stored Gate Charge for Efficient Switching Internal SourcetoDrain Diode Designed to Replace External

Zener Transient Suppressor Absorbs High Energy in theAvalanche Mode

SourcetoDrain Diode Recovery Time Comparable toDiscrete Fast Recovery Diode

* See App. Note AN1327 Very Wide Input Voltage Range;Offline Flyback Switching Power Supply

MAXIMUM RATINGS (TC = 25 C unless otherwise noted)

Rating Symbol Value Unit

DrainSource Voltage V DSS 1200 Vdc

DrainGate Voltage (RGS

= 1.0 M ) VDGR

1200 Vdc

GateSource Voltage ContinuousGateSource Voltage NonRepetitive (t p 50 ms)

VGSVGSM

20 40

VdcVpk

Drain Current Continuous @ 25 CDrain Current Continuous @ 100 CDrain Current Single Pulse (t p 10 s)

IDID

IDM

3.02.211

Adc

Apk

Total Power DissipationDerate above 25 C

P D 1251.0

WattsW/ C

Operating and Storage Temperature Range T J , Tstg 55 to 150 C

UNCLAMPED DRAINTOSOURCE AVALANCHE CHARACTERISTICS (TJ t 150 C)

Single Pulse DraintoSource Avalanche Energy Starting T J = 25 C(VDD = 100 Vdc, V GS = 10 Vdc, PEAK I L = 4.5 Apk, L = 10 mH, R G = 25 )

EAS101

mJ

THERMAL CHARACTERISTICS

Thermal Resistance Junction to CaseThermal Resistance Junction to Ambient

RJCRJA

1.062.5

C/W

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds T L 260 C

EFET and Designers are trademarks of Motorola, Inc.TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

M O T O R O L A

SEMICONDUCTOR TECHNICAL DATAOrder this document

by MTP3N120E/D

Motorola, Inc. 1995

M T P 3 N 1 2 0 E

TMOS POWER FET3.0 AMPERES1200 VOLTS

RDS(on) = 5.0 OHM

Motorola Preferred Device

D

S

GCASE 221A06, Style 5

TO220AB

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2 Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS (TJ = 25 C unless otherwise noted)Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

DrainSource Breakdown Voltage(VGS = 0 Vdc, I D = 250 Adc)Temperature Coefficient (Positive)

V(BR)DSS1200

1.28

VdcmV/ C

Zero Gate Voltage Drain Current(VDS = 1200 Vdc, V GS = 0 Vdc)(V

DS= 1200 Vdc, V

GS= 0 Vdc, T

J= 125 C)

IDSS

10100

Adc

GateBody Leakage Current (V GS = 20 Vdc, V DS = 0 Vdc) I GSS 100 nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage(VDS = VGS , ID = 250 Adc)Temperature Coefficient (Negative)

VGS(th)2.0

3.07.1

4.0

VdcmV/ C

Static DrainSource OnResistance (V GS = 10 Vdc, I D = 1.5 Adc) R DS(on) 4.0 5.0 Ohm

DrainSource OnVoltage (V GS = 10 Vdc)(ID = 3.0 Adc)(ID = 1.5 Adc, T J = 125 C)

VDS(on)

18.015.8

Vdc

Forward Transconductance (V DS = 15 Vdc, I D = 1.5 Adc) g FS 2.5 3.1 mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

Ciss 2130 2980 pF

Output Capacitance (VDS = 25 Vdc, V GS = 0 Vdc,f = 1.0 MHz)

Coss 1710 2390

Reverse Transfer Capacitance.

Crss 932 1860

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

td(on) 13.6 30 ns

Rise Time (VDD = 600 Vdc, I D = 3.0 Adc,

tr 12.6 30

TurnOff Delay Time= ,

RG = 9.1 ) td(off) 35.8 70

Fall Time

tf 20.7 40

Gate Charge

QT 31 40 nC

(VDS = 600 Vdc, I D = 3.0 Adc,

Q1 8.0

VGS = 10 Vdc) Q2 11

Q3 14

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (IS = 3.0 Adc, V GS = 0 Vdc)(IS = 3.0 Adc, V GS = 0 Vdc, T J = 125 C)

VSD

0.800.65

1.0

Vdc

Reverse Recovery Time

trr 394 ns

(IS = 3.0 Adc, V GS = 0 Vdc,

ta 118 dIS /dt = 100 A/ s) tb 276

Reverse Recovery Stored Charge Q RR 2.11 C

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance(Measured from contact screw on tab to center of die)(Measured from the drain lead 0.25 from package to center of die)

LD

3.54.5

nH

Internal Source Inductance(Measured from the source lead 0.25 from package to source bond pad)

LS 7.5

(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%.(2) Switching characteristics are independent of operating junction temperature.

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TYPICAL ELECTRICAL CHARACTERISTICS

R D S ( o n ) ,

D R A I N

T O

S O U R C E R E S I S T A N C E

( N O R M A L I Z E D )

R D S ( o n ) ,

D R A I N

T O

S O U R C E R E S I S T A N C E ( O H M S )

R D S ( o n ) ,

D R A I N

T O

S O U R C E R E S I S T A N C E ( O H M S )

10,000

1,000

100

10

10 400 600 800 1000

2.5

2.0

1.5

1.0

0.5

0 50 25 0 25 50 75 100 125 150

5.4

5.0

4.6

4.2

3.8

ID, DRAIN CURRENT (AMPS)

8

6

4

00 2 4 6531

6

00 6 12 18 24 30

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

I D ,

D R A I N C U R R E N T ( A M P S )

I D ,

D R A I N C U R R E N T ( A M P S )

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Currentand Temperature

Figure 4. OnResistance versus Drain Currentand Gate Voltage

TJ, JUNCTION TEMPERATURE (C)

Figure 5. OnResistance Variation withTemperature


Figure 6. DrainToSource LeakageCurrent versus Voltage

I D S S ,

L E A K A G E ( n A )

0

TJ = 25C VGS = 10 V VDS 10 V

VGS = 10 V TJ = 100C

55C

TJ = 25C

VGS = 10 V

VGS = 0 V

5

4

3

2

6

5

4

3

2

1

3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2

0 2 4 6531

TJ = 125C

1

2

200

6 V

5 V

4 V

25C

TJ = 55C

100C

25C

VGS = 10 VID= 1.5 A

1200

100C

25C

15 V

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predictedby recognizing that the power MOSFET is charge controlled.The lengths of various switching intervals ( t) are deter-mined by how fast the FET input capacitance can be chargedby current from the generator.

The published capacitance data is difficult to use for calculat-ing rise and fall because draingate capacitance varies

greatly with applied voltage. Accordingly, gate charge data isused. In most cases, a satisfactory estimate of average inputcurrent (I G(AV) ) can be made from a rudimentary analysis ofthe drive circuit so that

t = Q/I G(AV)During the rise and fall time interval when switching a resis-tive load, V GS remains virtually constant at a level known asthe plateau voltage, V SGP . Therefore, rise and fall times maybe approximated by the following:

tr = Q 2 x R G /(VGG VGSP )

tf = Q 2 x R G /VGSPwhere

VGG = the gate drive voltage, which varies from zero to V GGRG = the gate drive resistance

and Q 2 and V GSP are read from the gate charge curve.

During the turnon and turnoff delay times, gate current isnot constant. The simplest calculation uses appropriate val-ues from the capacitance curves in a standard equation forvoltage change in an RC network. The equations are:

td(on) = R G Ciss In [VGG /(VGG VGSP )]

td(off) = R G Ciss In (VGG /VGSP )

The capacitance (C iss ) is read from the capacitance curve ata voltage corresponding to the offstate condition when cal-culating t d(on) and is read at a voltage corresponding to theonstate when calculating t d(off) .

At high switching speeds, parasitic circuit elements com-plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which iscommon to both the drain and gate current paths, produces avoltage at the source which reduces the gate drive current.The voltage is determined by Ldi/dt, but since di/dt is a func-tion of drain current, the mathematical solution is complex.The MOSFET output capacitance also complicates themathematics. And finally, MOSFETs have finite internal gateresistance which effectively adds to the resistance of thedriving source, but the internal resistance is difficult to mea-sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-tance (Figure 9) shows how typical switching performance isaffected by the parasitic circuit elements. If the parasiticswere not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuitused to obtain the data is constructed to minimize commoninductance in the drain and gate circuit loops and is believedreadily achievable with board mounted components. Mostpower electronic loads are inductive; the data in the figure istaken with a resistive load, which approximates an optimallysnubbed inductive load. Power MOSFETs may be safely op-erated into an inductive load; however, snubbing reducesswitching losses.

10,000

1,000

1010 100 1000

2400

2000

1600

1200

800

400

010 5 0 5 10 15 20 25

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

C ,

C A P A C I T A N C E ( p F )

Figure 7a. Capacitance Variation

VGS VDS

Figure 7b. High Voltage CapacitanceVariation

DRAINTOSOURCE VOLTAGE (VOLTS)

C ,

C A P A C I T A N C E ( p F )

VGS = 0 VVDS = 0 V TJ = 25C

Ciss

Crss

VGS = 0 VTJ = 25C

Ciss

Coss

Crss

100

2800

Ciss

Coss

Crss

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V D

S ,D R A I N T

O

S O U R

C E V

O L T A

G E

( V O L T

S )

V G S

, G A T E

T O

S O U R C E V O L T A G E ( V O L T S )

1.2

0.6

00.55 0.59 0.63 0.67 0.750.71 0.79

1000

100

11 10 100

12

10

8

6

4

2

00 4 8 12 16 20

Qg, TOTAL GATE CHARGE (nC)

50

350

400

300

200

100

0

DRAINTOSOURCE DIODE CHARACTERISTICS

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

I S ,

S O U R C E C U R R E N T ( A M P S )

Figure 9. Resistive Switching TimeVariation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

t , T I M E ( n s )

Figure 8. GateToSource and DrainToSourceVoltage versus Total Charge

QT

ID= 3 ATJ = 25C

td(on)

td(off)tf

tr10

Q1

Q3

VDD= 600 VID= 3 AVGS = 10 VTJ = 25C

VGS = 0 VTJ = 25C

VGS

VDS

2.4

1.8

3.0

24 28 32

16

14

250

150Q2

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves definethe maximum simultaneous draintosource voltage anddrain current that a transistor can handle safely when it is for-ward biased. Curves are based upon maximum peak junc-tion temperature and a case temperature (T C) of 25 C. Peakrepetitive pulsed power limits are determined by using thethermal response data in conjunction with the proceduresdiscussed in AN569, Transient Thermal ResistanceGeneralData and Its Use.

Switching between the offstate and the onstate may tra-verse any load line provided neither rated peak current (I DM)nor rated voltage (V DSS ) is exceeded and the transition time(tr,tf) do not exceed 10 s. In addition the total power aver-aged over a complete switching cycle must not exceed(TJ(MAX) TC)/(R JC ).

A Power MOSFET designated EFET can be safely usedin switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-sipated in the transistor while in avalanche must be less thanthe rated limit and adjusted for operating conditions differingfrom those specified. Although industry practice is to rate interms of energy, avalanche energy capability is not a con-stant. The energy rating decreases nonlinearly with an in-crease of peak current in avalanche and peak junction

temperature.Although many EFETs can withstand the stress of drain tosource avalanche at currents up to rated pulsed current(IDM), the energy rating is specified at rated continuous cur-rent (I D), in accordance with industry custom. The energy rat-ing must be derated for temperature as shown in theaccompanying graph (Figure 12). Maximum energy at cur-rents below rated continuous I D can safely be assumed toequal the values indicated.

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SAFE OPERATING AREA

1.0

0.1

0.011.0E05 1.0E04 1.0E03 1.0E02

t, TIME (s)

120

100

40

025 50 75 100 125 150

100

10

1.0

0.1

0.1 1.0 10 100 1,000

TJ, STARTING JUNCTION TEMPERATURE (C)

E A S ,

S I N G L E P U L S E D R A I N

T O

S O U R C E

Figure 12. Maximum Avalanche Energy versusStarting Junction Temperature


Figure 11. Maximum Rated Forward BiasedSafe Operating Area

A V A L A N C H E E N E R G Y ( m J )

I D ,

D R A I N

C U R R E N T ( A M P S )

Figure 13. Thermal Response

ID = 3 A

80

60

20

Figure 14. Diode Reverse Recovery Waveform

di/dt

trrta

tp

IS

0.25 IS

TIME

IS

tb

1.0E01 1.0E+00 1.0E+01

RJC(t) = r(t) RJCD CURVES APPLY FOR POWERPULSE TRAIN SHOWNREAD TIME AT t1TJ(pk) TC = P(pk)RJC(t)

P(pk)

t1t2

DUTY CYCLE, D = t1 /t2

0.2

D = 0.5

0.05

0.01

SINGLE PULSE

0.1

0.02

10,0000.01

RDS(on)LIMITTHERMAL LIMITPACKAGE LIMIT

VGS = 20 VSINGLE PULSETC = 25C

100 s

1 ms

r ( t )

, N O R M A L I Z E D E F F E C T I V E

T R A N S I E N T T H E R M A L R E S I S T A N C E

10 s

dc10 ms

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Figure 15. The AC Input/Filter Circuit Section

Figure 16. The DC/DC Converter Circuit Section

C5100 m F

450 V

C6100 m F

450 V

R4

R3

R2

R1

INPUT GND

+Vin470 k1/2 W

470 k1/2 W

470 k1/2 W

470 k1/2 W

+

+

D1D41N4007s

C30.0047

3 kV

C20.00473 kV

C40.11 kV

L1

L1

EARTHGND

H2

H1

C10.1

1 kV

90VAC600VAC

+Vin

R9

R8 R7 R6 R5

R111.8 k

D10

Vaux

R1027 k

D53.3 V

UC3845BN

LL

10 m F25 V

C10

7

4

12 5

6

INPUT GND

C7220 pF

C81000 pF

R131 k

U21/2MOC8102

R15680 W

R12 10 W

MTP3N120E

R141.2 W 1/2 W

Q1

D6

C91 nF3 kV

R16100 k1/2 W

MUR1100

T1

D8MBR370

D9MUR430

C13 C14

C11 C12+ +

+ +

100 m F10 V

100 m F20 V

D7 C172.2 nF

Vaux

MUR130

+12 V

+5 V

GND

R20120 W

C151.5 nF

U2MOC8102

U3TL431

C16 R17

R212.49 k

R1932.4 k

1.3 m F 7.5 k

82 k, 1/2 W

+

3

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PACKAGE DIMENSIONS

CASE 221A06ISSUE Y

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES AREALLOWED.

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.570 0.620 14.48 15.75B 0.380 0.405 9.66 10.28C 0.160 0.190 4.07 4.82D 0.025 0.035 0.64 0.88F 0.142 0.147 3.61 3.73G 0.095 0.105 2.42 2.66H 0.110 0.155 2.80 3.93J 0.018 0.025 0.46 0.64K 0.500 0.562 12.70 14.27L 0.045 0.060 1.15 1.52N 0.190 0.210 4.83 5.33Q 0.100 0.120 2.54 3.04R 0.080 0.110 2.04 2.79S 0.045 0.055 1.15 1.39T 0.235 0.255 5.97 6.47U 0.000 0.050 0.00 1.27V 0.045 1.15 Z 0.080 2.04

B

Q

H

Z

L

V

G

N

A

K

F

1 2 3

4

D

SEATINGPLANE T

CST

U

R

J

STYLE 5:PIN 1. GATE

2. DRAIN3. SOURC E4. DRAIN

How to reach us:USA/ EUROPE : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; TatsumiSPDJLDC, Toshikatsu Otsuki,P.O. Box 20912; Phoenix, Arizona 85036. 18004412447 6F SeibuButsuryuCenter, 3142 Tatsumi KotoKu, Tokyo 135, Japan. 0335218315

MFAX: [email protected] TOUCHTONE (602) 2446609 HONG KONG : Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,INTERNET : http://DesignNET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in differentapplications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure ofthe Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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