M.tech vlsi list 2014 15
3
SAK INFORMATICS (0)9603999243, 8333034195 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected] www.sakinformatics.com VLSI M.Tech list S.no TITLE YEAR 1 High speed convolution and deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) 2014 2 Low Power Square and Cube Architectures Using Vedic Sutras 2014 3 High speed multiplier for FIR filter design using window 2014 4 Pipelined architecture for vedic multiplier 2014 5 Novel square root algorithm and its FPGA implementation 2014 6 Binary division algorithm and high speed deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) 2014 7 An optimized design of binary comparator circuit in quantum computing 2014 8 Design of Dedicated Reversible Quantum Circuitry for Square Computation 2014 9 A novel approach for constructing reversible fault tolerant n-bit binary comparator 2014 10 Fast Radix-10 Multiplication Using Redundant BCD Codes 2014 11 Functional Constraint Extraction From Register Transfer Level for ATPG 2014 12 Fault Tolerant Parallel Filters Based on Error Correction Codes 2014 13 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 - 1, 2n - 1, 2n} 2014 14 Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation 2014 15 Secure and efficient LBIST for feedback shift register-based cryptographic systems 2014
-
Upload
sak-informatics-pvt-ltd -
Category
Engineering
-
view
243 -
download
5
Transcript of M.tech vlsi list 2014 15
SAK INFORMATICS (0)9603999243, 8333034195 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected]
www.sakinformatics.com
VLSI M.Tech list
S.no TITLE YEAR
1 High speed convolution and deconvolution algorithm (Based on Ancient
Indian Vedic Mathematics)
2014
2 Low Power Square and Cube Architectures Using Vedic Sutras
2014
3 High speed multiplier for FIR filter design using window
2014
4 Pipelined architecture for vedic multiplier
2014
5 Novel square root algorithm and its FPGA implementation
2014
6 Binary division algorithm and high speed deconvolution algorithm
(Based on Ancient Indian Vedic Mathematics)
2014
7 An optimized design of binary comparator circuit in quantum computing
2014
8 Design of Dedicated Reversible Quantum Circuitry for Square
Computation
2014
9 A novel approach for constructing reversible fault tolerant n-bit binary
comparator
2014
10 Fast Radix-10 Multiplication Using Redundant BCD Codes
2014
11 Functional Constraint Extraction From Register Transfer Level for
ATPG
2014
12 Fault Tolerant Parallel Filters Based on Error Correction Codes
2014
13 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 - 1, 2n - 1,
2n}
2014
14 Area-delay-power-efficient architecture for folded two-dimensional
discrete wavelet transform by multiple lifting computation
2014
15 Secure and efficient LBIST for feedback shift register-based
cryptographic systems 2014
SAK INFORMATICS (0)9603999243, 8333034195 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected]
www.sakinformatics.com
VLSI M.Tech list
16 Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D
Discrete Wavelet Transform 2014
17 Design and implementation of a BIST embedded inter-integrated circuit
bus protocol over FPGA 2014
18 A novel approach to realize built-in-self-test(BIST) enabled UART using
VHDL 2014
19 Design and implementation of high-performance master/slave memory
controller with microcontroller bus architecture 2014
20 On Hard Adders and Carry Chains in FPGAs
2014
21 Implementation of floating point MAC using Residue Number System
2014
22 Design of a Low Error Fixed-Width Radix-8 Booth Multiplier
2014
23 A Novel Parallel Multiplier for 2's Complement Numbers Using Booth's
Recoding Algorithm
2014
24 An approach for efficient FIR filter design for hearing aid application
2014
25 Comments on “Self-Checking Carry-Select Adder Design Based on
Two-Rail Encoding” [Dec 07 2696-2705]
2014
26 Low Voltage and Low Power 64-Bit Hybrid Adder Design Based on
Radix-4 Prefix Tree Structure
2014
27 Design and Implementation of 32 Bit Unsigned
Multiplier Using CLAA and CSLA
2013
22 FPGA Implementation of high speed 8-bit Vedic multiplier using barrel
shifter
2013
29 Design of High Speed Low Power Multiplier using Reversible logic: a
Vedic Mathematical Approach
2013
30 Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD
Tool
2013
31 CORDIC Designs for Fixed Angle of Rotation
2013
32 Design and Implementation of a DDR3-based Memory Controller 2013
SAK INFORMATICS (0)9603999243, 8333034195 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected]
www.sakinformatics.com
VLSI M.Tech list
33 Accessing AHB Bus using WISHBONE Master in SoC Design 2013
34 Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers 2013
35 The Design of High Speed UART 2013
36 Novel High Speed Vedic Mathematics Multiplier Using Compressors. 2013
37 VLSI implementation of a high speed single precision floating point unit
using verilog
2013
38 A novel hardware efficient FIR filter for wireless sensor networks 2013
39 VLSI implementation of Fast Addition using Quaternary Signed Digit
Number System
2013
40 Design and implementation of truncated multipliers for precision
improvement
2013
41 Design of Low Power Comparator Circuit Based on Reversible Logic
Technology
2013
42 A Novel Modulo Adder for Residue Number System 2013
43 Error Detection in Majority Logic Decoding of Euclidean Geometry Low
Density Parity Check (EG-LDPC) Codes
2013
44 Multi-operand Redundant Adders on FPGAs 2013
45 Concurrent Error Detection for Orthogonal Latin Squares Encoders and
Syndrome Computation
2013
46 20-GHz 8 × 8-bit Parallel Carry-Save Pipelined RSFQ Multiplier 2013
47 Design of Low Power Comparator Circuit Based on Reversible Logic
Technology
2013
](https://static.fdocuments.in/doc/165x107/55cf8fe1550346703ba0ce6f/vlsi-technologymtech-1-1unit-3.jpg)
