MT6223 phone design notice...

MediaTek ConfidentialSubject to Change without Notice

MT6223(P) Phone Design NoticeMT6223(P) Phone Design Notice

2007/07/032007/07/03

WCP/SA/RP1WCP/SA/RP1


MT6223 PackageMT6223 Package

0.360.211.20.2750.52249.09.0

CA1A (Max.)beNED

SubstrateThk.

Stand OffPackageThk.

Ball Dia.Ball PitchBall CountBody Size


MT6223MT6223 vsvs MT6205MT6205

3(ext)+4(int)5ADC

MT6223Ponly

XSW Card

3(921.6kps)

2(115.2kbps)

UART

I2SXAudio Link

ACXResolution

MonoX

VV

Recording

Serial I/F

Keypad

EINT

BT

I2S

I2C

AudioDAC

FMRadio

LCM I/F

5x65x5

4X

DAI/PCMXVoice Link

VX

VX

2XChannel

StereoXInput

8/9-bitXParallel I/F

MT6223MT6205B


KeypadKeypad

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1R O W 0

R O W 1

R O W 2

R O W 3

R O W 4

C O L 0 C O L 1 C O L 2 C O L 3 C O L 4 C O L 5 C O L 6

P M ICB a seb a n d

1

1

1

1

1

1 1 1 1 1 1

D ed ica ted fo r P o w er-key

P M IC in teg ra ted B B ch ip

(5x 6 + o n e p o w er-key ) key m a tr ix

PWRKEY

R209NC

C231

100n

/SYSRST

D2E4

D3

D4

B1

G10G9H8

C2

RSTCAPVMSEL

PWRKEY

VREF

LED_BLED_GLED_R

RESET

C249

100n

S16

KSW[PWR/End]

C229

100n

VDD

•MT6223 is 5x6 matrix

•COL6 is dedicated for POWER_KEY(internal connection).


ADCADC

xAuxiliary ADC channel 0 data register for TDMA event 0AUXADC_7

xADC for Battery Voltage detectionAUXADC_6

xADC for charging current senseAUXADC_5

xADC for Charger voltage detectionAUXADC_4

xInternal reference voltageAUXADC_3

N2External ADC channelAUXADC_2

M3External ADC channelAUXADC_1

M2External ADC channelAUXADC_0

Pin outFunctionADC channel


MT6223 Speech & AudioMT6223 Speech & Audio

AU_MOUTL

AU_MOUTR

AU_OUT0_P

AU_OUT0_N

AU_FMINL

AU_FMINRM

UX

MU

X

Stereo-to-Mono

Stereo-to-Mono

FM/AM radiochip

VoiceSignal

AudioSignal

Voice Amp-0

Audio Amp-R

Audio Amp-L

AU_VIN0_P

AU_VIN0_N

AU_VIN1_N

AU_VIN1_P

MU

X

VoiceSignal

AudioLCH-DAC

AudioRCH-DAC

Voice DAC

Voice ADC

PGA

VXVR

VXMP3

VXWT 64Tones

MT6223MT6205Features

VVEcho Suppression

VXEcho Cancellation

VXNoiseSuppression

VXDL

VXULNoiseReduction

VXCTM

VXAMR HR

VXAMR FR

VVEFR

VVHR

VVFR

SpeechCodec

104MHz52MHzSpeed

21DSP


LCD & Memory Card I/FLCD & Memory Card I/F

•LCD I/F can control 2 LCMs and 1memory card at the same time.

•Memory Card I/F is MT6223P only.

•For SW memory card, if EINT isexhausted, it could uses MFIQ forCard detection. Anyway MFIQ actswhen 26MHz system clock on.

LCD2

R81247K

VR804VR801

MCCK

VDD

LCD3

MF

IQ_C

ardIn

VR802

R814200

VR805 VR807

LCD0

R81047K

R81147K

J802

TFRPN-00815-TP00

12345678

9101112

DAT2CD/DAT3CMDVDDCLKVSSDAT0DAT1

VSSVSSVSS

Detect

R80947K

C8054.7uF

LCD1

VR806

LCD4

MFIQ_CradInHigh : Card push outLow : Card push in

VR803

VDD

R81347K

Push-To-PushT-Flash Card

MCDA0

MCDA1

MCDA2

MCDA3

MCCMMSDC IF

SA0SDASCLKSerial IF

PD0PD1PD2PD3PD4PD5Pd6PD7PD8Parallel IF

D0D1D2D3D4D5D6D7D8LCD IO


PMU of MT6223PMU of MT62231.1 Charger Schematics

5108Total

X (Internal)ISENSE_OUT

X (ExternalResistor)12

X (Internal)VB_OUTX (External

Resistor)11

X (Share withCHRIN)GDRVUSB

X (Share withCHRIN)10

X (Share withCHRIN)USB

X (Share withCHRIN)9

X (Only Li-ion)X (Only Li-ion)BATUSE

(Li-ion and NiMH)8

X (Internal)INTCHRDET7

X (Internal)X (ThroughSPI)CHRCNTL6

BATDETBAT_ONBATDET5

BATSENSEVBATBATSNS4

ISENSEISNENSEISENSE3

GATEDRVGDRVACGATEDRV2

CHRINACCHRIN1

MT6223MT6318MT6305B


PMU of MT6223PMU of MT62231.2 Charger Current

8008007

6506506

4504505

3003004

2252253

1501502

90901

62.562.5

400

0

CC

62.562.525Pre-Charge

0.2 Ohm0.2 Ohm0.4 OhmSense Resistor

MT6223MT6318MT6305B

For Layout:Connect ISENSE and BATSNS directly to the two terminal of sense resistorto get a precise charge current. Don’t connect BATSNS to other VBAT tracenear IC, which could cause charge current mismatch for over hundreds mA.


PMU of MT6223PMU of MT62231.3 Charger Protection

7V

9V

MT6223

6.8V9V9VCharger OVP Point

30V15V15VMax. Charger Input

OVP/OCPMT6318MT6305B

VCHG

R201 0

U202

BQ24316

1

2 7

8

3

4 5

6

IN

VSS ILIM

OUT

NC

/fault /CE

VBAT

VBAT

TO CHRIN

C235

1u(1

6V08

05)

CHRIN

R202 220KR

205

25K

C2051uF

F201

FUSE(1A 0603)

Ext_OVP/OCP:


PMU of MT6223PMU of MT62232. LDO

X200XVIBR

X50XVSW_A

X250XVMC

X20XVUSB

VVXBAT_BACKUP

VVVVRTC

250XXVRF

202020VSIM

202020VTCXO

75150150VM

100100100VIO

125150150VA

200200200VCORE

MT6223 (mA)MT6318 (mA)MT6305B (mA)LDO Current


PMU of MT6223PMU of MT6223LDO-Capacitor Selection

0.1 uF0.1uF1 uF1 uF1 uF2.2 uF1 uF4.7 uF4.7 uFOutputCapacitor X5RX5RX5RX5RX5RX5RX5RX5RX5R

BAT__BACKUPVRTCVSIMVMVIOVCOREVTCXOVRFVALDO

VRF_SENSE layout noticeThe VRF_SENSE pin shouldconnect to MT6139’s power inpin directly to reduce thevoltage drop. And theVRF_SENSE trace should beprotected by GND in layout.


PMU of MT6223PMU of MT62233. SIM

C243

nc

C236

nc

C241

ncC2462.2u/6.3V (X5R)

VSIM

J219

ID1A-6S-2.54SF

1 2

3 4

5 6

7 89 10

CLK I/O

RST VPP

VCC GNDGND

GND

GND

GND

A5B5

C6D6

VSIMSIMIO

SIMRSTSIMCLK

378Total

X (Internal)X (Through SPI)SIMSEL8

X (Internal)SIMVCCSIMVCC7

X (Internal)SIMCLKSIMCLK6

X (Internal)SIMRSTSIMRST5

X (Internal)SIMIOSIMIO4

SCLKSCLKSCLK3

SRSTSRSTSRST2

SIOSIOSIO1

MT6223MT6318MT6305B

The equivalent capacitor on SIMI/F must be under 100pF toinsure operation normally.


PMU of MT6223PMU of MT62234. LED & Vibrator Driver

250 mAVIBRATOR

150 mALED

25 mALED_B

25 mALED_G

25 mALED_R

Current CapabilityDriver

•LED with PWM2 control duty cycle

•Vibrator/LED_X without PWM


VRF Design NoteVRF Design Note

● Place a 4.7uF X5R capacitor close to PMU to keep stabilization andperformance

● Place a 4.7uF X5R capacitor close to RF transceiver to keep stabilizationand performance

● Keep VRF trace > 15mil● Connect sense pin, VRF_SENSE, to RF’s power to reduce the voltage drop

due to layout and package.● Protect VRF_SENSE with GND vias and planes.


VTCXO Design NoteVTCXO Design Note

● Place a 1.0uF X5R bypass cap. and reserve a series 0402 0Ohm near PMU● Place 1uF X5R//10pF bypass cap. and reserve a series 0402 0Ohm close to

TRx pin16 VCCSYN● Protect VTCXO with GND vias and planes. If RF is on top layer, suggest to

put VTCXO routing on layer5 with good GND planes layer4 and layer6● Do not place any power, analog, digital, and signal traces and vias parallel

or close to VTCXO routing.● Keep VTCXO trace > 15mil● Do not place VTCXO trace across layers under RF transceiver /Crystal● Placement of PMU and RF transceiver as close as possible


MT6223 Memory Support PlanMT6223 Memory Support Plan

Intel Crystal (burst, deMux)Spansion NSJ (burst)ST M36W0R5040U3 (32+16 AD MUX, Intel pinout)

16

Samsung K5N3208ATM (32+16, ADMUX, Spansion pinout)8

Intel Crystal (burst, deMux)Spansion PLJ (70/30/16)ST M36W0R6050T1 (64+32 deMux)ST M36W0R6050U0 (64+32 AD MUX)Toshiba TV00560002DDGB (70/30/16)

32

32

16

RAMNOR

Intel Crystal (burst, deMux)ST M36W0R6040U3 (64+16 AD MUX, Intel pinout)

64

ModulePhone

GPRS

Remark: Spansion VSK, ES at Aug/07, 2008 Q1 MP


AD_MuxAD_Mux MCPMCP

EWAIT

EA23

ED3

ED[0..15]

ED6

EA21

ED9

ED4

ED13

VMEM_EMI

ED0

/EWR

ED8

/ECS0

VMEMED5

R512 0ohm(NC)

/ECS1

/WATCHDOG

EA19

EA24

ECLKEA18EA17

EA20

ED10

ED14

ED2

ED11

R511 0ohm /EADV

R-CRE: control register enable;for cellularRAM only

/EUB

/ERD

/ECS2

EA22

R510 0ohm

EA[17..22]

ECRE

ED12

U500

J14J13H11H10

J9J8H7H6

H13H12J11J10H9H8J6J5G6

F13G12F12G7F6

F14 G11G10G13

F5

H14

K9

E10E9

K10

G9

F9G5J12

F11

F8G8F10

A/DQ0A/DQ1A/DQ2A/DQ3A/DQ4A/DQ5A/DQ6A/DQ7A/DQ8A/DQ9A/DQ10A/DQ11A/DQ12A/DQ13A/DQ14A/DQ15A16A17A18A19A20A21A22 WP#/ACC

RESET#CE_F1#

RY_BY#f/RDY

OE#

CE_PS1#

R-UB#R-LB#

R-CRE

A23

VccVccQVccQ

F-ACC

CLKAVD#WE#

ED7

ED15 /ELB

ED1

For AD_Mux MCP:

1.EA0~15 are share with ED0~15.

2.Baseband’s EA17 connect to AD_MuxMCP EA16

Burst mode MCP mustcheck EWAIT, ECLK, and/EADV


Tools for MT6223Tools for MT6223

● Flash Tool/ MutilPortDownLoad : Ver_3.1.05● META : Ver_5.3.8● ATE : Ver_5.3.8


PCB note_4LayerPCB note_4Layer--II

•MT6223 0.5mm Pitch，top layer的trace在ball與ball之間必需要使用到3mil/3mil (線寬/線距)，當走出chip時,就要用4mil/4mil (線寬/線距)；雷射孔4/12 mil(Drill/Diameter)。

•內圈ball：優先使用1-4層貫孔，走內層，因內圈大多是GND pin，建議要配合1-2層雷射孔一起使用。


PCB note_4LayerPCB note_4Layer--IIII

第4 圈ball：第一優先使用1-4層貫孔，走內層。第二是使用1-2層雷射孔走L2層。

第3圈ball：第一優先使用1-2層雷射孔走L2層。第二是，若內圈有空間，可使用1-4層貫孔，走內層。若TOP走線有穿過ball，線寬與線距就要3mil。


PCB note_4LayerPCB note_4Layer--IIIIII

第1圈ball：第一優先使用4mil線寬的TOP走線，第二才是使用1-2層的雷射孔，走L2層。若TOP走線有穿過ball，線寬與線距就要3mil。

第2圈ball：第一優先使用3mil線寬的TOP走線，第二才是使用1-2層的雷射孔，走L2層。若TOP走線有穿過ball，線寬與線距就要3mil。

6-layer每圈ball的走線方式，大致與 4-layer相同，因6-layer會多埋孔，所以不同在於第4圈及內圈會以1-2層雷射孔加2-5層埋孔為主。

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