MScThesis Jagdish Pandey Final

7/31/2019 MScThesis Jagdish Pandey Final

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Low Power LO Generation Based on Frequency

Multiplication Technique

A Thesis

Submitted for the Degree of

Master of Science (Engineering)

in the Faculty of Engineering

by

Jagdish Narayan Pandey

Electrical Communication Engineering

Indian Institute of Science, Bangalore

Bangalore 560 012 (INDIA)

July, 2007


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i

I, hereby declare that the work reported in this thesis has been carried out inthe Circuits and Systems Lab, Department of Electrical Communication Engineer-ing, Indian Institute of Science, Bangalore under the supervision of Dr. Bharadwaj

Amrutur. I also declare that this work has not formed the basis for the award ofany Degree, Diploma, Fellowship, Associateship or similar title of any University orInstitution.

Jagdish Narayan Pandey,Circuits and Systems Lab,Department of Electrical Communication Engineering,Indian Institute of Science,Bangalore-560 012,INDIA.July 2007.


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Abstract

TO achieve high level of integration in order to reduce cost, heterodyne archi-

tecture has made way for low-IF and zero-IF (direct conversion) receiver ar-

chitectures. However, a very serious issue in implementing both zero and low-IF

receiver is of local oscillator (LO) pulling. Another challenge is on-chip generation

of high-precision quadrature LO signals for image-rejection. We have addressed both

these issues in this thesis. Regarding the first problem, we have developed a low-

power frequency multiplication technique which uses a low frequency ring oscillator

and multiplies its frequency in power efficient way to generate the desired frequency.

We then use this differential LO signal to generate high-precision quadrature phases

by using polyphase filter and an injection-locked quadrature oscillator.

Design examples are presented for 2.4 GHz band of IEEE 802.15.4 standard

which is a low-data rate WPAN standard. The standard offers relaxed performancespecifications in order to help achieve low power of operation.

Contributions in the thesis

The problem of local oscillator (LO) pulling can be addressed by running LOat a much reduced frequency and use a frequency multiplier (FM) to generate

the desired frequency. Also, use of low-frequency LO saves power in VCOand helps eliminate first few dividers leading to significant power savings. In

addition, the entire frequency synthesizer can be run at a lower supply voltage

saving additional power.

The frequency multiplier involves combining edges from the lower frequency

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Abstract iii

ring oscillator. It improves upon the prior work by proposing a new lower-power

edge-combiner. The overall power is reduced by exploiting the relaxed phase

noise specification of IEEE 802.15.4 standard. Simulations using SpectreRFshow that the circuit consumes only 550 W of power in 0.13 m RF-CMOS

technology with 1.2 V supply voltage, and provides 950 VPP sinusoidal output

with phase noise of -85.5 dBc/Hz at 1 MHz offset.

An injection-locking based quadrature desensitization circuit is designed forprecision quadrature generation. The differential (two phase) output of the

frequency multiplier is fed to a polyphase filter to generate nearly quadrature

signals. Output of polyphase filter is in turn fed to the desensitizer circuit to

obtain high-precision quadrature signals. Designed for 2.4 GHz band in 0.13 m

RF-CMOS technology, it achieves a phase error of 0.5 for 1% mismatch in LC

tanks. It achieves a phase noise of -84.3 dBc/Hz at 1 MHz offset and provides

quadrature sinusoids of 475 mV amplitude while consuming 1.56 mW of power.

We have analyzed the popular cross-coupled LC-VCOs to generate quadrature

sinusoids. In practical LC-oscillators built using low/moderate quality factor on-

chip inductors, the actual frequency of oscillation is a little less than 1/2

LC.

This is known as Groszkowski effect. On the other hand, in quadrature oscillator

topologies, consisting of two, cross-coupled, negative resistance LC-VCOs using

parallel coupling transistors, an upward shift in frequency of oscillation from the

free-running frequency of each LC-VCO is observed. This is because in order to

satisfy the Barkhausens criteria, the LC-tanks have to operate at a frequency

away from the frequency of resonance. This effect called as quadrature detuning

effect results in higher phase noise and reduced amplitude.

We have shown that the old treatment given in literature is quite inaccurate for

practical LC oscillators that are built using low/moderate Q on-chip inductors.

Also the prior work ignores Groszkowski effect which could be significant for low


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Abstract iv

Q LC tanks. We have provided simple, accurate and closed-form expressions

of associated frequency-shifts and amplitude of oscillation including both the

effects. Our results show excellent match with results obtained from SpectreRFand Matlab simulations.

List of Publications

1. J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low-power fre-

quency multiplication technique for ZigBee transceiver, IEEE Int. Conf. on

VLSI Design, Jan 2007

Submitted and in preparation

1. J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low power GHz-

range frequency multiplier for low-data date applications Submitted to IEEE

Transactions on circuits and systems-I

2. J. N. Pandey and Bharadwaj Amrutur, On frequency shifts in cross-coupled

LC-VCOs Submitted to IEEE Transactions on Circuits and Systems-II

3. J. N. Pandey and Bharadwaj Amrutur, Comparison of quadrature genera-

tion methods for frequency multiplication based oscillators In preparation


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To Shri Ram

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Acknowledgement

I would like to thank my advisor Dr. Bharadwaj Amrutur for encouraging me to do

creative research, his invaluable guidance and for his patience with me. His wisdom

will continue to be the guiding light for me in years to come. I profusely thank Dr.

Shantanu Mahapatra for being examiner in my Comprehensive Exam. I thank Dr.

Navakanta Bhat for teaching me the fundamentals of CMOS Analog Circuits through

his course. Thanks are also due to Dr. K. J. Vinoy for his useful comments on the

testing of our chip and lending the equipment. I thank Dr. Shanthi Pavan and Dr.

Nagendra Krishnapura at IIT Madras for teaching a wonderful short course on RF

Circuit Design.

Special thanks are due to Sudhir Kudva and Raghavendra R.G. whose generosity

and patience with me knew no limits. Sincere thanks to Cadence India for Cadence

licenses and Ms. J. Vedavalli for taking care of software issues. Life would have beentougher without the support of two great friends: Vishal Saxena and Satyam Dwivedi.

I would also like to single out Basavraj Talwar and Pratap Kumar Das for helping

me in a hundred different ways. Thanks are due aplenty to Madhusudan, Rakesh,

Balaji, Vijay, Anmol, Harish, Deepak, Venkatesh, Chaitanya, Arvind, Fazeel, Reddy,

Kannan and Janakiraman for being such a good company.

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Contents

Abstract ii

v

Acknowledgement vi

1 Introduction 1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Background 72.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1.1 Maximum Transmit Power . . . . . . . . . . . . . . . . . . . . 102.1.2 Receiver jamming resistance . . . . . . . . . . . . . . . . . . . 102.1.3 Effect of local oscillator phase noise on receiver and transmitter 10References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 A Low Power GHz-Range Frequency Multiplier for Low-Data RateApplications 153.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2 Frequency Multiplication by Edge-Combining . . . . . . . . . . . . . 183.3 A new method of edge-combining . . . . . . . . . . . . . . . . . . . . 21

3.3.1 Differential Operation . . . . . . . . . . . . . . . . . . . . . . 253.4 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.4.1 Effect of ground bounce . . . . . . . . . . . . . . . . . . . . . 313.4.2 Effect of mismatches in the ring oscillator . . . . . . . . . . . 323.4.3 Choice of multiplication number, M . . . . . . . . . . . . . . . 343.4.4 Voltage scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4 Layout Issues 404.1 Simulation of layout extracted netlist . . . . . . . . . . . . . . . . . . 42

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Contents viii

5 Quadrature Generation Methods For Frequency Multiplication BasedOscillators 445.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2 Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator 465.2.1 Combining Current Pulses . . . . . . . . . . . . . . . . . . . . 465.3 Quadrature generation based on poly-phase filters . . . . . . . . . . . 505.4 High-precision quadrature generation based on injection-locking . . . 55

5.4.1 Injection-locking as a desensitizer for I-Q imbalance . . . . . . 555.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6 On Frequency Shifts in Cross-Coupled LC-VCOs 616.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616.2 Behavioral modeling of LC-oscillators and Groszkowski Effect . . . . 62

6.3 Behavioral modeling of cross-coupled LC-VCOs and Quadrature De-tuning Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676.3.1 Treatment in literature . . . . . . . . . . . . . . . . . . . . . . 676.3.2 Our approach . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7 Conclusion 78

A Injection-Locking Basics 80References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84


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Tables

2.1 Frequency bands and data-rates . . . . . . . . . . . . . . . . . . . . . 8

3.1 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.1 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1 Summary of Expressions . . . . . . . . . . . . . . . . . . . . . . . . . 75

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Figures

1.1 Local oscillator pulling . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Local oscillator pulling in direct conversion transmitter architecture [4] 31.3 Offset LO architecture for direct conversion transmitter [4] . . . . . . 4

2.1 2.4 GHz frequency band in IEEE 802.15.4 . . . . . . . . . . . . . . . . 82.2 2.4 GHz frequency band in IEEE 802.15.4; The transmitter, in part . 92.3 Low-IF receiver block diagram . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Effect of local oscillator phase noise on (a) Receiver (b) Transmitter . 112.5 Calculation of phase noise from receiver side; Sn(f) represents thephase noise profile of the interferer channel . . . . . . . . . . . . . . . 12

3.1 Block diagram of an Integer-N PLL . . . . . . . . . . . . . . . . . . . 163.2 DLL-based frequency multiplier [5] . . . . . . . . . . . . . . . . . . . 163.3 PLL with a Frequency Multiplier; Here the PLL runs at fout/M where

fout is the desired frequency . . . . . . . . . . . . . . . . . . . . . . . 173.4 Frequency multiplication scheme of Chien et al. (M=9) . . . . . . . . 193.5 Frequency multiplication scheme of Shwetabh Verma et al. . . . . . . 203.6 3-Stage Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.7 Voltage waveforms of a 3-stage ring oscillator; T is the time period ofthe VCO shown in Fig. 5 . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.8 (a) An edge-combining switch for M=3 and (b) A symmetric arm . . 223.9 A single-ended frequency multiplier for M=3; Sizes are shown for target

frequency of 2.4 GHz implemented in 0.13 m technology . . . . . . . 233.10 Various voltage and current waveforms in circuit shown in Fig. 3.9.

(a) shows the three phases of the ring oscillator for the multiplicationfactor M=3. (b) shows the current through the tail transistor MCSand (c) contains the voltage waveforms at Node N and tail node P . . 25

3.11 (a) Differential 3-Stage Ring Oscillator [6] (b) A unit inverter . . . . 26

3.12 Frequency multiplier with differential output. Component values shownare for 0.13m technology and 2.4GHz center frequency. S and S rep-resent the complementary switches . . . . . . . . . . . . . . . . . . . 28

3.13 (a) Amplitude (b) Tuning curve and (c) Phase Noise for circuit shownin Fig. 3.12 for 2.4 GHz ZigBee band, M=3 using symmetric arms (Fig.3.8(b))and differential realization (Fig. 3.12) . . . . . . . . . . . . . . 30

3.14 Spurs at the frequency multiplied output. fRO is ring oscillator fre-quency and M, the multiplication factor . . . . . . . . . . . . . . . . 33

x


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Figures xi

3.15 Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using MonteCarlo analysis, N=1000, VT,N = 5.5%, VT,P = 2%, ,N = 10% ,P =6% and M=3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.16 Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using MonteCarlo analysis, N=2000, VT,N = 5.5%, VT,P = 2%, ,N = 10% ,P =6% and M=3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 (a) Single-ended frequency multiplier for M=3 and (b) The low fre-quency ring oscillator; NMOS is sized 2 m/0.2 m and PMOS is sized4 m/0.2 m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2 Symmetric floor plan for layout of the multiply-by-3 circuit. . . . . . 414.3 Layout of the ring oscillator and cascaded switches; Inductor, capacitor

and tail current source in the full multiplier circuit are not shown herein order to clearly display the arrangement of inverters and switches. 42

5.1 Six stage differential ring oscillator of Junfeng Xu et al. [8]. Size ratioof cross-coupling inverters to ring inverters is kept at 0.6. . . . . . . . 46

5.2 Frequency multiplier of Xu et al. [8] that combines current pulses froma low-frequency ring oscillator. The 12 inverters in the ring oscillatorare grouped into 4 sets with each having 3 inverters. Power nodes ofeach inverter in a set are connected to an LC-tank. . . . . . . . . . . 46

5.3 Regenerative, inductive-peaked buffer to amplify the output of fre-quency multiplier of Xu et al. It provides a voltage gain of about 4.5at a bias current of 500 A. . . . . . . . . . . . . . . . . . . . . . . . 48

5.4 6-stage differential ring oscillator phases to generate I and Q signals;Gray phases are complementary to Black ones to achieve differentialoperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.5 Composite switches to achieve quadrature edge-combining. Each NMOSis sized 6 m/0.12m . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.6 Quadrature edge-combiner circuit. SI and SI are the in-phase com-plementary edge-combining switches. Similarly, SQ and SQ are thequadrature-phase complementary edge-combining switches. . . . . . . 50

5.7 Frequency multiplier that combines edges from a low-frequency ringoscillator. S and S are the complementary edge-combining circuits.A, B and C are the three phases from a 3-stage ring oscillator. A, B

and C denote the complementary phases. . . . . . . . . . . . . . . . . 515.8 (a) A constant resistance lattice network and (b) Allpass filter of Sha-

effer et al. [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525.9 (a) 1-stage poly-phase filter (PPF) and (b) A 2-stage PPF with stag-

gered poles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535.10 Injection-locked QVCO and frequency multiplier. (I2, Q2) have smaller

quadrature imbalance than that in (I1, Q1). . . . . . . . . . . . . . . . 56


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Figures xii

5.11 A connected-source QVCO with parallel cross-coupling PMOS tran-sistors, MCP,1 and MCP,1. Parallel NMOS devices MIP,inj and MIN,injare used to injection lock the QVCO. N1 and N2 directly come from

frequency multiplier described in Fig. 5.7, without any intermediatebuffers. One stage of PPF generates the approximate quadrature sig-nals that are added to a suitable common-mode voltage before injectionlocking the PQVCO. VC provides the common-mode level. . . . . . . 56

6.1 A conventional disconnected-source quadrature-coupled LC oscillator 636.2 (a) RS is the extra-series resistance of the inductor. Capacitor is as-

sumed to have high Q (b) Negative resistance LC-oscillator . . . . . . 656.3 f0 = 2.4GHz, fn, the natural frequency of oscillation = 2.3508 GHz, fg

the Groszkowski frequency=2.3412 GHz. = 2.25 and Q=5. . . . . . 666.4 Equivalent model of the oscillator; Gmc is the transconductance of the

coupling transistors M3M4 and Gmc that of oscillator core transistorsM1 M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.5 Series to parallel tranformation; Rp = Rs(1 + Q2) and Lp = Ls(1+1/Q

2) 686.6 Phasor diagram of cross-coupled LC-VCO topology of Fig. 6.1. m =

Gmc/Gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706.7 Simple model of a cross-coupled LC oscillator. The coupling transistors

M3 M4 (Fig.6.1) are modeled as VCCS with i v equation, i =Sc tanh(v Gnc/Sc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.8 Solutions of (6.8) showing three positive roots for ; a = tan() where is is the phase shift at Groszkowsi frequency fg; 1 = 0.23960,

2 = 0.83780, 3 = 1.06480. Also note that compared to 2, 3, thedominant frequency is much closer to = 0 line. . . . . . . . . . . . 726.9 Frequency response of the resonator and dominant mode selection; The

phase shift due to Growszkowski effect is = 2.25 and Q = 5. Thethree modes of oscillations are at frequencies f1 = 526.3MHz, f2 =2.010 GHz, f3 = 2.555 GHz . . . . . . . . . . . . . . . . . . . . . . . . 73

6.10 Preformance comparison of both the methods. Dashed lines repre-sents Prior work and solid lines this work. Circles represent the resultsobtained from SpectreRF. The difference in results of both methodsincrease as m increases and narrows down for higher Q. . . . . . . . 74

6.11 Comparison of amplitude obtained using both the methods versus theSpectreRF results. Good match is observed over a wide range of m. . 75

A.1 Simple additive feedback model of the injection-locked oscillator . . . 80A.2 (a) Phasor diagram of signals shown in Fig. A.1, (b) Position of phasers

at the edge of injection-locking when = 90 . . . . . . . . . . . . . . 81


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Chapter 1

Introduction

1.1 Introduction

DEVELOPMENT of viable wireless sensor networks (WSNs) calls for a large

reduction in cost, power and form factor of radio transceivers, achievable today.

The call for low-power is primarily due to the fact that, most often, the nature of

environment in which the WSNs operate, makes battery replacement very hard, if not

impossible. Also applications such as environmental monitoring over large areas, may

require a very large number of devices that make battery replacement impractical.

Development of truly energy-harvesting sensor nodes is yet a long way to go as the

typical power harvested from common surroundings is of the order of 100W [1].

The research is on for an on-chip, low-cost and high-quality resonator, and a high-

efficiency energy-scavenger that can make self-powered sensor nodes a possibility. At

the same time, circuit-techniques are being constantly explored in order to prolong

the life of currently used batteries.

The radios usually employ phase or frequency modulation scheme to allow for a

non-linear and efficient Power Amplifier (PA) at the cost of spectral efficiency. Low-

data rate and relatively large bandwidth of transmission translate to lower power of

transmission for comparable SNR. Low transmitted and received power levels allow

for a less linear receive chain which in turn allows for stacking of transistors to save

power by current re-using or using lower supply voltage [2]. Spreading is employed

to help relax Noise Figure (NF) specification of the receive chain, therefore saving

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1.1. Introduction 2

power.

A less stringent EVM (error vector magnitude, a measure of modulation accu-

racy of the transmitter) encourages the use of a direct conversion transmitter (DCT)that allows for high-level of integration. Furthermore, filter attenuation and image

rejection specifications are also kept moderate by requiring a rather benign receiver

jamming resistance test. This leads to moderate receiver LO I/Q quadrature accu-

racy, easily realizable in modern CMOS processes.

To achieve high level of integration in order to reduce cost, heterodyne receiver is

not a favourable candidate as it uses bulky off-chip surface acoustic wave (SAW) filters

for image-rejection. Also intermediate frequency (IF) being high, a separate PLL isrequired to generate IF signal. As a result, low-IF and zero-IF (direct conversion)

receiver architectures have become more attractive. A moderate rejection of adjacent

channel (which becomes the image signal in low-IF receiver) in WSNs, helps overcome

the most serious design issue for Low-IF architecture and makes it a serious competitor

to zero-IF which has the simplest architecture (i.e. low complexity, cost and power

[3]).

Signal Large inbandinterferer

LNA

LO

Mixer

Figure 1.1: Local oscillator pulling

However, a very serious issue in implementing both zero and low IF receiver is


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1.1. Introduction 3

of LO pulling. As illustrated in Fig. 1.1, large interferer signals in the signal band

that are unaffected by the band-select filter are very close to LO frequency. These

interferers get amplified by the LNA and couple to LO through substrate, and mixerdue to finite isolation between its LO and RF ports. This phenomenon is called

injection pulling of receive LO [4].

Receive LO pulling is typically alleviated using two techniques. (1) Placing a

good reverse isolation buffer betwen LO and Mixer. (2) Running LO at twice the

desired frequency and divide it by two, which also generates quadrature signals.

However, both these methods entail higher power dissipation. To save some

power, the LO buffer is usually resonator-loaded which, in addition to larger area, isprone to common mode instability problem when used with Gilbert mixer [5]. Also

for very high-frequency LOs, generating a doubly fast oscillator may not be possible

technologically.

An interesting solution to the problem could be running LO at a much reduced

frequency and use a frequency multiplier (FM) to generate the desired frequency.

Also, use of low-frequency LO saves power in VCO and helps eliminate first few

dividers leading to significant power savings.

PABPF

MixerI

Q

LO

900

sin0t

cos0t

LO

Figure 1.2: Local oscillator pulling in direct conversion transmitter architecture [4]

On the transmitter side, a high level of integration is achieved using the DCT


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1.1. Introduction 4

I

Q

BPF

BPF PA

Mixer

LO

VCO1

VCO2

sin

0t

cos0t

2

1 + 2

90

1

Figure 1.3: Offset LO architecture for direct conversion transmitter [4]

architecture. Here the PA output, a modulated waveform with large power, has

a spectrum centered around LO frequency. This strong signal couples to LO and

disturbs its frequency (Fig 1.2). The situation is usually amended by using sum or

difference frequencies of two VCOs whose individual frequencies are far different from

the desired sum or difference frequency (Fig 1.3) [6]. This method ia called offset-

LO architecture. Another solution is to go for a two step transmitter. Both these

methods, in addition to extra mixers, necessitate steep bandpass filters which may

have to go off-chip, coming in the way of integration [4].

Frequency multiplier can be used in DCTs without any additional BPF required.

Also only a single VCO and PLL is needed.

The rest of the thesis is organized as follows. Chapter 2 gives a brief description

of IEEE 802.15.4 standard, and presents its important and relevant specifications.

Although the circuits developed in the following chapters are applicable to any low-

data rate application, the design examples are made compliant with IEEE 802.15.4

standard.

Development of a low-power FM with design issues/trade-offs involved, is the

subject of Chapter-3. Chapter 4 discusses in brief the layout issues critical to the


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1.1. Introduction 5

performance of FM circuit. Layout extracted results for the frequency-multiplier are

compared with those obtained from the simulation of the schematic.

Generation of low-power and moderate/high-precision quadrature sinusoidal sig-nals for oscillators based on the concept of frequency multiplication is described in

Chaper 5. We evaluate a number of architectures and identify an optimal topology.

A complete analytical treatment for our quadrature LO generator requires an

accurate modeling of the QVCO. Chapter 6 models the frequency shifts associated

with modern CMOS QVCO circuits that consist of cross-coupled LC-VCOs. These

LC oscillators use low/moderate quality factor on-chip inductors to facilitate higher

integration and because of their low-Q, the involved frequency shifts could be fairlybig and their calculation not amenable to approximations that presume high-Q.

Chapter 7 presents the conclusions drawn from the work covered in this thesis.


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References

[1] S. Roundy, E.S. Leland, J. Baker, E. Carleton, E. Reilly, E. Lai, B. Otis, J.M.Rabaey, P.K. Wright, V. Sundararajan, Improving power output for vibration-based energy scavengers, IEEE Pervasive Computing, vol. 4, no. 1, pp. 28-36,Jan.-March 2005

[2] Behzad Razavi, Analog integrated circuit design, Prentice Hall

[3] Ilku Nam, Kyudon Choi, Joonhee Lee, Hyouk-Kyu Cha, Bo-Ik Seo, Kuduck Kwon,

Kwyro Lee, A 2.4 GHz low-power low-IF receiver and direct conversion transmit-ter in 0.18 m CMOS for IEEE 802.15.4 WPAN application, IEEE Transactionson Microwave Theory and Techniques, vol. 55, no. 4, pp. 682-689 April 2007

[4] Behzad Razavi, RF Microelectronics, Prentice Hall

[5] S. Gueorguiev, S. Lindfors, T. Larsen, Common-mode stability in Low-power LOdrivers, IEEE International Symposium on Circuits and Systems, pp. 5505-5508vol. 6, May 23-26, 2005

[6] T.D. Stetzler, I.G. Post, J.H. Havens, M. Koyama, A 2.7-4.5 V single chip GSM

transceiver RF integrated circuit, IEEE Journal of Solid-State Circuits vol. 30,no. 12, pp. 1421-1429, December 1995

6


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Chapter 2

Background

This chapter briefly descibes the relevant features of IEEE 802.15.4 LR-WPANstandard. Design specifications are obtained to be used in the subsequent chapters.

2.1 Introduction

IEEE 802.15.4 WPAN standard released a preliminary draft in 2003, targetted at

low-data rate applications such as low-cost pervasive wireless sensor networks,

with extremely low duty-cycle capability (< 10 ppm) [1]. It is the first global wireless

standard aimed at low-power remote monitoring and control applications. While

IEEE 802.15.4 has defined physical (PHY) and media access control (MAC) layers,

ZigBee alliance [3] has added Network, Security and Application layers above it.

IEEE 802.15.4 operates in three unlicensed industrial, scientific and medical

(ISM) bands of 868/915 MHz and 2.4 GHz with a total of 27 channels. Table 2.1

summarizes the information on various bands, their data-rates, availability and mod-

ulation schemes.

Of the 3 bands, 2.42.4835 GHz band is most attractive as it is the only world-

wide allocation of spectrum that does not have restrictions on the application and

transmit duty-cycling. The center frequencies in this band are given by

fc = 2405 + 5(k 11) MHz, k=11...26

7


21/97

2.1. Introduction 8

Table 2.1: Frequency bands and data-rates

Phy(MHz)

Frequencyband

(MHz)

Spreading parameters Data parameters

Chip rate(Kcps)

Modulation Bitrate(Kbps)

Symbolrate(Ksps)

Symbols

868 868868.6 300 BPSK 20 20 Binary915 902928 600 BPSK 40 40 Binary2450 2400

2483.52000 O-QPSK 250 62.5 16-ary

Orthog-onal

The band contains 16 channels, each 5 MHz wide with 3 MHz of guard band

between 2 MHz wide data bands (Fig. 2.1).

2 MHz5 MHz

5 MHz

2.4 GHz 2.4835 GHz

Figure 2.1: 2.4 GHz frequency band in IEEE 802.15.4

The 2450 MHz PHY has data-rate of 250 Kbps and uses 16-ary quasi-orthogonal

modulation technique. This modulation technique is a power-efficient one that achieves

low SNR at the expense of large bandwidth that is significantly larger than its symbolrate.

Fig. 2.2 depicts the baseband part of transmitter. Four information bits are

used to generate one symbol resulting in 62.5 Ksymbols per second symbol rate. Each

symbol is converted to 32-chip pseudo-random noise sequence leading to chip-rate of

2 Mchips per second. Alternate chips are delayed by one chip period Tc and seperated


22/97

2.1. Introduction 9

shaping

Half sine pulse

shaping

Half sine pulse

Bits

Bit to symbolmapping

Chip to symbolmapping parallel

Offset

Serial to

62.5 Ksymbols/s 2 Mchips/s

Q

I

delay,

250 Kbps

TC

Figure 2.2: 2.4 GHz frequency band in IEEE 802.15.4; The transmitter, in part

into I and Q streams. Each baseband chip is represented by a half-sine pulse. After

being translated to designated carrier frequency, the I and Q branches are summed

up at the input of power amplifier.

B

A

S

E

B

A

N

D

I

G

N

S

A

L

P

R

O

C

Duplexer LNAAntenna

VCO

I

Q

From Tx Channel Select Filter

ADC

ADC

I

Q

900

Figure 2.3: Low-IF receiver block diagram

IEEE 802.15.4 PHY dictates receiver sensitivity to be -85 dBm or better. DSSS

with chip rate of 2 Mcps results in 10log(Chip rate/Bit rate) 9 dB of processinggain.

Fig. 2.3 shows block-diagram of a low-IF receiver as an example. The RF

signal is amplified and translated to a suitable intermediate frequency whereafter it


23/97

2.1. Introduction 10

is digitized. The demodulation to baseband, image rejection and despreading takes

place in digital domain.

2.1.1 Maximum Transmit Power

The 802.15.4 PHY standard says that the maximum transmit power shall conform

to the local regulations. In United States, the FCC rules provide for 0 dBm of effec-

tive radiated power (ERP) for narrow-band operation and 1 mW/MHz for wideband

operation above 1000 MHz, upto 1 W ERP. While an IEEE 802.15.4 equipment is gen-

erally supposed to transmit upto 0 dBm of power, international community usually

allows for a maximum of +10 dBm. At the lower end, an IEEE 802.15.4 compliant

device must be able to transmit at least -3 dBm of power.

2.1.2 Receiver jamming resistance

Adjacent channel rejection Alternate channel rejection

0 dB 30 dB

Compare this with IEEE 802.11a WLAN standard [2] that requires 16 dB of

adjacent channel and 32 dB of alternate channel rejection for 6 Mbps data rate.

The adjacent channel rejection is measured under the following conditions. The

desired signal is 2450 MHz IEEE 802.15.4 compliant pseudo-random data. The desired

signal is input to the receiver at a level 3 dB above the maximum receiver sensitivity.

2.1.3 Effect of local oscillator phase noise on receiver and

transmitter

Figures 2.4 (a) and (b) describe the effect of oscillator phase noise on the receiver

and transmitter respectively. In receiver, it leads to a larger interferer in the nearby

channel downconverting to the desired signal band. This effect is called reciprocal

self-mixing. While in transmitter, a large phase noise LO results in significantly large


24/97


Signal Large inbandinterferer

Downconverted signalLO profile

LO

LO

(a)

Nearby transmitter

Desired signal

1 2

(b)

Figure 2.4: Effect of local oscillator phase noise on (a) Receiver (b) Transmitter

power in the neighbouring band that makes the detection of a weak signal in that

band very hard [1]. Phase noise also corrupts the information carried in the phase and

frequency of the carrier. LO phase noise specification is derived from the knowledge

of interferer profile for both receive and transmit case. Let us assume that phase noise

of the interferer in the desired band is constant at PNc (narrowband approximation),

its value at the center frequency of the adjacent channel (Fig. 2.5). On the receive

side,


25/97


BW

Large interferer

Wanted Signal

Sn(f)

f

fcPNc

Figure 2.5: Calculation of phase noise from receiver side; Sn(f) represents the phasenoise profile of the interferer channel

Total noise power in the signal band = Pint + PNc + 10log(BW)

Where Pint is the power of interferer and BW, the bandwidth of the signal (2 MHz).

Allowing for some margin in SNR,

PNc(dBc/Hz) = Psig Pint SNRmin 10log(BW) margins (2.1)

Where Psig is the power of the signal. With minimum signal power of -85 dBm,

SNRmin of 0.5 dB, 10 dB margin, and adjacent channel interferer rejection of 0 dB

(section 2.1.2), phase noise turns out to be -75.5 dBc/Hz at 5 MHz offset. For alternate

adjacent channel interferer rejection of 30 dB, required phase noise is -103.5 dBc/Hz

at 10 MHz offset.On the transmit side, maximum spurious emission level is provided by the FCC

in US and ESTI in Europe. The U.S. requirement, more restrictive than the Eu-

ropean one, limits the spurious emission level to -41.2 dBm/MHz or an average of

-101.2 dBm/MHz for 2.4 GHz operation. Since the nearest channel at the edge is cen-

tered at 2.48 GHz, using the spreading gain of about 9 dB, the allowed phase noise at


26/97


3.5 MHz offset is -92.2 dBc/Hz. The European requirement puts it at -71 dBc/Hz at

3.5 MHz offset [5].


27/97

References

[1] IEEE 802.15.4-2003 Part 15.4: Wireless Medium Access Control (MAC) and Phys-ical Layer (PHY) specification for Low-Rate Wireless Personal Area Network (LR-WPANs)

[2] IEEE 802.11a-1999(R2003) Part 11: Wireless Medium Access Control (MAC) andPhysical Layer (PHY) specification

[3] www.zigbee.org

[4] Behzad Razavi, RF Microelectronics, Prentice Hall

[5] Nam-Jin Oh, Sang-Gug Lee, Building a 2.4 GHz Radio Transceiver Using IEEE802.15.4, IEEE Circuits and Devices Magazine, pp. 43-51, Nov/Dec 2005.

14


28/97

Chapter 3

A Low Power GHz-Range

Frequency Multiplier for Low-Data

Rate Applications

This chapter presents a new method of generating high frequency sinusoidal signalbased on the technique of frequency multiplication. The method is suitable forwireless sensor networks (WSN) application where low-power operation takesprecedence over high fidelity. The chapter discusses various existing techniques offrequency multiplication, and proposes a new technique which has lower power. Itinvolves combining edges from a lower frequency ring oscillator. This techniqueis suitable for applications which have relaxed phase noise specifications. Finally,an example design is presented for 2.4 GHz IEEE 802.15.4 standard. Simulationsusing SpectreRF show that the circuit consumes only 550W of power in 0.13m

RF-CMOS technology with 1.2 V supply voltage, and provides 950 mVPP sinusoidaloutput with phase noise of -85.5 dBc/Hz at 1 MHz offset.

3.1 Introduction

SYNTHESIS of high frequency on-chip clock signals is usually done via a Phase

Locked Loop (Fig. 3.1). Here the output of the VCO which generates the desired

clock, is divided by a factor of N and phase-locked to a low frequency reference clock

signal. In the frequency synthesizer, the largest fraction of power is consumed by the

components working at RF carrier frequencies namely the VCO and the Prescaler.

Reduction of power consumption in VCOs and Prescalers therefore has been the

subject of several publications [13]. The power in prescalers based on master-slave

15


29/97


30/97


In this chapter, we explore this idea of frequency multiplication for low-power

applications like wireless sensor networks (WSN). Since, the phase noise requirement

of the frequency synthesizer can be as high as -71 dBc/Hz at 3.5 MHz offset [7], anoptimal design should take advantage of these relaxed specifications to trade-off power

versus performance. In the case of the frequency synthesizer, lower power can be

achieved by trading it off with increased phase noise or jitter, while still meeting the

overall system level specifications.

PD CP+LF VCO

/2 /2 /2 /2

MultiplierM

Frequency

@Nfref/M@Nfref/2M

@Nfref/M

@ Nfref = foutfref

Nfref/M

Figure 3.3: PLL with a Frequency Multiplier; Here the PLL runs at fout/M wherefout is the desired frequency

RF applications typically use LC-VCOs as they offer good phase noise perfor-mance. While the DC current in the LC-VCO can be reduced to trade-off power and

phase noise, it also reduces the signal amplitude, which adversely affects the mixer

gain. Also for a desired amplitude, the DC bias current cannot be reduced beyond

a point due to the coupled requirements on phase noise, amplitude, frequency of

operation, tuning range and reliable start-up for a given type of oscillator [2,3].

The idea of using a low frequency PLL along with frequency multiplication us-

ing a phase combining technique, suggests an alternative approach to achieve lowerpower, as it eliminates the high frequency VCO and the high frequency dividers. A

low-frequency ring oscillator based VCO generates multiple phases which can then

be combined to generate the high frequency carrier signal. The drawback is an in-

creased phase noise from the ring oscillator based VCO, hence limiting its usage to

applications which can tolerate this higher noise.


31/97

3.2. Frequency Multiplication by Edge-Combining 18

The approaches presented in the literature so far, for achieving this phase com-

bining, are not power efficient and their limitations are discussed in detail in Section

3.2. In Section 3.3, we propose a new, power-efficient edge-combining technique,which enables a low-power frequency multiplication architecture based on simple dig-

ital ring VCOs operating at frequencies much lower than the desired carrier frequency.

Additionally, the lower frequency VCO and PLL can now be operated at a reduced

power supply, saving even more power. We discuss both single-ended and differen-

tial realizations and present some analysis and simulation results quantifying their

performance, followed by discussions on their limitations and applicability in Section

3.4 and conclusions in Section 3.5.

3.2 Frequency Multiplication by Edge-Combining

The PLL in Fig. 3.3 operates at a reduced frequency f0M

where f0 is the desired fre-

quency. The VCO generates multiple phases, and these are combined to generate the

carrier at f0. The VCO operates at f0/M and the first [log2M] number of dividers are

not required leading to power-savings in this PLL. However, the frequency multiplier

has to be designed in a power efficient way so as not to squander away the power

advantage obtained thus.

Ring oscillator based VCOs can conveniently generate multiple phases, but suf-

fer from degraded phase noise compared to LC-VCOs. The phase noise of the fre-

quency multiplied output is further worsened by an amount 20log10M which com-

pensates for the improved phase-noise of the VCO running at a reduced frequency.

Therefore, for cellular applications, frequency-multiplier based PLL employing a Ring

VCO may not be able to meet their stringent phase noise requirements. However for

WSN applications where one can live with much degraded phase noise, a digital ring

oscillator can be used in the PLL. Digital inverter (DI) based ring oscillators have

only dynamic power-dissipation and provide rail-to-rail swing which simplifies the


32/97


L C C L

1P 1N 2P 2N 8P 8N 9P 9N

P N

Out+ Out

ISS

Figure 3.4: Frequency multiplication scheme of Chien et al. (M=9)

design of a low-power edge-combiner. In addition, DI based ring oscillator can use

supply voltage scaling to save power greatly as the dynamic power in such a VCO

varies as NCV2DDf, while for LC-VCOs, the overall power varies only proportionately

with supply voltage. Razavi [4] and Chien [5] have used differential amplifier based

VCOs for which the edge-combiner becomes power hungry. Fig. 3.4 describes the

edge-combiner used by Chien et al. Here, each differential amplifier has a DC tail

current source of its own leading to static power dissipation. Differential amplifiers

also do not provide rail-to-rail swings. As a result, the edge-combiner has to employ

a differential MOS transistor pair as a unit for commutating the tail current. Thetail current sources in all these differential pairs lead to increased static and therefore

overall power.

Recently in a paper by Verma and Lee [6], an innovative method to perform

frequency multiplication was presented. Consider the circuit shown in Fig. 3.5. As a

rising edge propagates through an inverter, for the duration of propagation delay tp


33/97


1 2 3 N

N

N odd

CBA

Figure 3.5: Frequency multiplication scheme of Shwetabh Verma et al.

of the inverter, a current surge passes from the output to the ground node. Here, one

is effectively combining the edges of the input and output waveforms of the inverter.

In one time-period of the ring oscillator, there are N such occasions when a current

pulse is sent to ground. If we tie the ground node of all the inverters, and make the

combined current pulse pass through a LC tank as shown in Fig. 3.5, we can achieve

a frequency N times that of the ring oscillator. The LC tank tuned at NfRO filters

out the out-of-band components producing a sinusoidal waveform of frequency NfRO.

The primary drawback of this technique, however, is that of a poor amplitude.

As one tries to make the inverters wider to increase the magnitude of current pulse

(by reducing series resistance of the NMOS switch), a larger ground bounce reduces

the gate overdrive and increases ON resistance of the switch. When implemented in

0.13 m RF-CMOS process, it is difficult to achieve even 150 mV of voltage swing

using this method and hence, an additional amplifier is needed to get the desired

voltage swing. But amplifying a high-frequency LO signal is costly both in terms of

area and power [8].

In the next section, we will present a new technique to achieve phase combining

in a power efficient way. This technique also provides large amplitude sinusoidal

signals which can be directly used in the mixer without any further amplification.


34/97

3.3. A new method of edge-combining 21

Performance comparison of the proposed circuit vis-a-vis the circuit shown in Fig.

3.5 is presented in section 3.4.

3.3 A new method of edge-combining

Clearly, to work around the above problem of low output amplitude, one has to

decouple the ground node of the ring oscillator from the LC tank [8]. This can be

easily achieved at the expense of some extra power. Consider a 3-stage ring oscillator

shown in Fig. 3.6. The voltage waveforms at nodes A, B and C are shown in Fig. 3.7.

The signals AB, BC and CA, represent the logical ANDing of the waveforms, and aredisplaced from each other by T/3, where T is the time period of the ring oscillator. If

we combine the equally spaced signals (by wire-ORing them), the resultant waveform

will not only be periodic with period T /3 but will also carry the same power as either

of the waveforms at A, B or C. However, the actual power will be somewhat less

considering the finite rise and fall time of the voltages at A, B and C.

A B C

Figure 3.6: 3-Stage Ring Oscillator

An easy technique to perform this logical ANDing with low-power and area cost

is to use MOS switches in cascade as shown in Fig. 3.8(a). Various phases are used

symmetrically so as to present equal load to all ring oscillator phases and preserve thephase symmetry. Fig. 3.8(b) shows a symmetric realization of an arm which helps

realize a uniform ON resistance of each switch cascade. The current from each pair of

switches is made to flow though the LC tank tuned to 3fRO, where fRO is frequency

of the ring oscillator. The tank filters out the frequency components other than the

fundamental. Even though we have illustrated this technique for N = 3, it can be


35/97


T/3

AB AC BC ABCurrent

Waveformt

VA

VB

VC

Combined

Figure 3.7: Voltage waveforms of a 3-stage ring oscillator; T is the time period ofthe VCO shown in Fig. 5

easily extended to any odd number greater than 3. Fig. 3.9 shows the complete

schematic of multiply-by-3 edge-combiner circuit.

C

C

B

AB

A B

B

A

A

(a) (b)

Figure 3.8: (a) An edge-combining switch for M=3 and (b) A symmetric arm

Another thing to observe here is that the tail node P oscillates at frequency f0 =


36/97


N

C

C

B

AB

A

P

L

C

11nH

314fF

6m0.12m

120m0.25m

Vbias

CGD

CDB

Iin

CGS

MCS

Figure 3.9: A single-ended frequency multiplier for M=3; Sizes are shown for targetfrequency of 2.4 GHz implemented in 0.13m technology

MfRO unlike 2f0 in a LC-VCO. For large tail transistor MCS, the oscillations at point

P at frequency f0 get coupled to the gate of MCS through large CGD, modulating the

tail current. At large amplitudes, the oscillations at point P get big enough to drive

MCS periodically into saturation (maximum current) and triode region (minimum

current) giving the tail current a square shape. However, a large tail transistor, due

to large CDB to ground, will degrade PSRR. The circuit will pick more noise from the

substrate and also will inject more switching noise into it (both leading to self-mixing

and saturation of RF-demodulation chain). But, a large tail current source will help

reduce 1/f noise which is upconverted by the switching transistors to 1/f3 close-in

phase noise due to AM-PM conversion mechanism in non-linear varactors [9].

The modulated current waveform along with drain voltage of the tail transistor

is shown in Fig. 3.10. Fig. 3.10(a) shows the 3 phases of the 3-stage ring oscillator.

The voltage waveforms at points P and N are shown in Fig. 3.10(c). The current

injected into the switches (Fig. 3.9) is shown in Fig. 3.10(b).

The amplitude of oscillation, going by the square shape of the current, can be


37/97


estimated from the magnitude of the fundamental harmonic as

VAmp =2IPeak

RP (3.1)

where RP is Tank impedance at resonance.

For RP = 1.25 ks and IPeak = 550 A. (3.1) gives VAmp=475 mV which is

close to the simulation results of VPP = 950 mV shown in Fig. 3.10. For any

multiplication factor, the average current drawn from the supply is about 465 A.

The average current consumed by the ring oscillator is 171 A and that used (Iavg)

by the multiplier is 278 A. To compare it with current-reuse LC-VCO for the same

value of L and center frequency [2],

VAmp,LCVCO =4Iavg

RP = 442.5 mV (3.2)

Equivalently, this structure is as power efficient as the current-reuse LC-VCO

for conversion of DC current to output amplitude. Due to extra power in the ring

oscillator, for the same output swing of 450 mV, the proposed structure consumes a

total of 465 A as against 278 A of LC-VCO. In other words, for M=5, effectively,

we are replacing the dividers working at 2.4 GHz and 1.2 GHz with a 5-stage ring

oscillator working at 480 MHz. Phase noise of the LC-VCO is -110 dBc/Hz as against

-85.5 dBc/Hz of frequency-multiplying oscillator at 1 MHz offset for the same out-

put amplitude of 475 mV. At 3.5 MHz offset, the phase noise is -99.7 dBc/Hz. The

degraded phase noise is due to the poor phase noise characterstic of ring oscillators.

Size of switch MOSFETs is chosen as a compromise between small IR drop

(larger swing) and higher power dissipation in the ring oscillator (due to larger

load capacitance.) Also with large switches, parasitic capacitances (CGD and CDB

of top NMOSes become a significant part of the total capacitance and it being time-

dependent distorts the waveform at node N.

The voltage swing at point N cannot be increased arbitrarily due to reliability


38/97


5.1 5.12 5.14 5.16 5.18 5.2 5.22

0

0.5

1

Volta

ge

(in

vo

lts)

5.1 5.12 5.14 5.16 5.18 5.2 5.22

0

500

ITank

(inAs)

950mV

5.1 5.12 5.14 5.16 5.18 5.2 5.220

1

2

Voltage

(in

volts)

Time (in seconds)

N

P

108

108

950mV

108

A

BC

Figure 3.10: Various voltage and current waveforms in circuit shown in Fig. 3.9.(a) shows the three phases of the ring oscillator for the multiplication factor M=3.(b) shows the current through the tail transistor MCS and (c) contains the voltagewaveforms at Node N and tail node P

concerns. The common mode voltage at N is VDD (to be precise, little less than VDD,

allowing for small drop in small series resistance of the inductor). A VGD for the top

NMOS switch much larger than VDD will cause gate oxide breakdown. In 0.13 m

technology with 1.2 V supply voltage, one should limit the amplitude to about 450 mV.

3.3.1 Differential Operation

To avail the inherent benefits of rejection of common mode noise and even harmonics,

differential or balanced operation is always preferred over the single-ended one. To


39/97


A A1 B B1

A

A1

B

B1

(a)

In Out

0.8m

0.2m

0.4m

0.2m

(b)

Figure 3.11: (a) Differential 3-Stage Ring Oscillator [6] (b) A unit inverter

generate differential high frequency signals, low-frequency RO must also generate

differential signals. There are two ways to do this. 1. Differential ring oscillator with

two or more differential amplifiers in feedback loop or 2. Coupled digital inverter-

based ring oscillators. Razavi [4] and Chien [5] used the first choice. Here the edge-

combiner has to employ a differential MOS transistor pair as a unit to switch the tail

current. These tail currents lead to static power dissipation and therefore increase

overall power.

On the other hand, digital inverter-based cross coupled ring oscillators only

dissipate dynamic power and provide rail to rail swing which can be used to completely

turn-ON and OFF the simple MOS switches in the frequency multiplier. A simple

MOSFET based switch being the highest speed switch available in a given technology,


40/97


the circuit can be used for very high frequencies with a suitable microwave resonator

replacing the LC-tank.

The N-stage (N-odd) differential RO consists of 2, N-stage single-ended ROs,with each stage comprising of 3 inverters. One inverter from each stage is cross-

coupled to force corresponding nodes in the two ring oscillators to be mutually com-

plementary. It is clear that for the same frequency of operation, increased number

of inverters (3-times in this case) compared to a 3-stage oscillator, does not lead to

higher power as the load driven by each inverter reduces by the same factor. This

also allows for lowering the VCO gain as one of the three inverters in very stage can

be tuned without disturbing the symmetry of the various phase of the ing oscillator.In addition, the larger number of inverters will average out the random component of

process mismatch helping in improving the carrier-to-spur ratio (CSR) in the multi-

plied output and is further discussed in the next section. Effect of this choice on the

phase noise will also be discussed in the next section. A simple differential realiza-

tion will have two copies of the circuit in Fig. 3.9 with each switch bank driven by

complementary nodes of the differential ring oscillator of Fig. 3.11(a).

Since the two switch banks are complementary, switching the tail current alter-

nately, a single tail current source can be used leading to an important power saving

(current re-use). We can also reuse a single inductor by connecting it across the two

differential nodes N1 and N2 saving an inductor (reducing area, therefore cost, to half)

leading to the final differential structure shown in Fig. 3.12 which is both area and

power efficient. The cross-coupled PMOS pair at the top helps limit the oscillations

at nodes N1 and N2 below the supply voltage. However in this conversion, we have

lose one advantage of single-ended structure viz. the tail node being a common mode

point now oscillates at frequency 2f0. And a large current source transistor (big drain

junction-capacitance) used to reduce 1/f noise provides a small impedance at 2f0 to

ground which degrades the LC-tank by allowing gds of the triode region switch MOS

to load the tank [10].


41/97


N1

B

A

N2

CC

L

MCSVBias

SB

Cpar Cpar

AS

M2M1

20m0.18m

11nH 607fF607fF

IDC = 300A

36m0.18m

Figure 3.12: Frequency multiplier with differential output. Component values shownare for 0.13 m technology and 2.4 GHz center frequency. S and S represent thecomplementary switches

A significant advantage of this structure is that unlike LC-VCO, it does not

require a minimum bias current for reliable start-up. The NMOS switches, S and S,

will ensure the current switching irrespective of the value of the current and size of

the cross-coupled PMOS pair at the top.

Output voltage amplitude as in the case of LC-VCO is given by

VAmp =4

IDCRP (3.3)

For the circuit shown in Fig. 3.12 working at 2.4 GHz, total current drawn from

the supply is 595 A of which 201 A is spent in the ring oscillator of Fig. 3.11(a).

The inverters in the ring oscillator are sized as (W/L)PMOS = 0.8 m/0.2 m and

(W/L)NMOS = 0.4 m/0.2 m. Average current drawn by the intermediate buffers is

73 A. The buffers have the same size as that of the inverters in the ring oscillator.

As one increases the size of cross-coupled PMOS pair to reduce its gate over-


42/97


drive for supporting the IDC and therefore delay the onset of the voltage-controlled

regime, an interesting thing happens; The cross-coupled PMOS pair M1 M2 gener-

ates enough negative resistance to more than compensate the losses in the LC-tankcreating an LC oscillator by providing sufficient start-up gain. However, the circuit

continues to function faithfully as a frequency multiplier as the strong switched-

current signal at 3fRO will injection-lock the LC-VCO. Injection-locking being a

narrow-band phenomenon would restrict the correct operation to its lock-bandwidth.

Therefore one must restrict the size of M1 M2 to have sufficient bandwidth of oper-ation. For example, a 70 m/0.18 m sized PMOS pair limits the injection lock range

to 2.112.64 GHz frequency band.It should be noted that nothing prevents the use of this frequency multiplication

scheme for a wideband operation. A small varactor can be used to tune the ring

oscillator (with, say, f as tuning range). However frequencies away from the centre

frequency of the LC-tank (tuned at 3fRO) will suffer attenuation. For wideband

operation, a strong varactor or a switched-capacitor bank [11] can be used in the

LC-tank. A strong varactor has problems related to high sensitivity (large gain) to

noise on the control voltage signal. It also gives rise to AM-to-PM conversion owing

to large VCO swing pushing the operation of varactor deep into the non-linear regions

of its CV curve [12]. Switched-capacitor bank scheme, on the other hand, degradesthe Q of the LC-tank due to finite on-resistance of the MOS switches [13].

For large amplitudes of the oscillation, we run into instability problems due to

back-coupling (CPar in Fig. 3.12) from multiplier-oscillator to the ring VCO though

CGD of the top switch transistors as shown. The circuit is a two-way coupled system of

two oscillators and has more than one solution (frequency and amplitude pairs). This

is analogous to the case of familiar cross-coupled LC-VCOs generating quadrature

phases, where we encounter three possible solutions (three frequency and amplitude

pairs) [14] and the highest frequency is chosen as it leads to highest loop gain due

to largest tank impedance at this frequency (discussed in detail in Chapter-6). In


43/97


0 0.2 0.4 0.6 0.8 10

100

200

300

400

500

600Amplitude of high frequency output

Tuning voltage (in volts)

Amplitude(inmVs)

Band

ofInterest

541mV

501mV479mV

448mV

VDD=1.2V

VDD=1.0V

Band

ofInterest

(a)

0 0.2 0.4 0.6 0.8 11.5

2

2.5

3

Tuning Curve


Frequency(inGHZ)

2.405 GHz

2.485 GHz

Band of Interest

VDD=1.2V

VDD=1.0V

(b)

0 0.2 0.4 0.6 0.8 195

90

85

80

75

70Phase Noise at high frequency output


PhaseNoise(indBc/Hz)at1MHzoffset

Band

ofInterest

VDD=1.0 V

VDD=1.2V

VDD=1.2V

10dB

Output of ringoscillator

Output of frequencymultiplier

Band

ofInterest

(c)

Figure 3.13: (a) Amplitude (b) Tuning curve and (c) Phase Noise for circuit shownin Fig. 3.12 for 2.4 GHz ZigBee band, M=3 using symmetric arms (Fig. 3.8(b))anddifferential realization (Fig. 3.12)

our case as the amplitude of oscillations is increased, a point comes when the system

suddenly switches to the other mode of the oscillation (even though, frequency mul-

tiplication still holds good) with a different pair of frequency and amplitude. Clearly,

this is an undesirable situation. To eliminate such possibility, one must provide suffi-

cient reverse isolation, i.e. from multiplier to the ring oscillator. This is easily done

by putting buffer inverters after the ring oscillator, driving the switch MOSFETS.


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3.4. Discussions 31

RO buffers are anyway necessary to avoid disturbing the phase symmetry that would

otherwise be caused due to loading by the frequency divider in the PLL [15].

3.4 Discussions

All the circuits were simulated in SpectreRF using a commercial 0.13 m RF-CMOS

technology with MIM capacitor option. Fig. 3.13 shows the amplitude, tuning and

phase noise curves for differential realization of Fig. 3.12 and multiplying factor M=3,

for the example case of 2.4 GHz ZigBee band. The differential ring oscillator (Fig.

3.11(a)) is tuned using inversion-mode MOS capacitors. The 2.4 GHz ZigBee bandis covered by varying the tuning voltage from 0.5 to 0.58 V. For 2.45 GHz output

frequency, M=3, and IDC = 300 A, the peak amplitude is 550 mV and phase noise

of the frequency multiplied output is -84 dBc/Hz at 1 MHz offset which is about

20log103 10 dB worse as compared to the ring oscillator. The thermal noise of theswitches is upconverted to fRO and is filtered out by the LC-tank tuned at 3fRO and

therefore does not degrade the phase noise at the output further.

Table 3.1 summarizes the performance of a single-ended multiplier versus that

of the S. Verma et al. for the same center frequency of 2.45 GHz, identical LC-

tank and 0.13 m RF-CMOS technology. For the comparable phase noise and same

multiplying factor of 3, the total current required by our approach is 458 A which is

2.86 times that needed by [6]. However the output voltage amplitude in our case is

451 mV which is 5.8 times that obtained by Shwetabh Verma et al. which underlines

the power efficiency of the proposed technique.

3.4.1 Effect of ground bounce

An important issue to be considered in high-frequency single-ended realizations is

the effect of ground bounce resulting from large bond-wire inductance. Since the

single-ended circuts do not enjoy the presence of virtual ground, their performance


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3.4. Discussions 32

Table 3.1: Performance Comparison[6], M=3 This Work,

M=3This Work,M=5

Amplitude 77.8 mV 451 mV 457.7 mVCurrent drawn fromsupply

160 A 45 8A 465.8 A

Phase Noise (dBc/Hzat 1 MHz offset)

-85.7 -83.3 -88.5

Phase Noise (dBc/Hzat 3.5 MHz offset)

-100.1 -97.5 -102.8

Frequency 2.45 GHz, L=11 nH and 0.13 m technology

is adversely affected by the supply and ground bounces. While the bounce on the

VDD line can be alleviated by tuning out the bond-wire inductance by placing large

de-coupling capacitors, nothing can be done about the ground bounce. For the circuit

shown in Fig. 3.9, since the current at 2.4 GHz is just 272 A, the bounce due to 5 nH

bond-wire is L I = 21 mV which is quite small. The current injected by thering oscillator working at 800 MHz causes only 172 A 2 800MHz 5 nH = 4.3 mVoscillations on the ground node which is again negligible.

3.4.2 Effect of mismatches in the ring oscillator

Mismatches between the inverters of the ring oscillator lead to delay mismatches

between various adjacent phases of the ring oscillator. This in turn leads to spurs in

the frequency multiplied output. Fig. 3.14 illustrates the various tones present at the

output of the multiplier. Even though the tone at 2MfRO is largest in power after

the desired signal, tones at (M 1)fRO are most dangerous as RF signal at thesefrequencies suffers much less attenuation by the band-select filter compared to that

at 2MfRO. Fig. 3.15 shows the Carrier-to-spur ratio (CSR) in dB for circuit shown

in Fig. 3.12, obtained using Monte-Carlo analysis and mismatch data provided by

the foundry. For N=1000, VT,N = 5.5%, VT,P = 2%, ,N = 10% and ,P = 6%,


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3.4. Discussions 33

a minimum CSR of 40 dB (only for 0.8% cases) was obtained. CSR for differential

circuit (Fig. 3.12) is presented in Fig. 3.16 for the same values of process variations

and N=2000. Here the minimum CSR was found to be 42 dB (only for 0.44% cases).

CSR

Spurs

fRO fRO

MfRO 2MfROf

Figure 3.14: Spurs at the frequency multiplied output. fRO is ring oscillator frequencyand M, the multiplication factor

30 40 50 60 70 800

20

40

60

80

100

120

140

160

180Mismatch Analysis

CarriertoSpur Ratio (in dB)

No.ofoccurences

Figure 3.15: Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using MonteCarlo analysis, N=1000, VT,N = 5.5%, VT,P = 2%, ,N = 10% ,P = 6% and M=3


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3.4. Discussions 34

30 40 50 60 70 800

50

100

150

200

250

300

350Mismatch analysis for differential realization

Carriertospur (in dB)

No.ofoccurances

Figure 3.16: Carrier to Spur Ratio (CSR) for circuit shown in Fig. 3.9 using MonteCarlo analysis, N=2000, VT,N = 5.5%, VT,P = 2%, ,N = 10% ,P = 6% and M=3

3.4.3 Choice of multiplication number, M

As discussed in section 2, values of M greater than 5 do not result in any significant

power saving. A large M rather leads to a larger number of phases in ring oscillator

leading to increased level of spurs (at fRO due to more mismatches. Also as the

spurs come closer to the desired frequency (as shown in Fig. 3.14), it suffers lesser

attenuation by the LC tank. It is therefore sufficient to discuss the case of M = 3

and 5.

The amplitude, phase noise and the tuning curves for differential realization,

M=3 and ZigBee band of 2.4 GHz are shown in Fig. 3.13.The expressions of SSB phase noise for a ring oscillator due to white and flicker

noise are respectively given by [16]

L(f) = 2kTI

1

VDD Vt (N + P) +1

VDD

f0f

2(3.4)


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3.4. Discussions 35

L(f) = 14M(VDD Vt)2

KfN

WNLN+

KfPWPLP

f20f3

(3.5)

where f0 is the frequency of ring oscillator, approximated by

f0 I/CMVDD

assuming square law

f0 CoxW2CLM

(VDD Vt)2VDD

(3.6)

Where N and P are thermal noise coefficients and KN and KP stand for flicker

noise coefficients. C is the total load on each ring oscillator node and M, the number

of stages in the ring oscillator.

For M = 5, RO runs at a lower frequency f0/5 leading to reduction of phase

noise (caused by both flicker and white noise) by 10log10(5) 15 dB. When multipliedin frequency, it worsens by the same factor leading to no net change in the phase noise.

Also observe that the use of larger number of inverters (3 per stage) does not

affect the phase noise of the ring oscillator; The number of stages, M, does not appear

in equation (3.5) while in (3.6) the product MW L (total capacitative load) remains

constant for any other M but the same frequency. In addition, the noise current

sources of switch transistors get modulated by their gate voltage at frequency fRO,

which gets filtered out by the LC-tank tuned at 3fRO.

3.4.4 Voltage scaling

The large tuning range of ring oscillator can be alternatively utilized to reduce power

by lowering the supply voltage. As the supply voltage is lowered, a larger tuning

voltage can be used to restore the ring oscillator to the old frequency. The circuit

in Fig. 3.12 can be run down to 1 V supply voltage for 2.4 GHz frequency band of

ZigBee transceiver. For this circuit and M=3, at VDD = 1V and 2.4GHz, the total


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3.5. Summary 36

average current from the supply is 475 A resulting in 20% saving in power.

Fig. 3.13 also captures the effect of supply voltage scaling on the amplitude,

tuning curve and phase noise for circuit shown in Fig. 3.12 and M=3. For VDD =1.0 V, the amplitude reduces due to higher IR drop in the switches as their resistance

(1/(n(VGate Vt VDS))) goes up due to lower voltage on their gates (Fig. 3.13(a)).(3.6) predicts that f1.0 = 0.75 f1.2. For VDD = 1.0 V, the ring oscillator slows downand the band of interest (2.4052.485 GHz) is now covered by applying higher tuning

voltage (0.850.95 V)(Fig. 3.13(b)).

As the switches contribute little to the phase noise of the multiplied output,

their increased resistance at VDD = 1.0 V does not degrade the output phase noise(Fig. 3.13(c)). Since the flicker noise corner frequency is around 5 MHz, phase noise

at the output at 1MHz offset has 1/f3 characterstic. Assuming square law (ID (VGSVt)2) for transistors in the ring oscillator, (3.5) predicts that for a given tuningvoltage, phase noise of the ring oscillator at 1 MHz offset will vary as proportional

to f20 /(VDD Vt)2. Since (from (3.6)) f0 varies as (VDD Vt)2/VDD, L(f) will varyroughly as (VDD Vt)2/V2DD. This predicts that L1.0 is lower than L1.2 by 0.47 dB

for the same Vtune as seen in the (Fig. 3.13(c)). Near the peak of the LC tank, the

phase noise curve takes a slight dip for both VDD = 1.2V and 1.0V. For the same

output frequency of 2.45 GHz, L varies as 1/(VDD Vt)2 and therefore L1.0 is worsethan L1.2 by 2.0 dB.

3.5 Summary

We have proposed a new low-power frequency multiplication technique based on edge-

combining. The technique can be used to reduce power in a PLL based frequency

synthesizer. Design trade-offs involved in design of a low-power edge-combiner have

been developed. Also a design example is presented for 2.4 GHz ZigBee transceiver

which consumes only 550 W of power from 1.2 V supply. Both single-ended and


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3.5. Summary 37

differential realizations have been developed. Using mismatch data provided by a

commercial technology, Monte-Carlo simulations carried out in SpectreRF show that

spur suppression upto 40 dB can be easily achieved. The edge-combiner being basedon simple MOS transistor (MOST) switches controlled by a digital ring oscillator,

voltage scaling can be employed to save power upto 20%. Use of simple MOST

switches as against current-commuting differential MOST pair allows not only lower

power, but also high speed and can be used to design oscillators close to fT of a

technology with a suitable resonator replacing the LC-tank.


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References

[1] Marc Tiebout, A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider, IEEE Journal of Solid-State Circuits,vol. 39, no. 7, July 2004

[2] Ali Hajimiri, Thomas H. Lee, Design issues in CMOS differential LC Oscillators,IEEE Journal of Solid-State Circuits vol. 34, no. 5, pp. 717-724,May 1999

[3] Donhee Ham, Ali Hajimiri, Concepts and methods in optimization of integrated

LC VCOs, IEEE Journal of Solid-State Circuits vol. 36, no. 5, pp. 896-909, June2001

[4] Behzad Razavi and JanMye James Sung, A 6 GHZ 60 mW BiCMOS phase-lockedloop, IEEE Journal of Solid-State Circuits vol. 29, no. 12, pp. 1560-1565, Dec1994

[5] George Chien and Paul R. Gray, A 900 MHz local oscillator using a DLL-basedfrequency multiplier technique for PCS applications, IEEE Journal of Solid-StateCircuits vol. 35, no. 12, Dec 2000

[6] Shwetabh Verma, Jenfung Xu, Thomas Lee, A multiply-by-3 coupled-ring os-cillator for low-power frequency synthesis, IEEE Journal of Solid-State Circuitsvol. 39, no. 4, April 2004

[7] Nam-Jin Oh, Sang-Gug Lee, Building a 2.4 GHz Radio Transceiver Using IEEE802.15.4, IEEE Circuits and Devices Magazine, pp. 43-51, Nov/Dec 2005.

[8] J. N. Pandey, Sudhir Kudva and Bharadwaj Amrutur, A low-power frequencymultiplication technique for ZigBee transceiver, IEEE Int. Conf. on VLSI DesignJan 2007

[9] J. J. Rael and A. A. Abidi, Physical processes of phase noise in differential LC

oscillators, IEEE Custom Integrated Circuits Conference 2000

[10] Emad Hegazi, Henrik Sjoland, Asad A. Abidi, A filtering technique to lower LCoscillator phase noise,IEEE Journal of Solid-State Circuits vol. 36, no. 12, pp.1921-1930, Dec 2001

[11] A Kral, F. Behbahani and Asad A. Abidi, RF-CMOS oscillators with switchedtuning Proc. IEEE Custom Integrated Circuits Conference, Santa Clara, CA,1998 pp. 555-558

38


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References 39

[12] Emad Hegazi, Asad A. Abidi, Varactor characterstics, oscillator tuning curves,and AM-FM conversion, IEEE Journal of Solid-State Circuits vol. 38, no. 6, pp.1033-1039, June 2003

[13] Henrik Sjoland, Improved switched tuning of differential CMOS VCOs, IEEETransactions of Circuits and SystemsII vol. 49 no. 5 May 2002

[14] Rofougaran, Single-chip 900 MHz spread-spectrum wireless transceiver in 1 mCMOSPart 1: Architecture and transmitter design, IEEE Journal of Solid-State Circuits vol. 33, no. 4, April 1998

[15] Shenggao Li, Issy Kipnis and Mohammed Ismail, A 10 GHz CMOS quadratureLC-VCO for multirate optical applications, IEEE Journal of Solid-State Circuitsvol. 38, no. 10, pp. 1626-1634, April 1998

[16] Asad A. Abidi, Phase noise and jitter in ring oscillators, IEEE Journal ofSolid-State Circuits vol. 41, no. 8, pp. 1803-1816, August 2006


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41

N

Vbias

MCS

11nH

314fF

6m0.12m

120m0.25m

P2

P1

A1

B1

B1

C1

C1

A1

A A1 A2 B B1 B2

CC1C2

(a) (b)

Figure 4.1: (a) Single-ended frequency multiplier for M=3 and (b) The low frequencyring oscillator; NMOS is sized 2 m/0.2 m and PMOS is sized 4 m/0.2 m.

C

A B

A1 B1

B1 B2

C1 B1

C1C2

C1A1

A1 A2

Figure 4.2: Symmetric floor plan for layout of the multiply-by-3 circuit.

arrangement of inverters and switches.

Foundry supplied circular planar inductor has been used. Common centroid

layout of the current source has been done.


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4.1. Simulation of layout extracted netlist 42

Figure 4.3: Layout of the ring oscillator and cascaded switches; Inductor, capacitor

and tail current source in the full multiplier circuit are not shown here in order toclearly display the arrangement of inverters and switches.

4.1 Simulation of layout extracted netlist

To compensate for the extra layout parasitics, we had to increase the size of invert-

ers from (PMOS 1.5 m/0.2 m, NMOS 0.75 m/0.2 m) to (PMOS 4 m/0.2m,


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4.1. Simulation of layout extracted netlist 43

NMOS 2 m/0.2 m) in order to cover the tuning range of 2.0GHz to 3.0GHz.

Consequently the power consumption has gone up to 766 A from 478 A obtained

from the schematic simulation. This of course has improved the phase noise to -104.2 dBc/Hz at 3.5 MHz offset and has helped with CSR since the larger area of

inverters leads to less mismatch. The whole multiplier is able to run down to 1 V of

VDD while meeting the desired frequency and phase noise targets.

Table-4.1 summarizes the performance of the circuit obtained from SpectreRF

simulation of the layout-extracted netlist. The circuit is able to operate from supply

voltage upto 1.0 V while covering the 80 MHz wide ZigBee band at 2.4 GHz center

frequency. At VDD = 1.0 V, the circuit draws 495 A of current from the supplywhile the amplitude at the FM output drops to 317 mV due to larger IR drop in the

switches.

Table 4.1: Performance SummaryThis Work, M=3,VDD=1.2 V

This Work, M=3,VDD=1.0 V

Amplitude 452 mV 317 mVCurrent drawn from

supply

766 A 495 A

Phase Noise (dBc/Hz at1 MHz offset)

-90.4 -82.5

Phase Noise (dBc/Hz at3.5 MHz offset)

-102.4 -94.6

Frequency 2.45 GHz, L=11 nH and 0.13 m technology

After considering the worst case mismatch between inverters, the worst-case

CSR is found to be 34 dB which is 6 dB lower than that obtained from the schematic

simulation.


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Chapter 5

Quadrature Generation Methods

For Frequency Multiplication

Based Oscillators

This chapter compares two methods of generating low-power quadrature sinusoidsfor oscillators based on frequency multiplication. The first method involves an evenstage ring oscillator running at lower frequency and uses appropriate edge-combiningto generate the quadrature signals. The second method simply employs a polyphasefilter after the differential frequency multiplier. To achieve low-power of operation,power-hungry buffers are excluded by design optimization. For high quadratureprecision, injection-locking property of quadrature oscillators which desensitizes theI Q imbalance, as originally proposed by Kinget et al. is exploited. SpectreRFsimulations indicate that the second method uses moderately high power and area

for comparable amplitude and phase noise, and yields very small phase error whichis unachievable using the first method.

5.1 Introduction

IN image-reject radio receiver architectures, precision of the quadrature LO often

limits the achievable image cancellation. The accuracy of amplitude and phases of

quadrature signals is limited due to the presence of process variations in both active

and passive devices in modern CMOS technologies. This has made the task of on-chip

high-precision RF LO generation very hard.

A measure of quadrature amplitude and phase accuracy is given by Image-reject

Ratio (IRR) defined as (Pim/Psig)Out normalized to (Pim/Psig)In , where Pim and Psig

44


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are image and signal powers respectively. For small mismatch in amplitude, A and

phase imbalance, , IRR can be written as [1]

(A/A)2 + 2

4(5.1)

An IRR of about 35 dB is found sufficient which translates to roughly 2.5% of

amplitude mismatch and 1.5 of phase imbalance. However (5.1) is valid for an ideal

multiplicative mixer and small A and . For a hard-switching mixer, effect of A

is much reduced and phase error, limits the IRR. Ignoring the effect of amplitude

mismatch, phase mismatch must be limited to 2 to achieve 35 dB of IRR.

This chapter compares two methods of quadrature generation for oscillators

based on the concept of frequency multiplication that works on the principle of edge-

combining. The first method involves using an even-stage ring oscillator [8] which

generates a set of low-frequency edges that can be judiciously combined by two edge-

combiners to generate the respective multiplied I and Q signals. The second method

uses a polyphase filter following the edge-combiner to generate the quadrature phases.

This can be optionally followed an injection-locked QVCO (IL-QVCO) to achievebetter quadrature accuracy [9].

Section 5.2 evaluates the method of quadrature generation based on edge-

combining the phases from an even-stage ring oscillator. Section 5.3 discusses the

technique of using polyphase filter for quadrature LO generation and brings out the

issues involved in its design, particularly the effect of exclusion of buffers. Section

5.4 addresses the issue of high-precision quadrature generation and discusses I-Q

imbalance desensitization scheme based on injection locking, originally proposed byKinget et al. [9]. Conclusions are drawn in section 5.5.


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5.2. Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator 46

A7 A8 A9 A10 A11 A12

A2 A3 A4 A5 A6A1

I1

I2 I3I4 I5 I6 I7

I9I8 I10 I11 I12

Figure 5.1: Six stage differential ring oscillator of Junfeng Xu et al. [8]. Size ratioof cross-coupling inverters to ring inverters is kept at 0.6.

5.2 Quadrature Frequency Multiplication Using

Even-Stage Ring Oscillator

5.2.1 Combining Current Pulses

1 5 9 2 6 10 3 7 11 412 8

QNINQPIP

CL

VDD

Coupled Inverter Ring Oscillators @ 800 MHz

L=11nH

C=320 fF

Figure 5.2: Frequency multiplier of Xu et al. [8] that combines current pulses froma low-frequency ring oscillator. The 12 inverters in the ring oscillator are groupedinto 4 sets with each having 3 inverters. Power nodes of each inverter in a set areconnected to an LC-tank.

To generate I and Q signals from a edge-combiner, one would require N equally


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5.2. Quadrature Frequency Multiplication Using Even-Stage Ring Oscillator 47

spaced phases from the ring oscillator where N is the minimum-common factor of

4 and M, M being the desired factor of multiplication. While even stage RO is

convenient to design using diffential amplifier as a unit, the edge-combiner for suchRO, as brought out in chapter-3 is not power efficient. Recently Xu et al. [8] have

published even-stage RO based on digital inverters that makes the design of low-

power quadrature edge-combiner a feasibility. Fig. 5.1 shows a 6-stage differential

ring oscillator (DRO) intended to achieve quadrature multiplication by a factor of 3.

The quadrature frequency multiplier (QFM) proposed by Xu et al. [8] is shown in

Fig. 5.2. It uses four sets of top nodes (VDD) of 3 inverters each in the ring oscillator,

each tied to an LC-tank. Current pulses from each of the 3 inverters are drawn fromthe supply as the corresponding inverters go through a 1 0 transition. Each tankis tuned at frequency MfRO which filters out the harmonics in the combined current

pulse.

Even though the edge-combiner is built into the ring oscillator itself and does

not require any extra transistors, the circuit suffers from the fundamental limitation

of small voltage swing at the high-frequency output. When implemented in 0 .13 m

technology, it coul

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