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LOW NOISE LOW OFFSET OPERATIONAL AMPLIFIER FOR
NANOPORE-BASED GENE SEQUENCER
By
Zhineng Zhu
B.S. Hefei University of Technology, 1998
A THESIS
Submitted in Partial Fulfillment of the
Requirements for the Degree of
Master of Science
(in Electrical Engineering)
The Graduate School
The University of Maine
May, 2007
Advisory Committee:
David E. Kotecki, Associate Professor of Electrical and Computer Engineering,
Advisor
Donald M. Hummels, Professor of Electrical and Computer Engineering
Rosemary Smith, Professor of Electrical and Computer Engineering
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LIBRARY RIGHTS STATEMENT
In presenting this thesis in partial fulfillment of the requirements for an advanced
degree at The University of Maine, I agree that the Library shall make it freely availablefor inspection. I further agree that permission for fair use copying of this thesis for
scholarly purposes may be granted by the Librarian. It is understood that any copying
or publication of this thesis for financial gain shall not be allowed without my written
permission.
Signature:
Date:
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LOW NOISE LOW OFFSET OPERATIONAL AMPLIFIER FOR
NANOPORE-BASED GENE SEQUENCER
By Zhineng Zhu
Thesis Advisor: Dr. David E. Kotecki
An Abstract of the Thesis Presented
in Partial Fulfillment of the Requirements for the
Degree of Master of Science
(in Electrical Engineering)
May, 2007
A nanopore-based gene sequencer generates a modulated current signal with the
expected magnitude to be in the range of several pico-amps to a nano-amp, and the
bandwidth up to 10MHz. To detect such a weak signal, an ultra-low noise, low offset,
high precision CMOS operational amplifier is designed in a 0.35m CMOS process.
Most of the literature on low noise amplifier design emphasizes flicker noise
reduction. This research analyzed and optimized a proposed differential pair and opera-
tional amplifier, with both the flicker noise and the thermal noise minimized simultane-
ously. The size of each MOSFET is optimized, making the input pair the only dominant
noise source. The input pairs bias current is maximized to reduce the thermal noise.
Also this bias current is rationed between the active current source load and the current
mirror load. This ration of bias current makes the optimization of the amplifiers noise
performance and DC gain separated, which is often a trade-off in normal operational
amplifier design. An operational amplifier with the input-referred voltage noise Power
Spectral Density (PSD) of less than 2nV/
Hzfor frequencies above 1MHz is realized.
The DC gain of this amplifier is up to 120dB. The extra bias current and the cascode
structure also result in a high speed design: the unity gain bandwidth of this operational
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amplifier is more than 200MHz with 20pF loading, providing a sufficient close loop gain
in the MHz range.
CMOS operational amplifiers generally have a higher offset voltage than bipolar
ones. In this design, a digital offset trimming method is studied and used to cover 10mV
input-referred offset. Its effect on noise performance is minimized. This method is
suitable for low voltage and continuous mode applications.
Power Supply Rejection Ratio (PSRR) is an important parameter for the low
noise operational amplifier. The PSRR limitation of the taped-output operational am-
plifier with common source output stage is analyzed. An operational amplifier with
cascode compensation scheme is studied, which shows the potential improvement in
PSRR.
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ACKNOWLEDGMENTS
A special thanks to my wife, Ming Luan, for her constant support and encour-
agement.I would like to express my sincere gratitude to Professor Kotecki for his guidance
and assistance throughout the course of this research work. Thanks to Professor Collins
and Professor Smith for their advices and support. Thanks to Professor Hummels for
the time and reviewing my thesis. Thanks to Steve for his kindly help in the CAD and
chip testing. Thanks to Sanjeev, Alma and Bingxin for their discussions and happy time
in the past two years.
This work was supported by the National Institutes of Health, Bethesda, MD,
under contract 5R01HG003565-03.
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TABLE OF CONTENTS
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ii
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . v
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . vi
Chapter
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 1
1.1. Background . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1
1.2. Purpose of this Research. . . . .. . . . .. . . . .. . . . . .. . . . .. . . . . .. . . . .. . . . .. . . . .. . . . . .. 2
1.3. Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Noise in MOSFETs and Basic CMOS Operational Amplifiers. . .. . .. . .. . .. . .. . .. . 6
2.1. Noise Sources in MOSFETs. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . . 6
2.1.1. Thermal noise in the channel . . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . . 6
2.1.2. Flicker noise in the channel. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . . .. . . . .. 7
2.1.3. Noise of polysilicon gate resistance . . . . .. . . . .. . . . . .. . . . .. . . . . .. . . . .. 8
2.1.4. Noise from the distributed substrate resistance . . . . . . . . . . . . . . . . . . . . . 10
2.2. Noise Performance of the CMOS Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Novel Structure for a Low Noise Operational Amplifier using MOSFETs . . . . .. . 18
3.1. Noise Analysis of New Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 203.1.1. The noise contribution of the input stage M1,2 . . . . . . . . . . . . . . . . . . . . . 213.1.2. The noise contribution of the active current source load M3,4 . . . . . 213.1.3. The noise contribution of current mirror load M7,8 . . . . . . . . . . . . . . . . 223.1.4. The noise contribution of cascode stage M5,6 . . . . . . . . . . . . . . . . . . . . . . 223.1.5. The noise contribution of current bias MOSFET M0 . . . . . . . . . . . . . . 233.1.6. Total output noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 24
3.2. Noise Reduction Techniques for this New Structure . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1. Determination of the input pair type for M1,2 . . . . . . . . . . . . . . . . . . . . . . 253.2.2. Optimization of the bias current ID2 of the input pair . . . . . . . . . . . . . . 263.2.3. Optimization of the sizes and aspect ratios of MOSFETs. . . . . . . . . . 26
3.2.4. Noise performance of the folded-cascode differential pair. . . . . . . . . 293.3. DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 29
3.4. AC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31
3.5. Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 35
3.6. Offset Reduction and Auxiliary Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 35
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4. Testing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 47
4.1. Tape-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 47
4.2. Noise Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3. PCB Board Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4. Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50
4.4.1. Input Common Mode Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 504.4.2. Output Voltage Swing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 54
4.4.3. Transient Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 54
4.4.4. AC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 55
5. PSRR of Low Noise Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 59
5.1. Modified Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2. PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 59
6. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 64
6.1. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 64
6.2. Future Work. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 65
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 68
BIOGRAPHY OF THE AUTHOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 70
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LIST OF TABLES
Table 3.1. Optimized devices size of the two-stage operational ampli-
fier . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 31
Table 3.2. MOSFETsaspect ratio in the bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36
Table 4.1. Operational amplifiers or their first stage included in the
chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 49
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LIST OF FIGURES
Figure 1.1. Nanopore gene sequencing . . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . .. . . . . .. . . . .. 2
Figure 1.2. Typical input-referred voltage noise PSD for a MOSFET . .. . . . . .. . . . . . 4
Figure 2.1. MOSFET noise model: a) Model of thermal noise in the
channel, b) Input-referred voltage noise model . . . . .. . . . .. . . . .. . . . .. . . . . 7
Figure 2.2. Reduction of gate noise through layout, a) single-finger MOS-
FET, b) single-finger MOSFET with contact at both ends, c)
multiple-finger MOSFET and d) multiple-finger MOSFET
with contacts at both ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 10
Figure 2.3. Contribution mechanism of substrate noise to the drain current. . . . . . . . 11
Figure 2.4. a) Differential pair with current mirror load, b) noise model
of a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 12
Figure 2.5. Two stage operational amplifier with noise sources . . . . . . . . . . . . . . . . . . . . 14
Figure 2.6. Four basic CMOS differential pairs, a) resistive load, b)
diode-connected load, c) active current source load and d)
folded-cascode differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 16
Figure 3.1. Proposed structure of the low noise differential pair . . . . . . . . . . . . . . . . . . . 19
Figure 3.2. Noise model of differential pair in Figure 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3.3. Small-signal noise model for input stage M1,2 . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3.4. Small-signal noise model for current mirror load M7,8 . . . . . . . . . . . . . . . . 22
Figure 3.5. Small-signal noise model for the cascode stage M5,6 . . . . . . . . . . . . . . . . . . 22
Figure 3.6. Small-signal noise model for bias current source M0 . . . . . . . . . . . . . . . . . . 24
Figure 3.7. Optimum gate length of the input pair . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 27
Figure 3.8. The noise performace of the circuit in Figure 3.1 . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3.9. The noise performace of the circuit with PMOS as the input
pair . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 28
Figure 3.10. Modified structure of the operational amplifier with an aux-iliary port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30
Figure 3.11. Two stage low noise low offset operational amplifier . . . . . . . . . . . . . . . . . . 31
Figure 3.12. Small signal model of the circuit in Figure 3.11 . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3.13. AC performance with parasitic resistances and capacitances. . . . . . . . . . . 34
Figure 3.14. Noise performance with parasitic resistances and capacitances . . . . . . . . 34
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Figure 3.15. Self-biasing Vthreshold reference with start-up circuit . . . . . . . . . . . . . . . . . . . 35
Figure 3.16. Schematic of entire bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 36
Figure 3.17. Offset tuning scheme with operational amplifier in open
loop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 39
Figure 3.18. Offset tuning scheme with operational amplifier inverting-
configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 40
Figure 3.19. Setup for auxiliary input design . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 40
Figure 3.20. DC sweep of the auxiliary input . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 41
Figure 3.21. Noise level with and without auxiliary input . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3.22. Diagram of offset tuning block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 42
Figure 3.23. Connection between counter and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 43
Figure 3.24. Timing of offset tuning . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.25. Simulation of offset tuning: a) Switching point, b) DAC
output, c) Calibration output, d) Operational amplifier output . . . . . . . . . 46
Figure 4.1. Microphotograph of the op amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 48
Figure 4.2. Microphotograph of the chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 48
Figure 4.3. Diagram of the noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 49
Figure 4.4. The diagram of the PCB board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 51
Figure 4.5. Bias current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4.6. Bias voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4.7. PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 52
Figure 4.8. PCB Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 53
Figure 4.9. Common mode input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 54
Figure 4.10. Sinewave input test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 55
Figure 4.11. Measured sine wave input: a)Input=1kHZ, Gain=50, b) In-
put=1kHz, Gain=3, and c)Input=1MHz, Gain=3 . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 4.12. AC gain test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 4.13. AC gain . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 58
Figure 5.1. AC performance with 20pF load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 5.2. New structure with cascode compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 61
Figure 5.3. PSRR simulation results: a) Positive PSRR, b) Negative
PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 62
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Figure 5.4. Cascode-compensated operational amplifiers AC performance
. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 62
Figure 5.5. Noise level of the cascode-compensated operational ampli-
fier . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . 63
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CHAPTER 1
Introduction
1.1 Background
A proposed gene sequencer generates a modulated signal based on the tunneling
current through a single strand of DNA passing through a nanopore as illustrated in
Figure1.1. This signal is expected to be in the range of several pico-amps to a nano-
amp, and the bandwidth can be up to 10MHz. This corresponds to a change of 100-
1000 electrons being detected as different base pairs pass through the nanopore. To
detect such a weak signal, an ultra-low noise, low offset, high precision transimpedance
amplifier is needed [1].
There are many low noise, high precision amplifiers available. Operational am-
plifiers designed using bipolar technology have achieved a wide bandwidth and superior
voltage noise performance. For example, the AD8099 from Analog Devices[2] has
about 1nV /
Hz of input voltage noise at 10KHz, and a Gain-Bandwidth Product
(GBP) as high as 3.8GHz. There are also designs which use the lateral pnp transis-
tors provided in digital CMOS processes as the input stage of the amplifier to achieve
very-low voltage noise performance[3]. However, a bipolar operational amplifier needs
several micro amps of input current to bias the input stage. Such high bias current can in-
troduce several pA/
Hzof input-referred current noise. For example, the AD8099 has
more than 2pA/
Hznoise Power Spectral Density (PSD) at frequency up to 100MHz.
The high input-referred current noise prevents bipolar technology from being used in
the nanopore gene sequencer application.
Commercially available CMOS operational amplifiers have higher voltage noise
than bipolar amplifiers. For example, the LM6211 from National Semiconductor[4] has
5.5nV/
Hz input voltage noise at 10KHz. Another example is the opa725 from Texas
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Current
Voltage
Tunnelling CurrentSilicon Nitride
Silicon
Metal
CurrentCurrent
VoltageVoltage
Tunnelling CurrentSilicon Nitride
Silicon
Metal
Figure 1.1: Nanopore gene sequencing
Instruments[5], which has10nV /
Hz
input voltage noise at 10KHz. These CMOS
operational amplifiers have a limited bandwidth. The GBP of the op725 is only 20MHz.
This will not provide sufficient close-loop gain at megahertz frequencies need for the
nanopore application. However, CMOS transistors are voltage controlled devices and
there is almost no bias current needed for the input stage. For both the LM6211 and
opa725, the device input bias current is far less than a nano amp and the input-referred
current noise is less than 10f A/
Hz at 1KHz. Therefore, to amplify a current signal
with a magnitude of several pico amps, a CMOS device is preferred over a bipolar
device.
1.2 Purpose of this Research
There are two noise sources in MOSFET devices: flicker noise (below 1MHz)
and thermal noise. In order to distinguish the flicker noise from the thermal noise, the
PSD of both types of noise are plotted on the same axis as shown in Figure 1.2. The
corner frequency is where both PSDs are equal to each other. From Figure 1.2, it is
observed that flicker noise is inversely proportional to frequency and most significant
at low frequencies. The thermal noise is independent of frequency and dominant at
high frequencies. In the modern deep-submicron CMOS processes, the flicker noise
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source may dominate the device noise at frequencies well into megahertz range. For the
nanopore gene sequencer application, the bandwidth of interest is between 1MHz and
10MHz. In this frequency range, the thermal noise is dominant, and the flicker noise
tail will overlap the thermal noise and increase the noise floor. So for deep sub-micron
CMOS process implementation of low noise operational amplifier, both types of noise
are significant in this bandwidth and both need to be considered simultaneously.
Most of the literature addressing the design of low noise operational amplifiers
deal only in the low frequency range and therefore emphasize flicker noise reduction
techniques[3][6][7][8][9]. In [3], the BiCMOS process is used and bipolar transistors
are chosen for the input pair to address the high CMOS input-referred flicker noise prob-
lem, which is not good for amplifying low current signal. Some dynamic techniques,
like auto-zeroing and chopper stabilization [9], can achieve flicker noise levels in CMOS
comparable to bipolar devices. But those methods use switch-capacitor circuits which
introduce switching noise and alias high frequency thermal noise, and therefore achieve
low flicker noise at the cost of bandwidth and thermal noise performance. The ther-
mal noise PSD of these dynamic circuits could be far higher than 10nV/
Hz [9] at
frequencies in the MHz range.
In this research, special circuit techniques are exploited to reduce both thermal
and flicker noise in a CMOS operational amplifier designed as a current detector capable
of operating in the frequency range of 1-10MHz. The unity gain bandwidth and DC gain
are maximized. Since the untrimmed DC offset of a CMOS operational amplifier can be
up to 20mV, larger than that of bipolar counterpart, a digital trimming method has been
investigated and implemented to reduce the DC offset voltage. The amplifier design is
based on a 0.35m CMOS process operated with a 3.3V supply voltage. This amplifier
has applications to other systems requiring low levels of current detection.
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thermal Noise
corner frequency
flicker Noise
(log scale)
)log(20 2nv
cf f
thermal Noise
corner frequency
flicker Noise
(log scale)
)log(20 2nv
cf f
Figure 1.2: Typical input-referred voltage noise PSD for a MOSFET
1.3 Thesis Organization
Chapter 1 introduces the research background and problem being addressed.
Chapter 2 describes the various noise sources associated with MOSFETs. For
each noise source a small-signal model is provided. Then the noise performance is ana-
lyzed for the basic operational amplifiers with four different loads: current mirror load,
resistor load, diode-connected load and active current source load. Their limitations for
further noise reduction are analyzed.
Chapter 3 introduces a new circuit topology for minimizing noise. Its noise per-
formance is analyzed and the techniques of noise reduction are described and compared
with those basic operational amplifiers presented in Chapter 2 and the folded cascode
differential pair. Because of the relatively large offset voltage associated with CMOS
operational amplifiers, a digital offset trimming method is also described in chapter
three.
Chapter 4 describes the noise measurement technique. The test circuit is pro-
vided. Some test results are provided.
Chapter 5 presents a low noise operational amplifier with a cascode compensa-
tion scheme, which result in an improved PSRR.
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Chapter 6 summarizes the conclusions for the design and suggestions for future
work are provided.
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CHAPTER 2
Noise in MOSFETs and Basic CMOS Operational Amplifiers
This chapter provides an overview of noise sources in MOSFETs. The noise
performance of four basic CMOS operational amplifiers is analyzed. The limiations of
noise reduction techniques for these basic amplifiers are discussed.
2.1 Noise Sources in MOSFETs
The noise sources in MOSFETs include: (a) thermal noise introduced by the
channel; (b) flicker noise from the channel[10][11]; (c) thermal noise introduced by the
polysilicon gate resistance[12]; (d) thermal noise introduced by the source/drain resis-
tance and (e) thermal noise instroduced by the distributed substrate resistance[13]. In
the design of a low-noise operational amplifier, wide transistors are typically chosen for
the input pair and there are lots of contacts connected to the source and drain, therefore
the thermal noise associated with the source/drain resistances can be neglected[14].
2.1.1 Thermal noise in the channel
Thermal noise is generated by the random motion of carriers in the channel[ 10]
which introduces fluctuations, and therefore noise in the drain current. When a MOS-
FET is biased in the active region, this noise source can be represented by a current
noise generator connected from the drain to source as shown in Figure 2.1(a). The PSD
of this current noise generator is i2d,thermal, which is described by
i2d,thermal = 4kT2
3gm (2.1)
where k is Boltzmanns constant, T is the temperature in Kelvin, and gm is the small-
signal transconductance from the gate to the channel.
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2
,thermaldi2
,thermaldi
(a)
2
,thermaldv2
,thermaldv
(b)
Figure 2.1: MOSFET noise model: a) Model of thermal noise in the channel, b) Input-
referred voltage noise model
To compare the noise performance of the different circuits, the concept of input-
referred noise is introduced. Input-referred noise is a source at the circuit input which
represents the effect of all noise sources in the circuit. It is fictitious and cannot be
measured in the real circuit. For a MOSFET, the current noise source introduced by the
channel is referred back to the gate by dividing the PSD of the current noise generator
by the square of the MOSFET transconductance gm. This results in an input-referred
voltage noise source which is connected in series with the gate as shown in Figure 2.1(b).
Its approximate PSD is given by:
v
2
d,thermal = 4kT
2
3gm . (2.2)
Minimizing the channel thermal noise of a MOSFET is straightforward from the above
formula: the small-signal transconductance must be maximized. This can be achieved
by using a large DC bias current and having a large width to length (W/L) ratio for the
device.
2.1.2 Flicker noise in the channel
Flicker noise has been observed in all kinds of devices, from metal film resistors
to semiconductor devices and even chemical batteries [15]. The MOSFET has one of
the highest PSD of flicker noise among all active devices. Its precise origin has not yet
been identified unequivocally. One popular explanation is that in a MOSFET, current
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flows near the surface between SiO2 gate oxide and the crystalline silicon substrate.
The silicon crystal terminates at this Si/SiO2 interface, producing many unoccupied
dangling energy bonds [14]. As charge carriers move along this surface, they are trapped
and released by those energy bonds randomly and introduce flicker noise in the drain
current. The PSD of the noise depends inversely on the frequency and the input-referred
flicker noise model[16] is given by:
v2i,flicker(f) =KF
2C2oxW L
1
f(2.3)
where
=carrier mobility in the channel;
Cox=capacitance per unit area of the gate oxide;
W=channel width;
L=channel length;
f=frequency;
KF=flicker noise coefficient which is a process-dependant factor on the order of
1028F
A and can be different for NMOS and PMOS devices. In the 0.35m process
used in this study, KF for the NMOS device is less than that of PMOS device.
From the Equation 2.3, the PSD of the flicker noise is inversely proportional to
the active gate area. Therefore devices with large gate areas are chosen to reduce the
flicker noise of the MOSFET. Input-referred flicker noise is often modeled by connecting
a noise voltage source in series to the gate of a MOSFET like that shown in Figure 2.1(b).
2.1.3 Noise of polysilicon gate resistance
The thermal noise and flicker noise in the channel are the two main sources of
noise in MOSFETs. But for a low-noise amplifier design, other noise sources need to
be considered. One of these is the noise introduced by the resistance of the polysilicon
gate. The gate of modern CMOS device is made of polysilicon material often with a
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silicided surface layer instead of metal. However, the polysilicon gate has its drawback,
in that a polysilicon silicided gate is more resistive than metal [12], and therefore more
noisy. For example, a silicided polysilicon gate sheet resistance is about 7/2. For
a transistor with a W/L ratio of 10/1, the noise density from the gate is approximately
1.077nV/
Hz. The sheet resistance of aluminum is about 0.05/2 and the noise
density of aluminum with the same aspect ratio is about 0.0288nV/
Hz, which is
negligible when compared to that of a polysilicon gate. In low-noise amplifier design,
wide transistors are adopted for the input pair and the noise contribution from the gate
can be reduced by proper layout.
When the resistance of the gate is calculated, only effective resistance is consid-
ered. The effective resistance of polysilicon gate is actually less than the multiplication
of the technologys sheet resistance by the aspect ratio of the gate. This is because the
gate resistance of a MOSFET is a distributed resistance[12] and its effective value for
the gate when contacted at only one end as shown in Figure 2.2(a) is given by:
RG =1
3RSH,G
W
L(2.4)
where RSH,G is the gate polysilicon sheet resistance with the typical value of 7/2 for
a silicided polysilicon gate. If both ends of the gate are connected together, like that in
Figure 2.2(b), the gate resistance becomes:
RG =1
12RSH,G
W
L(2.5)
The above equation works for a single-finger device. If the device consists of
multiple fingers such as that shown in Figure 2.2(c), then the overall gate resistance is
given by
RG =1
3RSH,G
W
L
1
N(2.6)
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(a) (b)
(c) (d)
Figure 2.2: Reduction of gate noise through layout, a) single-finger MOSFET, b) single-
finger MOSFET with contact at both ends, c) multiple-finger MOSFET and d) multiple-
finger MOSFET with contacts at both ends
where N is the number of fingers. If all of the fingers are connected at both ends as
shown in Figure 2.2(d), then the factor 1/3 should be replaced by 1/12 such that:
RG =1
12RSH,G
W
L
1
N (2.7)
The noise spectral density associated with the gate resistance is then given by:
v2g,thermal = 4kT RG (2.8)
To reduce the thermal noise generated by the gate resistance, the transistor is laid-out in
a multi-finger version with both ends of the gate connected together.
2.1.4 Noise from the distributed substrate resistance
Figure 2.3 shows the noise contribution from the substrate to the drain current
[13]. The substrate has a distributed resistance and therefore generates thermal noise
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2
,thermalsubv
subR
2
,thermalsubv
subR
Figure 2.3: Contribution mechanism of substrate noise to the drain current
v2sub,thermal that can be approximated by:
v2sub,thermal = 4kT Rsub (2.9)
where Rsub is substrate distributed resistance. This noise is amplified by the substrate
transconductance gmb and coupled to the drain current through a depletion capacitance,
such that the current noise can be represented by:
i2sub,thermal = 4kT Rsubg2mb (2.10)
The direct way to reduce the noise from substrate is to decrease gmb by increasing
the source bulk bias voltage or using a process with heavily doped substrate.
2.2 Noise Performance of the CMOS Differential Pair
To understand the main noise sources involved in an operational amplifier, lets
consider the noise performance of a differential pair with a current mirror load shown in
Figure 2.4. The voltage gain of the amplifier, A, measured from the gate of M1,2 to the
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1M
2M
3M
4M
DDV
SSI
outV
1M
2M
3M
4M
DDV
SSI
outV
(a)
1M
2M
3M
4M
SSI
2
1nv
2
2nv
2
3nv
2
4nv
DDV
outV
1M
2M
3M
4M
SSI
2
1nv
2
2nv
2
3nv
2
4nv
DDV
1M
2M
3M
4M
SSI
2
1nv
2
2nv
2
3nv
2
4nv
DDV
outV
(b)
Figure 2.4: a) Differential pair with current mirror load, b) noise model of a)
output Vout is described by the following equitation:
A = gm2ro =2
(nCOX(W/L)2)
(2 + 4)
ID2(2.11)
where is is channel length modulation, is carrier mobility in the channel, Cox is the
capacitance per unit are of the gate oxide, W and L are MOSFETs width and length
respectively, ID2 is the bias current of the input pair M1 and M2.
The gain from the gate ofM3,4 to the output Vout is gm4ro, where gm2 and gm4 are
transconductance of M2 and M4, respectively, and ro is small-signal output resistance.
The output noise is given by:
v2
no(f) = 2(gm2ro)2
v2
n2(f) + 2(gm4ro)2
v2
n4(f) (2.12)
where vn2 and vn4 represent the noise from M2 and M4 respectively, which include all
those noise sources discussed above and are referred back to the gate ofM2 and M4.
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This noise v2no can be referred back to the amplifiers input by dividing the
squared gain from the amplifiers input to its output which results in
v2
ni(f) = 2v2
n2(f) + 2v2
n4(f)gm4
gm22
= 2v2
n2(f) + 2v2
n4(f) (W/L)4p
(W/L)2n
(2.13)
Assuming COX,n = COX,p = COX, the flicker noise and thermal noise of this structure
are given by the following two equations:
v2flicker(f) =KFn
nC2OXW2L2f
1 +
KFpKFn
L2L4
2(2.14)
v2thermal =16kT
3
2nCOX(W/L)2ID2
1 + p(W/L)4n(W/L)2
(2.15)where KFn is the flicker noise coefficient of NMOS, KFp is the flicker noise coefficient
of PMOS, n and p are carrier mobilities for both NMOS and PMOS respectively.
From the above equations, we find that each MOSFET introduces both flicker noise and
thermal noise. All CMOS voltage operational amplifiers have at least two MOSFETs
as the input pair. The more MOSFETs in the circuit, the more noise is introduced.
From Equation 2.15, it is observed that large bias currents can be used to minimize
thermal noise at the cost of power dissipation and voltage gain A. The large bias current
also results in a large overdrive voltage for transistors M3 and M4. The drain to source
voltage VDS ofM3 and M4 has to be large enough to keep the transistors in the saturation
region. Hence
VDS > Vthreshold + Voverdrive (2.16)
Therefore increasing the bias current reduces the voltage headroom at the output. For
the differential pair with current mirror load, it is clear from this analysis that optimizing
the noise performance involves a trade off with other parameters, including the DC gain
and power.
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A1 A2
2
1v
2
2v
A1 A2A1 A2
2
1v
2
2v
Figure 2.5: Two stage operational amplifier with noise sources
Figure 2.5 shows a two stage operational amplifier. The first stage has a gain of
A1 and an output noise v21; the second stage has a gain of A2 and an output noise v22 .
The total gain of the amplifier is A = A1 A2. The total output noise of the amplifier is
v2
total = v2
2 + A2
2 v2
1 (2.17)
When this noise is referred back to the input port, the input-referred noise is
v2i =v22
A22A21
+1
A21v21 (2.18)
Since the noise from the first stage is amplified by the second stage, the noise of first
stage is more important than that of the second stage. The larger the gain of first stage
A1, the less important the noise contribution of second stage. However, the differential
pair with current mirror load has a disadvantage in that the DC gain is inversely propor-
tional to the bias current. The higher the bias current, the lower the DC gain of the first
stage, which will make the noise from later stage more pronounced.
In this research, the differential pair with more than 4 cascode stages is not pre-
ferred because we used a 0.35m CMOS process with a working voltage of 3.3V. A
differential pair with more than 4 cascode stages will have a headroom problem. So, the
first effort is to analyze some other basic differential pairs to see whether any of them
can provide a superior noise performance.
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Differential pair with a resistive load:
The differential pair with resistive load is shown in Figure 2.6(a). Its input-
referred noise is given by:
v2ni = 8kT
2
3gm+
1
g2mRD
+
KFnnC
2OXW2L2f
(2.19)
For low-noise design, a large bias current (even to the order of a few milliamps) is
needed and the resistor value has to be chosen to minimize thermal noise. The opera-
tional amplifier with a large resistive load can reduce the voltage headroom at the output.
Moreover, the gain of this structure is relatively low, which make the noise of the later
stages a larger issue.
Differential pair with a Diode-connected load:
An Differential pair with a diode-connected load is shown in Figure 2.6(b), and
the noise performance is given by Equation 2.14 and 2.15. This structure has the same
problems as the operational amplifier with a resistive load. For low noise operational
amplifier design, the bias current should be large and the drain-source voltage also needs
to meet Equation 2.16, which results in a small output voltage swing range. Also such a
structure has a small gain.
Differential pair with an active current source load:
The fully differential pair with active current source load is shown in Figure
2.6(c). The structure has a higher output common mode range than those amplifiers dis-
cussed above since its load drain-source voltage only need to meet the requirement of
VDS > Voverdrive, a threshold voltage less than that of the differential pair with a current
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1M
2M
1R
2R
DDV
SSI
1M
2M
1R
2R
DDV
SSI
(a)
1M
2M
3M
4M
DDV
SSI
1M
2M
3M
4M
DDV
SSI
(b)
CMFB
1M
2M
3M
4M
DDV
SSI
CMFB
1M
2M
3M
4M
DDV
SSI
(c)
1M 2M
3M
4M
SSI
5M 6M
7M
8M
AB
In +In
ddV
2bV
4bV
Out
1M 2M
3M
4M
SSI
5M 6M
7M
8M
AB
In +In
ddV
2bV
4bV
Out
(d) Folded-cascode differential pair
Figure 2.6: Four basic CMOS differential pairs, a) resistive load, b) diode-connected
load, c) active current source load and d) folded-cascode differential pair
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mirror load and diode-connected structure. The larger headroom provided by this struc-
ture allows the input pair to sink more DC bias current than the other structures. The
input-referred noise density is also given by Equations 2.14 and 2.15. Therefore it has
the potential of the best noise performance among those introduced before. But such
a structure requires a Common Mode Feedback (CMFB) network to define the output
common-mode level. Any mismatch in the CMFB circuit can introduce extra noise that
could outbalance the advantage of the fully differential structure.
Folded-cascode differential pair:
Figure 2.6(d) gives the structure of a folded cascode differential pair. This struc-
ture has the limitation of maximizing the input pairs bias current for a low noise design.
M3 and M4 source bias current for the input pair M1 and M2, and the current mirror
load M7 and M8. When the bias current ofM1 and M2 is maximized, the bias current
ofM3 and M4 is maximized as well. This will reduce the DC voltage level at the drain
of M3 and M4. This reduced DC voltage level will reduce the voltage headroom at the
drain of M6, which is especially true when the length of M3 and M4 is chosen larger
than normal in a low noise operational amplifier design.
From the above discussion, we can appreciate the trade-offs between noise,
power dissipation, voltage headroom when designing a low noise operational ampli-
fier. Chapter three describes a new amplifier structure which combines the features of
the fully differential pair with active current source load with an amplifier with a current
mirror load. That structure has the potentiality of improved noise performance.
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CHAPTER 3
Novel Structure for a Low Noise Operational Amplifier using
MOSFETs
This chapter proposes a new operationality amplifier structure offering the po-
tential of better noise performance. The techniques used to reduce noise are described.
In Chapter 2, the noise limitations of the basic CMOS differential pair structure
were discussed. In this chapter a new structure shown in Figure 3.1 is proposed and
analyzed. This structure combines the merits of a fully differential pair with an active
current source load and an differential pair with a current mirror load. The active current
source M3 and M4 can source the maximum current for the input pair to reduce thermal
noise. The current mirror M7 and M8 combine with the transconductance of the input
pair to define the DC gain. A cascode stage, M5 and M6, is introduced for the following
three reason:
1. This cascode stage can reduce the Miller effect, thereby increasing the bandwidth
of the amplifier. The input pair (M1, M2) has a gate-drain parasitic capacitance
Cgd. If there is no cascode stage, the gain Amiller from input (M1, M2) to the drain
of M7 and M8 will be larger than 1, that is, Amiller > 1. The Miller effect will
magnify the parasitic capacitance as AmillerCgd, which will limit the amplifiersbandwidth. With the introduction of cascode stage M5 and M6, the voltage at the
drains ofM1 and M2 is fixed, and the gain from the input to the source of M5,6 is
reduced and therefore the parasitic capacitance at the gate ofM1,2 is minimized.
2. This cascode stage increase the output resistance looking into the drain ofM6 and
therefore increase the gain of this differential pair.
3. The cascode structure reduces the short channel variation of the input stage. In
describing the channel length modulation using the channel length modulation
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DDV
1M
2M
3M
4M
5M 6M
7M
8M
SSI
2bV
4bV
+In
In
Out
DDV
1M
2M
3M
4M
5M 6M
7M
8M
SSI
1M
2M
3M
4M
5M 6M
7M
8M
SSI
2bV
4bV
+In
In
Out
Figure 3.1: Proposed structure of the low noise differential pair
parameter , we assume that the small-signal output impedance ro is constant.
This is not really true. This output impedance varies with the drain-source voltage.
When the drain-source voltage increases, the pinch-off point will move towards
source region resulting in a wider depletion region around the drain and a higher
ro. When the drain-source voltage decreases, a lower value ofro results. With thecascode stage M5,6, the drain-source voltage of M1,2 doesnt experience a large
variation and the small-signal resistance ofM1,2 remains almost constant.
Lets examine how the disadvantages of achieving low noise performance for
those differential pairs discussed in Chapter 2 are avoided in this new structure. In this
new structure, the bias current of the amplifiers input pair is rationed between M3,4
and M7,8. M3,4 is sized to source most of the bias current. For example, if the bias
current ofM1,2 is chosen to be 3mA, I3,4 ofM3,4 can be 2.85mA and I7,8 can be set as
0.15mA. The common-mode level at the drain of M3,4 is defined by the cascode stage
M5,6, instead of common mode feedback circuit used in the differential pair with active
current source load. To reduce the thermal noise, the large bias current of 3mA is chosen
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1M
2M
3M
4M
5M
6M
7M
8M
DDV
0M
2
1nv
2
2nv
2
3nv
2
4nv
2
5nv
2
6nv
2
7nv
2
8nv
2
0nv
1M
2M
3M
4M
5M
6M
7M
8M
DDV
0M
2
1nv
2
2nv
2
3nv
2
4nv
2
5nv
2
6nv
2
7nv
2
8nv
2
0nv
Figure 3.2: Noise model of differential pair in Figure 3.1
for the input pair M1,2. This current is mainly provided by the active load M3,4. The
output of the common-mode level is defined by M7,8, which takes a very small current
and provides a wider output swing than that provided by a differential pair with a current
mirror load. In the analysis that follows, we show that this structure has the advantage
of increasing the small-signal gain without deteriorating the noise performance. The
large 3mA bias current results in the input pair M1,2 with a high aspect ratio and a large
transconductance gm, these improves the bandwidth and other performances, like low
flicker noise and high DC gain.
3.1 Noise Analysis of New Structure
Figure 3.2 shows the noise model for the structure in Figure 3.1. The noise con-
tribution of each gate is referred back to their own gate input, like the noise contribution
ofM3, which is represented by v2n3 connected in series to its gate. In the following noise
calculation, symmetry is assumed, such that the noise contributions ofM1, M3, M5 and
M7 are the same as those ofM2, M4, M6 and M8.
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42|| rr
16vg
m
22 nmvg
8r
1v
2nov
2nv
42|| rr
16vg
m
22 nmvg
8r
1v
2nov
2nv
Figure 3.3: Small-signal noise model for input stage M1,2
3.1.1 The noise contribution of the input stage M1,2
The small-signal model shown in Figure 3.3 is for the calculation ofM2s noise
contribution, where the parasitic capacitances are omitted for simplicity. From this
model, we find the output noise from M2 is:
vno2 = gm2r8vn2 gm2rovn2 (3.1)
where ro is the small-signal output resistance of the circuit in Figure 3.1.
3.1.2 The noise contribution of the active current source load M3,4
The small-signal model to calculate the noise contribution of the active current
source load stage is the same as that in Figure 3.3 withvn
2 andgm
2 replaced withvn
4
and gm4. So the output noise from the active current load M4 is:
vno4 = gm4r8vn4 gm4rovn4 (3.2)
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8r
16vg
m
88 nmvg 42 || rr
1v
8nov
8nv
8r
16vg
m
88 nmvg 42 || rr
1v
8nov
8nv
Figure 3.4: Small-signal noise model for current mirror load M7,8
3.1.3 The noise contribution of current mirror load M7,8
The small signal model for noise contribution of the current mirror load is shown
in Figure 3.4. The noise contribution from M8 is approximately:
vno8 = gm8r8vn8 gm8rovn8 (3.3)
3.1.4 The noise contribution of cascode stage M5,6
The cascode stages small-signal noise model is shown in Figure 3.5. Here
vgs6 = vn6 v1. The output noise from this stage is given by:
42|| rr
1v
6r
66 gsmvg
8r
6nov
6nv
42|| rr
1v
6r
66 gsmvg
8r
6nov
6nv
Figure 3.5: Small-signal noise model for the cascode stage M5,6
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vno6 =gm6r6r8
r6 + r8 + gm6r6r2vn6 r8
r2vn6 (3.4)
where vn6 is noise contribution of M6 referred back to its gate. The effective transcon-
ductance of M6 according to Equation 3.4 is approximately 1/r2 and is much smaller
than transconductance gm6 of M6 and gm2 of M2. The operational amplifiers small-
signal output resistance ro is close to r8. The noise generated by the cascade current
buffers and referred back to the amplifiers input is vni5,6 =1
gm2ro
r8r2
vn6 1gm2r2 vn6, andis much smaller than those generated by input stage, active current and current mirror
loads, therefore it is omitted in the later noise analysis.
3.1.5 The noise contribution of current bias MOSFET M0
M0 provides the bias current for the input pair, and noise associated with this
transistor will modulate the bias current. Ideally, the active current source load M3,4
will not see noise from M0 since their gate voltage experience no change. So this noisewill run through the input pair M1,2 and the cascade stage M5,6 to the current mirror
load M7,8. The other observation is that the drains voltage of M8 will track that ofM7.
So, the noise from M0 at the output (drain of M8) is equal to the noise at the drain of
M7. As a result, the small-signal model shown in Figure 3.6 can be used to analysis the
noise contribution ofM0. The noise from M0 is approximately vno0 = gm0gm7vn0, and theamount of noise referred back to the operational amplifiers input is vni0 =
1
gm2ro
gm0gm7
vn6.
This is a very small value when compared with other stages input referred noise due to
the large gain gm2ro from the input pair to the output.
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1v
00nm
vg0r
11vg
m
1r
3r
2v
7
1
mg
0nov
5r
25vg
m
1v
00nm
vg0r
11vg
m
1r
3r
2v
7
1
mg
0nov
5r
25vg
m
Figure 3.6: Small-signal noise model for bias current source M0
3.1.6 Total output noise
Combining all those noise models discussed above, the total output noise is given
by
v2no(f) = v2
no0(f) + 2v2
no2(f) + 2v2
no4(f) + 2v2
no6(f) + 2v2
no8(f)
2(gm2ro)2v2n2(f) + 2(gm4ro)2v2n4(f) + 2(gm8ro)2v2n8(f) (3.5)
The input referred noise is
v2ni(f) = 2v2
n2(f) + 2v2
n4(f)
gm4gm2
2
+ 2v2n8
gm8gm2
2
= 2v2n2(f) + 2v2
n4(f)
(W/L)4pID4(W/L)2nID2
+ 2v2n8(f)
(W/L)8pID8(W/L)2nID2
(3.6)
The following two equations show the input referred flicker noise and thermal noise for
this design respectively:
v2flicker(f) =KFn
nC2OXW2L2f
1 + KF
p
KFn
L2L4
2ID4ID2
+ KFp
KFn
L2L8
2ID8ID2
(3.7)
v2thermal =16kT
3
2nCOX(W/L)2ID2
1 +
p(W/L)4ID4n(W/L)2ID2
+
p(W/L)8ID8n(W/L)2ID2
(3.8)
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3.2 Noise Reduction Techniques for this New Structure
From the above two equations, we find there are three techniques that can be
used to reduce the noise:
1. Determination of the input pair type for M1,2
2. Optimization of the bias current ID2 of the input pair
3. Optimization of the sizes and aspect ratios of the MOSFETs
3.2.1 Determination of the input pair type for M1,2
In this structure, NMOS should be chosen for the input pair M1,2 for the follow-
ing three reasons:
1. The bandwidth we are dealing with is between 1MHz to 10MHz. Over this band-
width range, thermal noise is often dominant. Selecting a NMOS transistor for
the input pair reduces thermal noise according to Equation 3.8, since NMOS tran-
sistors have a lager mobility n(often 2 to 3 times) than PMOS transistors.
2. Flicker noise is still important in this design. In a submicron process, the corner
frequency could be greater than 1MHz. In Figure 1.2 we can see that as the
thermal noise floor is reduced, the corner frequency is increased. The flicker
noise tail will overlap with the thermal noise floor. In the 0.35m CMOS process
used, the NMOS flicker noise coefficient KFn is smaller than that of PMOS flicker
noise coefficient KFp, which is helpful for achieving lower flicker noise according
to Equation 3.7.
3. NMOS transistors have a higher transition frequency fT than PMOS transistors,
which help achieve a higher bandwidth.
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3.2.2 Optimization of the bias current ID2 of the input pair
To further reduce the thermal noise, the bias current ID2 of the input pair can be
increased up to several milliamps in this new structure. With such large bias current,
the basic CMOS differential pair like the one with current mirror load can have good
noise performance but at the cost of gain and voltage headroom at the output. However,
for this new structure, the increased bias current does not deteriorate either the gain or
voltage headroom . This is one of the highlights of this new structure which is explained
in the DC gain section 3.3 below.
3.2.3 Optimization of the sizes and aspect ratios of MOSFETs
According to Equation 3.7, choosing a large size (W L)2 for the input pair, and
making the channel length L of the active load M3,4 and current mirror M7,8 larger than
that of input pair M1,2 can help to reduce the flicker noise. The aspect ratio (W/L)2
is chosen to be larger than (W/L)4 and (W/L)8, so the second and third terms in the
bracket of Equation 3.8 is less than 1. This helps to reduce the thermal noise. After
those choices, we can find that the input pair contributes most of the noise of both types.
The gate length L1,2 of the input pair could increase or decrease flicker noise
according to Equation 3.7. The optimum value is determined by:
v2flickerL2
= 0 L2 =
KFnKFp
1
L24
ID4ID2
+
1
L28
ID8ID2
(3.9)
When the gate lengths of M3,4 and M7,8 are first chosen to be 2.1m to avoid a large
overdrive voltage, ID2 and ID4 chosen to be 3mA and 2.85mA respectively, the optimum
gate length ofM1,2 is found to be 0.7m as shown in Figure 3.7.
The simulated input-referred voltage noise performance of the circuit of Figure
3.1 using a 0.35m CMOS process is shown in Figure 3.8. The total noise level is
simulated to be 1.796nV /
Hzat 1MHz and 1.184nV/
Hzat 10MHz.
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0 0.5 1 1.5 2 2.5 3
x 10-6
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7x 10
-19
Input Gate Length (m)
Noise
Level(v
2)
X: 7e-007
Y: 2.873e-019
Figure 3.7: Optimum gate length of the input pair
100
101
102
103
104
105
106
107
0
1
2
3
4
5
6
7
8
9x 10
-7
X: 1e+006
Y: 1.796e-009
Frequency(Hz)
noise
level(v/(Hz))
X: 1e+007
Y: 1.184e-009
Figure 3.8: The noise performace of the circuit in Figure 3.1
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100
101
102
103
104
105
106
107
0
0.5
1
1.5
2
2.5
3x 10
-6
X: 1e+007
Y: 2.427e-009
Frequency(Hz)
noise
level(v/(Hz))
X: 1e+006
Y: 2.306e-009
Figure 3.9: The noise performace of the circuit with PMOS as the input pair
Figure 3.9 shows the simulated noise level of the same structure when using
PMOS transistors as the input pair. The size, aspect ratio and bias current are all
the same as those in Figure 3.8. From this figure we conclude that the PMOS input
pair shows poorer noise performance: the noise level is 2.306nV /
Hz at 1MHz and
2.427nV/
Hzat 10MHz.
From the previous analysis, we find that the current mirror load M7,8 sources
a very small amount of bias current compared with the input pair. Thus, ID8ID2
120
,
ID4 ID2 and Equation 3.7 and 3.8 are reduced to:
v2flicker(f) KFn
nC2OXW2L2f
1 +
KFpKFn
L2L4
2(3.10)
v2thermal 16kT
22nCOX(W/L)2ID2
1 +
p(W/L)4n(W/L)2
(3.11)
From these two equations, we can find that the four MOSFETs ( M1,2,3,4) contribute most
of the noise in this new structure. Also from these two equations, we can find that the
noise performance of this new structure is comparable with the differential pair with
active load, but it doesnt need CMFB circuit.
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3.2.4 Noise performance of the folded-cascode differential pair
Figure 2.6(d) shows a folded-cascode differential pair. It has the same small-
signal model as that of Figure 3.1. And its flicker and thermal noise are also represented
by Equation 3.7 and 3.8 respectively. But the new structure has better noise performance
than this folded-cascode differential pair. Assuming ID2, ID4 and ID8 are the bias cur-
rents of M2, M4 and M8 in Figure 3.1 respectively, and IfD2, I
fD4 and I
fD8 are the bias
currents ofM2, M4 and M8 in Figure 2.6(d) respectively, we find ID2 = ID4 + ID8 and
IfD2 = IfD4 IfD8. If we choose ID2 = IfD2, then ID4 < IfD4 and the drain of M4 in
Figure 2.6(d) will have smaller DC level than that of the drain of M4 in Figure 3.1. This
smaller DC level in folded-cascode differential pair results in smaller voltage headroom
at the drain ofM6. This is especially true when a long gate length is chosen for M3 and
M4 and a large bias current is chosen for the input pair in a low noise design. Therefore,
this folded-cascode structure has smaller output swing. Lets think about it in another
way, if we apply the same power to both the circuits in Figure 3.1 and Figure 2.6(d),
which means ID2 = IfD4 > I
fD2, then new structure has better noise performance since
its input pair has larger bias current which results in lower thermal noise. Hence, the
new structure offers an improvement over the standard folded cascode structure.
3.3 DC Gain
The small-signal DC gain of the differential pair of Figure 3.1 is given by:
A1 = gm2((gm6ro6(ro2 ro4 r1a)) ro8) (3.12)
where roa is the small signal resistance of the auxiliary port consisting ofM1a and M2a
as shown in Figure 3.10. This auxiliary port is used to reduce offset and its detailed
analysis is given in the offset reduction section 3.6 below. Even though the large bias
current reduces ro2 and ro4, the introduction of the cascode stage increases the output
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1M
2M
3M
4M
5M
6M
7M 8M
DDV
1SSI
2SSI
aM
1a
M2
2bV
4bV
+InIn +Ina
Ina
Out
1M
2M
3M
4M
5M
6M
7M 8M
DDV
1SSI
2SSI
aM
1a
M2
2bV
4bV
+InIn +Ina
Ina
Out
Figure 3.10: Modified structure of the operational amplifier with an auxiliary port
resistance looking into the drain of M6 and makes the ro8 the dominant parameter in
determining the DC gain in Equation 3.12. ro8 can be approximated by ro8 1ID8 andcan be increased in two ways. First the channel length of the transistors M7,8 can be
increased to reduce the length modulation parameter which is inversely proportional
to the MOSFET channel length for the first order approximation [14]. In this design, the
current is radioed between the active load M3,4 and current mirror M7,8. So the second
way to increase ro8 is to minimize the current ID8 in M7,8. Increasing the bias current ID2
increases the transconductance gm2 and therefore DC gain. The active load M3,4 sources
this extra bias current through the input pair M1,2, and therefore the thermal noise is
reduced as described by Equation 3.8. By now it can be observed from the previous
discussion that M1, M2, M3 and M4 are primarily responsible for noise reduction, while
M1, M2, M5, M6, M7 and M8 are responsible for the DC gain. The DC gain and noise,
which is often a trade-off between noise level and gain in differential pair with current
mirror load, can be optimized independently for this proposed structure .
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1M
2M
3M
4M
5M
6M
7M
8M
DDV
aM
1 aM
2
0M
aM
0
9M
10M11M
12M
13M
14M
Rc
C
Out
1bI
2bI
3bI
4b
V
5bI
+In In
+a
In aIn1M
2M
3M
4M
5M
6M
7M
8M
DDV
aM
1 aM
2
0M
aM
0
9M
10M11M
12M
13M
14M
Rc
C
Out
1bI
2bI
3bI
4b
V
5bI
+In In
+a
In aIn
Figure 3.11: Two stage low noise low offset operational amplifier
3.4 AC Performance
The common source configuration is chosen for the output stage of the opera-
tional amplifier. Such a stage can achieve about 20-30 dB of gain. A Miller compen-
sation scheme is chosen to achieve reasonable phase margin. A two stage low noise
operational amplifier incorporating the new structure for the differential pair is shown in
Figure 3.11. Sizes of the transistors, and the Miller compensation resistor and capacitor
are provided in Table 3.1.
M1 816/0.7 M6 66/0.7 M0a 66/0.7 M13 220/0.35M2 816/0.7 M7 132/2.1 M9 385/0.7 M14 198/2.1
M3 198/2.1 M8 132/2.1 M10 220/0.35 R 940M4 198/2.1 M1a 105/0.7 M11 408/0.7 Cc 5pFM5 66/0.7 M1b 105/0.7 M12 66/0.7
Table 3.1: Optimized devices size of the two-stage operational amplifier
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1R
1C
cC6r
16vgm
29vg
m 3R 3C
R
2
2 im vg2
R2
C
2
1 im vg
1v
2v outv
1R
1C
cC6r
16vgm
6r
16vgm
29vg
m 3R 3C
R
2
2 im vg2
R2
C
2
1 im vg
1v
2v outv
Figure 3.12: Small signal model of the circuit in Figure 3.11
The small-signal model for the circuit in Figure 3.11 is given in Figure 3.12:
Here R1 = r2a r2 r4C1 = Cgd2 + Cgd4 + Cgd2a + Cgs6
R2 = r8
C2 = Cgd6 + Cgd8 + Cgs9
R3 = r9 r10C3 = Cgd9 + Cgd10
Analysis of ac small-signal model, after considerable algebra work and discard-
ing some minor parameters such as C1 and C2, results in the following equation:
voutvi
=gm2gm9R2R3 sgm2R2R3Cc(1 gm9R)
1 + s(RCc + R3C3 + gm9R2R3Cc) + s2RR3CcC3(3.13)
With the assumption that the second pole is far larger than the dominant pole, the dom-
inant pole of above equation can be approximated by:
p1 = 1gm9R2R3Cc
. (3.14)
Since the DC gain of this amplifier is:
A(0) = A1A2 = (gm2((gm6ro6(ro2 ro4 r2a)) ro8)) gm9R3= gm2R2 gm9R3 (3.15)
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and the unity gain bandwidth is still given by GBP = A(0)|p1| = gm2CcThe second dominant pole is:
p2 gm9R2RC3
. (3.16)
and the zero is:
z =gm9
Cc(1 gm9R) . (3.17)
For unity-gain stability, the magnitude of the second dominant pole should be greater
than the GBP such that:
|p2| gm9R2RC3
> GBP =gm2Cc
. (3.18)
Therefore
Cc >gm2RC3gm9R2
. (3.19)
From Equations 3.16 and 3.17, we can find that the zero-nulling resistor R can control
the zero and second dominant pole positions and therefore change the phase margin.
One observation from Equation 3.19 is that in this low noise operational amplifier de-
sign, the input transconductance can be larger than the transconductance of the output
driver. If R is chosen close to 1/gm9, thenp2 is maximized and stability is achieved with
a minimum Cc.
For the values given in Table 3.1, the circuit of Figure 3.11 was simulated. The
simulated AC results and noise performance including parasitic resistances and capaci-
tances introduced by the layout are shown in Figure 3.13 and Figure 3.14 respectively.
Simulation results in Figure 3.13 show the DC gain of the design is around 120dB with
unity-gain bandwidth up to 380MHz. The phase margin is around 11o. The simulated
total input-referred noise level is lower than 2nV /
Hzfrom 1MHz to 10MHz.
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100
101
102
103
104
105
106
107
108
109
1010
-100
-50
0
50
100
Frequency(Hz)
Gain(dB) X: 3.802e+008
Y: -0.1363
100
101
102
103
104
105
106
107
108
109
1010-400
-300
-200
-100
0
Frequency(Hz)
Phase
X: 3.802e+008
Y: -169.4
Figure 3.13: AC performance with parasitic resistances and capacitances
100
101
102
103
104
105
106
107
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1x 10
-6
X: 1e+006
Y: 1.939e-009
Frequency(Hz)
noise
level(v/(Hz))
X: 1e+007
Y: 1.297e-009
Figure 3.14: Noise performance with parasitic resistances and capacitances
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6bM
5bM
7bM
1bM
2bM
3bM 4bM
R
6bM
5bM
7bM
1bM
2bM
3bM 4bM
R
Figure 3.15: Self-biasing Vthreshold reference with start-up circuit
3.5 Bias Circuit
The bias network is an important component in the low noise amplifier design.
The bias core is shown in Figure 3.15. The advantage of this bias circuit is that the
currents through Mb3,b4 are insensitive to the supply voltage to the first order, which
means such circuit has superior PSRR performance. A combination of current- and
voltage-routing techniques [10] is used to reduce the mismatch and supply resistance.
The MOSFETs Mb5,b6,b7 consist of a start-up circuit with Mb5 being a long channel
device.
The entire bias network is shown in Figure 3.16. Cascode stages are imple-
mented to increase the output resistance and the values of the transistors are given in
Table 3.2.
3.6 Offset Reduction and Auxiliary Port
In general CMOS operational amplifiers exhibit higher input offset voltage than
their BJT counterparts. The photolithography, ion implantation, etching and other process-
related factors can cause a mismatch in the threshold voltage Vt and gain factor between
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7bM
5bM
6bM
1bM
2bM
3bM
4bM
8bM
9bM
10bM
11bM
12bM
13bM
14bM
15bM
16bM
17bM
18bM
19bM
20bM
21bM
22bM
23bM
1bV
2bV
3bV
5bV
R
DDV
7bM
5bM
6bM
1bM
2bM
3bM
4bM
8bM
9bM
10bM
11bM
12bM
13bM
14bM
15bM
16bM
17bM
18bM
19bM
20bM
21bM
22bM
23bM
1bV
2bV
3bV
5bV
R
DDV
Figure 3.16: Schematic of entire bias circuit
Mb1 220/0.7 Mb7 2.2/2.1 Mb13 220/0.7 Mb19 72/0.7Mb2 220/0.7 Mb8 220/0.7 Mb14 660/0.7 Mb20 22/2.1Mb3 220/0.7 Mb9 55/2.1 Mb15 660/0.7 Mb21 110/0.7Mb4 220/0.7 Mb10 690/0.7 Mb16 22/2.1 Mb22 310/0.7Mb5 22/0.7 Mb11 690/0.7 Mb17 110/0.7 Mb23 310/0.7
Mb6 2.2/14 Mb12 44/2.1 Mb18 72/0.7 R 940
Table 3.2: MOSFETsaspect ratio in the bias circuit
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the input pairs and generate a random voltage. Typically, a CMOS operational ampli-
fiers offset can be up to 20mV. In this design, there have been many efforts made to
reduce the amplifiers noise level. These efforts are inherently helpful in minimizing the
operational amplifiers random offset.
Because of the high gain of the first stage, the offset introduced by the second
stage is negligible. So, the input-referred random offset for the operational amplifier
shown in Figure 3.11 is approximated by [10]:
VOS Vt1,2 +Vt3,4 gm4gm2
+Vt7,8 gm8gm2
+Vov1,2
2
(WL
)1,2
(WL
)1,2+(W
L)3,4
(WL
)3,4+(W
L)7,8
(WL
)7,8
(3.20)
The first term in Equation 3.20 is due to the input pairs threshold mismatch. The second
term is due to the active current source load threshold mismatch referred back to the in-
put of amplifier. Having gm4 smaller than gm2 to reduce noise is also helpful in reducing
this second term. The third term is negligible because ofgm8 is designed far less than
gm2 fr noise performance. In this design, the large aspect ratio of the input pair achieves
a small overdrive voltage Vov1,2 and therefore helps to reduce the last term. The standard
deviation of the difference between the input pairs threshold is used as a measure of the
mismatch. This is defined as [17]
Vt =AVtW L
(3.21)
and the mismatch in the current gain factor is given by [17]:
= ATW L
(3.22)
where AVt , AT are process-dependent constants and AVt decreases with gate oxide
thickness. From the above equations, it is observed that the large gate area used to reduce
the flicker noise can also reduce the threshold and gain factor mismatches, and therefore
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the offset between the input pair. This can be intuitively understood if we consider the
flicker noise as a low frequency signal and the offset also as a low frequency signal.
The efforts to reduce flicker noise will also reduce offset. So, the mechanisms to reduce
noise are consistent with reduction of the input-referred offset.
Even though the input-referred random offset of this design is theoretically low,
it still deserves further reduction because of the systematic offset and the remaining ran-
dom offset. Conventional offset reduction techniques such as on-wafer trimming used
in bipolar technology is very expensive and prevents real-time trimming. Some state-of-
art dynamic offset reduction schemes such as auto-zeroing [9] and chopper stabilization
[18] methods can reduce the offset down to several microvolts, but they often alias high-
frequency noise down to the base band. Moreover, there is unavoidable charge injection
and clock feed through. These issues limit dynamic offset reduction schemes to low
frequency applications. Some other methods, such as the ping-pong amplifier [19], use
cascode transistors as a load, and adjust the current running through those cascode tran-
sistors. This method will reduce the voltage headroom at the output of the first stage and
is problematic in low voltage designs.
In this design, a digital trimming method for offset reduction is introduced and
analyzed. Such a method can provide offset trimming at power-up or upon request. A
schematic representation [19] of this method is shown in Figure 3.17. During the offset
calibration phase, the operational amplifiers inputs are connected to a common voltage
source. The counter keeps counting and a new controlling voltage is applied to the
auxiliary port of the operational amplifier. Then, the operational amplifier generates a
new output which is compared with a reference voltage. The counter will stop counting
when comparator experiences a zero crossing. When the output of comparator changes
its state, the calibration phase is concluded and the output of the DAC is set to the
desired controll voltage. In Figure 3.17, the operational amplifier is in the open loop
mode. When the open loop DC gain of the amplifier is very large, such a configuration
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Comparator
DAC
CO=1?
Vc
Cross Zero?
Counter
12-bit
Vref
CO yes
Stop
Op AmpVOS
ComparatorComparator
DAC
CO=1?
Vc
Cross Zero?
Counter
12-bit
Vref
CO yes
Stop
Op AmpVOSOp AmpVOS
Figure 3.17: Offset tuning scheme with operational amplifier in open loop mode
is not very efficient to reduce the offset to make the output fixed within the supply rail
unless using the big size auxiliary input pair at the cost of more noise. But in practical
application, the operational amplifiers are seldom used in an open-loop configuration.
They are often used in an inverting, non-inverting or transimpedance configuration with
a gain much less than open-loop DC gain. An example of inverting configuration is
shown in Figure 3.18. The amplifier can keep inverting, non-inverting or transimpedance
configuration when offset trimming is taking place.
For this offset calibration, an auxiliary port in introduced to this operational
amplifier [20] like that shown in Figure 3.10. The size and bias current of the auxiliary
port are chosen to cover a 10mV input referred offset without adding too much extra
noise. The auxiliary input size and offset adjustable range are determined by the setup
shown in Figure 3.19. The operational amplifiers primary port is in the unity-gain
configuration. A 10mV offset is applied to the operational amplifiers positive input of
the primary port. The desired DC output level is 0V. The voltage at the positive input of
auxiliary port is biased at a DC level and the negative input is DC swept from 0V to 3.3V.
The simulation result in Figure 3.20 shows that the output experiences a change from
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12-bitOp Amp
Comparator
DAC
CO=1?
Vc
Cross Zero?
Counter
VOS
Vref
CO yes
Stop
12-bitOp Amp
ComparatorComparator
DAC
CO=1?
Vc
Cross Zero?
Counter
VOS
Vref
CO yes
Stop
Figure 3.18: Offset tuning scheme with operational amplifier inverting-configured
VOS
Vsweep
Vref
VOutVOS
Vsweep
Vref
VOut
Figure 3.19: Setup for auxiliary input design
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0 0.5 1 1.5 2 2.5 3
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.02
utput
Input(V)
Output Sweep
Desired Output Level
Figure 3.20: DC sweep of the auxiliary input
20mV down to less than desired DC output level (0V), which means the chosen size of
auxiliary port can cover the selected offset range. The bias current in this auxiliary port
is 10 times less than that of primary port; the aspect ratio is 8 times less than that in
the primary port. Figure 3.21 shows the pre-layout noise performance of the circuits in
Figure 3.1 and Figure 3.10 with the auxiliary port, just a little difference in noise level.
The detailed offset tuning and zero-crossing detection circuit is shown in Figure
3.22. In this figure, there is a DAC, which consists of a segmented wide-swing 12-
bit R-2R configuration [21] shown in Figure 3.23. The 12-bit counters upper 5 bits
are thermo-coded. This makes the accuracy requirement for 1/2 LSB DNL in a 12-bit
converter to be set by 7-bit matching instead of 12-bit. Such segmentation is also helpful
in reducing the glitch area associated with the changing DAC output. Since the output
of DAC drives a capacitive load, the operational amplifier as a buffer in this DAC is
omitted.
CNT includes a positive edge triggered 2-bit counter, the counters two output
bits are anded to give C1 output. Therefore receiving three clocks after reset, C1 is set
to 1 to enable DAC and disable itself. During this three-clock period D2, which is two
D flip-flops connected in series, stores the comparators initial status and XOR becomes
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100
101
102
103
104
105
106
107
0
1
2
3
4
5
6
7
8
9x 10
-7
Frequency(Hz)
noise
level(v/
(H
z))
W ith Auxi l iary Port
W i thout Auxi l iary Port
Figure 3.21: Noise level with and without auxiliary input
CO
Op Amp
Comparator
1D
1D
DAC
Vref+
Vref-Clr
Clk
Vc
S
CAL
Out
A1
XORD2
Clkin
D1
Clk
Clr
Clk
D1
Clr
ClkC1
CNTClr
Clk
A2En
I1
I2
I3
I4
CO
Op AmpOp Amp
ComparatorComparator
1D
1D
1D1D
1D1D
DAC
Vref+
Vref-Clr
Clk
VcDAC
Vref+
Vref-Clr
Clk
Vc
S
CAL
Out
A1A1
XORD2
Clkin
D1
ClkClkin
D1
Clk
Clr
Clk
D1
Clr
Clk
D1
Clr
Clk
Clr
ClkC1
CNTClr
Clk
A2En
I1
I2
I3
I4
Figure 3.22: Diagram of offset tuning block
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5-bit
Counter
7-bit
Counter
Thermo-
Decoder
31-bit
Register
7-bit
Register R
esistor
S
tring
315
7
38
5-bit
Counter
7-bit
Counter
Thermo-
Decoder
31-bit
Register
7-bit
Register R
esistor
S
tring
315
7
38
Figure 3.23: Connection between counter and DAC
0. If CLK[n-1] comparators output changes from 1 to 0, D2 is still 1 and XOR
gates output becomes 1. Therefore, there is zero crossing for comparator within two
continuous clocks when the XOR equals 1. D1 is a one-bit D flip-flop, which turns off
the clock signal Clkin when offset tuning phase is finished to reduce switching noise
in the chip. Also D1 is used to switch the operational amplifiers output into or out of
the calibration circuit. The Schmidt Trigger is used to reduce the switching noise in the
comparators output.
The timing for the offset tuning is shown in Figure 3.24. At the beginning, a
Clr signal (command to start offset tuning) is activated, all the registers are cleared,
and DAC is disabled. The period of Clr should be long enough for the operational
amplifier and comparators output to become stable. In this figure, the initial output of
the operational amplifier is larger than the reference voltage and the comparators output
is 1. At the time 1, the reset signal is released and the counter CNT begins to count.
The comparators initial status is clocked into D2 at time 2 and the output of the XOR
gate is
0
. This
0
will be kept until comparator changes its output status by having azero crossing. At time 3, which is the third clock edge after the reset signal, the counters
output is set to 1 to disable the counter and enable the DAC. The DAC starts to increase
its output. When the DAC increases its output, the operational amplifier generates a
new output, which is compared with a reference DC voltage through comparator. This
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process continues until at time 4, the operational amplifiers output becomes less than
the reference voltage. At this time, the comparator changes its output to low and D2
is still comparators previous status, which makes the XOR change its status to logical
1
to indicate a zero-crossing. Then A1 is set to
0
to disable the DAC and conclude
the offset tuning process. At the time 5, D1 changes to 1 to switch the operational
amplifiers output back to the circuit and disable Clkin.
Figure 4.11 shows the simulation of the offset tuning. In this simulation, the
operational amplifier works with a single supply voltage with the midpoint voltage at
1.65V. Figure 3.25(a) shows the timing of signal D1 in Figure 3.22. It shows that the
calibration phase is concluded at the time of0.2805s. In Figure 3.25(b), we can see that
the DAC keeps increasing its output until at the time 0.2805s when the output of the
operational amplifier becomes less than the reference voltage. Figure 3.25(c) shows the
waveform of signal CAL in Figure 3.22. This waveform from 0s to 0.2805s resembles
the waveform in Figure 3.20. After the calibration phase, signal CAL becomes float-
ing, and is no longer used. Figure 3.25(d) shows the waveform Out in Figure 3.22.
The signal Out is floating during the time from 0s to 0.2805s. After the time 0.2805s,
the operational amplifiers output is switched back to the Out signal and its value is
close to 1.65V as shown in Figure 3.25(d).
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Clk
_in
Clk
Clr
C1
A1
A1
D1
D2
S XOR
CO
Vc
1
2
3
4
5
OpAmp
Clk
_in
Clk
_in
ClkClk
ClrClr
C1