Ms Mileiko Pgs Drozd

7/31/2019 Ms Mileiko Pgs Drozd

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REPORT ON THE RESULTS OF

INTERNSHIPName: Mileiko Serhii, 5th year master student,

Drozd Myroslav, 1st year postgraduate student.

University: Odessa National Polytechnic University (ONPU).

Place of internship: Newcastle University, Newcastle upon Tyne,

United Kingdom

Date of internship: 17.11.201117.12.2011

Supervisors: Prof. A. Yakovlev, Newcastle University

Prof. A. Drozd, ONPU

TEMPUS PROJECT WORKSHOP1


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The task

1) To get acquainted with the research in the field Energy-Modulated Computing and to connect it with subject of

Diagnostics of Digital Components of Computer Systems.

2) To investigate the errors, which occur in digital componentsin case of using the energy-saving technologies



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Content

2. Restrictions and ways of experiment execution

Research of errors in digital circuits on condition

of low Vdd


1. Introduction. Motivation, goal and structure

4. Estimation of a horizontal error

3. Two types of errors

5. Conclusions


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Motivation

2. This fact can reduce trustworthiness of results and can limit

area application of energy-aware technologies.

Introduction


3. The development of energy-aware technologies requires to

research the nature of faults and errors arising from their use.

1. Power-efficient modes can create conditions for occurrence

of faults increasing amount of erroneous results.


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Goal and structure

The goal of research - to assess the nature of faults and

errors arising from the use of energy-aware technologies


It is necessary to solve the following problems:

To evaluatethe possibilities of carrying out the experiments;

To develop and improve tools for experiments to assess thefaults and errors;

Dynamically plan and carry out experiments, analyzing the

results.

Introduction


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One source of failure in energy-saving technologies is reduction

of power in digital circuits

Tool for experimentsFPGA Altera design kit DE1

Limitations and ways for carrying out the

experiments


The main limitation for the experimentsstand FPGA Altera

design kit does not allow to lower the power of digital circuits


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Assumption of two directions of result distortion

caused by reduction of Vdd

1. Vertical errors caused by approximation of zero and

unit levels.


Two types of errors

2. Horizontal errors caused by deceleration of transient

process in a digital circuit.

Vdd

VddT T


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Imitation of Vdd decrease by shortening a clock

unit of calculation.

1.A circuit for learning a horizontal error

Estimation of a horizontal error


0..65535

1

CLK

MUL

3

16

8 A

B

MUL

2

8 A

8

8

16

16

RG

4

D

C

16

comp

6

A

B

RG

7

D

C

Calculation

and

output of error

amount

8

RG

5

D

C

16

16

32

B

Multiplier 2 is researched on a half of clock unit: CT 1 RG4

Check Multiplier 3 works during a clock unit: CT 1 RG5


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Reducing a duration of impulse by decreasing of its duty cycle.

Frequency F=50 MHz and clock duty cycle DC=10% or F=100 MHz

and DC=20% define =2 nS.

Comparison of errors obtained by two ways


Conclusion:1. Number of errors grows exponentially with reducing a

duration of impulse;

2. Different results for T=2nS in cases of F=50MHz or F=100MHz

Table of

Results

F=50MHz , DC=10% F=100MHz , DC=20%

Error quantity Error % Error quantity Error %

Project # T, nS Total Essential Total Essential Total Essential Total Essential

1, 7 2,0 86 86 0,13 100 114 114 0,17 100

2, 8 1,8 1726 1726 2,63 100 2343 2296 3,58 98,0

3, 9 1,6 12005 10985 18,32 91,50 15127 13938 23,08 92,1

4, 10 1,4 60116 47495 91,7 79,0 61325 46253 93,6 75,4

5, 11 1,2 65050 51271 99,6 78,8 65176 50631 99,5 77,7

6, 12 1,0 65282 51020 99,6 78,2 65343 50952 99,7 78,0


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2. Different results for T=2

nS in cases of F=50

MHzor F=100MHz

10

Changing frequency needs to change the settings of phase

locked loop (PLL) block and recompile the project

Because of this, we have an inexact clock signal

Recompiled project programs FPGA in another way, and

project with a small changes can have a big difference on

FPGA and can have different signal ways length

Reasons

TEMPUS PROJECT WORKSHOP

In spite of this, we can consider the results relatively to the

number of errors


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Factors are formed using counter (direct count). =2 nS.

Values of errors


# Erroneous Correct Error # Erroneous Correct Error # Erroneous Correct Error

1 1220 1420 -0200 11 0840 0A40 -0200 21 1C00 0000 1C00

2 1000 0000 1000 12 1C00 0000 1C00 22 0DA0 0BA0 0200

3 D400 0000 D400 13 3500 1500 2000 23 E000 0000 E000

4 D000 0000 D000 14 2F80 1F80 1000 24 1C00 0000 1C00

5 4000 0000 4000 15 21E0 1FE0 0200 25 5200 3200 2000

6 2E20 3020 -0200 16 4FC0 3FC0 1000 26 1F20 3F20 -2000

7 F000 0000 F000 17 3580 1580 2000 27 5300 3300 2000

8 1C00 0000 1C00 18 35C0 15C0 2000 28 7FA0 5FA0 2000

9 FC00 0000 FC00 19 3640 1640 2000 29 5380 3380 2000

10 1C60 1E60 -0200 20 36C0 16C0 2000 30 1C00 0000 1C00


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Values of errors


Conclusions:Errors coloured red occur when one factor is equal to zero.

Result also must be equal to zero, but isnt. The reasons of these errors are in

transition from the previous result.


1 1220 1420 -0200 11 0840 0A40 -0200 21 1C00 0000 1C00

2 1000 0000 1000 12 1C00 0000 1C00 22 0DA0 0BA0 0200

3 D400 0000 D400 13 3500 1500 2000 23 E000 0000 E000

4 D000 0000 D000 14 2F80 1F80 1000 24 1C00 0000 1C00

5 4000 0000 4000 15 21E0 1FE0 0200 25 5200 3200 2000

6 2E20 3020 -0200 16 4FC0 3FC0 1000 26 1F20 3F20 -2000

7 F000 0000 F000 17 3580 1580 2000 27 5300 3300 2000

8 1C00 0000 1C00 18 35C0 15C0 2000 28 7FA0 5FA0 2000

9 FC00 0000 FC00 19 3640 1640 2000 29 5380 3380 2000

10 1C60 1E60 -0200 20 36C0 16C0 2000 30 1C00 0000 1C00


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Transition error XXFF (XX+1)00

12

This type of errors appears one of the first, and anxiously

distorts the result.

Despite this, the study of such errors will not be superfluous

However, in actual computations such kind of transitions

occurs very seldom

Examination of typical error

TEMPUS PROJECT WORKSHOP


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This error occurs when second factor from the maximum

turns into the minimum, whereas the first factor increases only

by 1.



Assumption: Possibly, error appears due to the fact that

some bits of the previous result, which contains many units do

not have enough time to switch to zero?


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An experiment was conducted to validate this

assumption.

The inputs of the multiplier were served alternately with

two pairs of factors: 00FF and 0100.



The result of the multiplication is always zero, thus there is

no switching in the output of multiplier, and if the assumption

is true, the errors should not occur.


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Results:

1. Errors in the transition from 0 to 0 appeared as often as

other errors of this type.



2. Errors in the transition from 0100 to 00FF manifested

earlier and occurred more often than in the transition from

00FF to 0100.

Conclusion: This type of error does not depend on theprevious result, but depend on the previous input data.

Perhaps this error is typical only for embedded dsp

multiplier in Altera FPGA


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Values of errors



1 1220 1420 -0200 11 0840 0A40 -0200 21 1C00 0000 1C00

2 1000 0000 1000 12 1C00 0000 1C00 22 0DA0 0BA0 0200

3 D400 0000 D400 13 3500 1500 2000 23 E000 0000 E000

4 D000 0000 D000 14 2F80 1F80 1000 24 1C00 0000 1C00

5 4000 0000 4000 15 21E0 1FE0 0200 25 5200 3200 2000

6 2E20 3020 -0200 16 4FC0 3FC0 1000 26 1F20 3F20 -2000

7 F000 0000 F000 17 3580 1580 2000 27 5300 3300 2000

8 1C00 0000 1C00 18 35C0 15C0 2000 28 7FA0 5FA0 2000

9 FC00 0000 FC00 19 3640 1640 2000 29 5380 3380 2000

10 1C60 1E60 -0200 20 36C0 16C0 2000 30 1C00 0000 1C00

Conclusions:Difference between erroneous and correct result always hasonly one

bit equal to 1 and other bits equal to 0. So we can see that these are single arithmetic

errors.

In most cases errors are positive, i. e. erroneous result is higher then correct


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Comparison of results at direct and reverse count


Conclusions:Previous and following results are replaced only for 5 errors

(# ).

Direct count: Total amount of errors88. Negative errors10 (11,4%).

Reverse count: Total amount of errors66. Negative errors14 (21,2%) .

# Factors Correct Erroneous Error Prev. Res. # Factors Correct Erroneous Error Prev. Res.

1 1460 0780 0380 -0400 076C 2 EB3F 39D5 59D5 2000 3AC0

2 2180 1080 3080 2000 105F 3 E93F 3957 5957 2000 3A40

5 4000 0000 C000 C000 3EC1 4 E73F 38D9 58D9 2000 39C0

6 4800 0000 4000 4000 46B9 5 E63F 389A 589A 2000 3980

10 51A0 32A0 72A0 4000 324F=519F 8 DA3F 35A6 55A6 2000 3680=DA40

13 53A0 33E0 53E0 2000 338D=530F 11 CB9F 7E15 3E15 -4000 7EE0=CBA0

37 C1A0 78A0 98A0 2000 77DF=C19F 13 C19F 77DF 37DF -4000 78A0=C1A0

43 CBA0 7EE0 3EE0 -4000 7E15=CB9F 54 539F 338D 538D 2000 33E0=53A0

54 DA40 3680 5680 2000 35A6=DA3F 56 519F 324F 724F 4000 32A0=51A0

88 FE00 0000 4000 4000 FC03 66 1D9F 1203 1003 -0200 1220

Direct count Reverse count

10-56 13-54 37-13 43-11 54-8


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Comparison of essential and negative errors at

direct and reverse count with step 1 and 3


Conclusions: Table shows:

high percent of essential errors in most significant bits (70,2%-95,5%),

low percentof negative errors: 18%-46%, average

irrespectively of direction and step of count.

big difference between results of multipliers

Count

#

M

U

L

Step 1 Step 3

Total Essential Negative Total Essential Negative

Amount

of errors%

Amount

of errors%

Amount

of errors%

Amount

of errors%

Amount

of errors%

Amount

of errors%

Direct

1 9953 15,2 8906 89,5 2041 20,5 5328 24,4 4858 91,2 1428 26,8

2 47980 73,2 33690 70,2 20081 41,9 17278 79,1 13821 80,0 7875 45,6

3 9979 15,2 9102 91,2 3451 34,6 8644 39,6 7757 89,7 3189 36,94 24156 36,9 20795 86,1 10572 43,8 13316 61,0 12047 90,5 4872 36,6

Reverse

1 9937 15,2 9349 94,1 2427 24,4 3260 14,9 3113 95,5 635 19,5

2 35899 54,8 28357 79,0 6486 18,1 18220 83,4 15757 86,5 2481 13,6

3 13142 20,1 12218 93,0 2761 21,0 6398 29,3 5899 92,2 1299 20,3

4 20567 31,4 18298 89,0 5939 28,9 16367 74,9 14555 88,9 5352 32,7

35%, 36% for direct count

21%, 23% for reverse count


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Comparison of positive and negative errors in

process of direct and reverse count


Conclusions: Reduction of T from 2,29 nS down to 1,46 nS

decreases percent of positive errors from 76,6% down to 2,5% and

increases percentof negative errors from 23,4% up to 97,5%

reducing average increment of result from 7777 or 6575 down to -7 or 5.

Count T, nS

Total Positive NegativeAverage

increment

of result by

positive

error

Average

decrement

of result by

negative

error

Average

increment

of result

by errorAmount

of errors%

Amount

of errors%

Amount

of errors%

Direct

2,292 1006 1,54 771 76,6 235 23,4 11369 3985 7777

1,875 5932 9,01 4328 73,0 1604 27,0 7637 2344 4939

1,458 64254 98,4 1596 2,5 62658 97,5 5405 130 -7

Reverse

2,292 1014 1,55 770 75,9 244 24,1 9802 3624 6575

1,875 10962 16,8 8589 78,4 2373 21,6 4455 2582 2932

1,458 64767 99,2 64265 99,2 502 0,76 135 16622 5


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case of random input words


Conclusions: Examination of random input words case confirms

decrease of average increment of result

on condition of T reduction from 2,29 nS down to 1,46 nS.

MUL T, nS

Total (Tot) Positive (Pos) Negative (Neg)Average

increment

of result

by positive

error

Average

decrement

of result by

negative

error

Average

increment

of result

by errorAmount

of errors%

Amount

of errors%

Amount

of errors%

1

2,292 17934 27,4 13353 74,5 4582 25,6 15908 4407 10718

1,875 61890 94,4 49442 79,9 12448 20,10 20118 9804 14100

1,667 65228 99,5 41026 62,9 24202 37,1 20617 14320 7654

1,458 65263 99,6 32622 50,0 32641 50,0 15709 15693 3

2

2,292 27586 42,0 18894 68,5 8691 31,5 8716 3180 4968

1,875 62112 94,8 42707 68,8 19405 31,2 13190 7057 6864

1,667 65263 99,6 32767 50,2 32496 49,8 15980 15673 219

1,458 65257 99,6 32616 50,0 32641 50,0 15714 15695 3


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case of random input words


Conclusions: Examination of random input words case confirms

decrease of average increment of result

on condition of T reduction from 2,29 nS down to 1,46 nS.

0

10

20

30

40

50

60

70

80

90

100

2,3 1,9 1,7 1,5

MUL 1 2

Tot

Pos

Neg

T


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1. Reduction of Vdd can be imitated by cut of clock unit for examination ofhorizontal error

2. Small duration of clock unit defines high percent of essential errors

(in most significant bits) and low percentof negative errors.

Conclusions


5. It is necessary to continue the researches.

3. Reduction of clock unitduration decreases percent of positive errors

andincreases percentof negative errors reducing average

increment of result.

4. The stable results of horizontal error research can be obtained only

in framework of one ALTERA project.


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The work done

1. The subject of Energy-Modulated Computing developed inNewcastle University by prof. A. Yakovlev was studied.

2. We studied the errors arising in the multiplier, which wasbuilt on the FPGA, used in low power modes. Theinvestigations were performed on the Altera DE1 design kit.Because of the inability to lower the level of the energyconsumption in DE1, the digital component was investigatedin conditions of limited computation time. Reducing the

computation time has influence similar to slowing down thecalculations with decreasing power of digital components.

We designed and investigated a scheme in which the resultsof multiplication with reduced computation time werecompared with the correct results. The scheme allows tocount the number of errors and to maintain the correct anderroneous results, when the errors occur, for their analysis.

The experiments were performed with different input dataflows: sequential, reverse sequential, sequential with differentsteps, random. We compared the errors at the outputs ofseveral devices operating in parallel.



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The results of internship

Interests in the diagnosis of digital

components of computer systems were expandedin the area of the Energy-Modulated Computing.

We obtain experience in researching of digital

components in the low power modes. Detected

that errors, which occur in multiplier with limited

computation time, are arithmetic, obtained

depending of the number of positive and negative

errors on the modes of computing time limits.



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Implementation/approbation of the results

The results of research were presented on theInternational Academic Conference of Young

Scientists and students "Modern Information

Technology 2012" and will be published in the

scientific journal Electro-technical systems andcomponents. Furthermore, the results of the

researches will be presented in the Master

student's qualifying work and PHD dissertation.

Ms Mileiko Pgs Drozd

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