Memory Management Unit

Mrs. Shilpa S. Paygude

Architecture of 80386DX

Flexible 32-Bit Microprocessor 8, 16, 32-Bit Data Types 8 General Purpose 32-Bit Registers Very Large Address Space 4 Gigabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size

80386DX Features

Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging 4 Levels of Protection Virtual 8086 Mode Allows Running of 8086

Software in a Protected and Paged System Optimized for System Performance Pipelined Instruction Execution On-Chip Address Translation Caches 20, 25 and 33 MHz Clock

Contd.

No Memory Management Unit Application program size limited to available

memory (RAM) Single tasking environment Segment size maximum 64KB

Previous members in x86 family

Multitasking Protection –Restricted Access to Data , Code

& Stack Secure Access to I/O devices With minimum available memory, execution

of application of any size

Requirements of Efficient working Environment

Real Address Mode

Protected Mode

Virtual 86 Mode

Modes of Operation

Multitasking Protection Virtual Memory- Demand Paging

Protected Mode Features

Microprocessor can execute one instruction at a time

Microprocessor works very fast ( in microseconds ) compared to human response time

Significant Facts

Important Bits

Segmentation Unit : Deals with segments of a program .

Paging Unit : Divides programs in fixed size (4KB) blocks.

Components of MMU

Defines various types of segments with different attributes and provides segment level protection.

Cannot be Disabled.

It converts Logical Address to Linear Address.

Segmentation Unit

Divides a program in fixed sized pages(4KB).

Swaps pages between RAM & secondary device as required.

Provides page level protection.

It converts Linear address to Physical address.

Optional -can be enabled or disabled.

Paging Unit

Virtual / logical address to Linear Address◦ CS : IP Base address + IP Linear address

Linear Address to Physical AddressLinear Address Base address from page table +

offset

Address Translation

Segmentation is one method of memory management.

Segmentation provides the basis for protection.

Segments are used to encapsulate regions of

memory which have common attributes. Segment selectors can be considered the

logical “name” of a program module or data structure

Segmentation

Segments are variable sized blocks of linear addresses which have certain attributes associated with them

There are two main types of ( non system) segments: code and data

Segments are of variable size - as small as 1 byte or as large as 4 gigabytes Base address (32bit) + Offset (32bit)

Linear Address Base address defined in the descriptor by

system

What Are Segments?

A segment is described by a structure – Segment Descriptor

Each segment (Code/data/stack) has a unique descriptor in memory

All descriptors are maintained in a table – Descriptor Table

Segment Registers

GDT (Global Descriptor Table), IDT (Interrupt Descriptor Table), LDT (Local Descriptor Table), TSS (Task State Segment).

System Tables

System Segment Registers

Global Descriptor Table (GDT), & GDTR

Segment Descriptor n

Segment Descriptor 1

Segment Descriptor 0

NULL Descriptor

Base Address

Limit - 1

+

Linear address(32bit)

Segment base address (32 bit)

Offset(32bit)

GDT

GDTR

Selector

Segment register

Details of Registers

Working Environment

How Segment Descriptor is accessed?

The Global Descriptor Table (GDT) contains descriptors which are possibly available to all of the tasks in a system.

The GDT can contain any type of segment descriptor except for descriptors which are

used for servicing interrupts (i.e. interrupt and trap descriptors).

Every Intel386 DX system contains a GDT

Global Descriptor Table

Generally the GDT contains code and data segments used by the operating systems

and task state segments, and descriptors for the LDTs in a system.

GDT contains descriptors for segments which

are common to all tasks

Contd.

LDTs contain descriptors which are associated with a given task.

Generally, operating systems are designed so that each task has a separate LDT. The LDT may contain only code, data, stack,

task gate, and call gate descriptors. There can be 0 or many LDTs.

Local Descriptor Table

The visible portion of the LDT register contains only a 16-bit selector.

This selector refers to a Local Descriptor Table descriptor in the GDT.

LDTs provide a mechanism for isolating a given task's code and data segments from the rest of the operating system

LDTR

Descriptor Table Registers

Non System Segment Descriptor

System Segment Descriptor

Segment Level Protection

Privilege Level-One of the four hierarchical privilege levels. Level 0 is the most privileged level and level

3 is the least privileged. More privileged levels are numerically

smaller than less privileged levels.

Privilege Level

System tables are manipulated by the operating system.

Therefore, the load descriptor table instructions are privileged instructions.

The instructions that can be executed at CPL=0 are privileged instructions.

Privileged Instructions

Memory Map

Paging is another type of memory management useful for virtual memory multitasking operating systems

Freed space of an outgoing task always same as that needed for an incoming task

A page most likely corresponds to only a portion of a module or data structure

Paging

The page directory

The page tables

The page itself (page frame)

Components of the paging mechanism

A uniform size of 4KB for all of the elements simplifies memory allocation and reallocation

schemes, since there is no problem with memory fragmentation.

Protection can further be increased at page level.

Advantages

Linear Address to Physical Address

Directory Entry

Page Table Entry

4KB page

PDBR

Index to Directory

Index to Table Offset in Page

31 22

21 12

11 0

Page Table Directory

Page Table

Page

CR3

Linear Address

Base address

Paging Mechanism

CR3 is the Page Directory Physical Base Address Register. It contains the physical starting address of the Page Directory.

Page Directory is always page aligned.

CR2 is the Page Fault Linear Address register. It holds the 32-bit linear address which caused the last page fault detected

PAGE DESCRIPTOR BASE REGISTER

The Page Directory is 4K bytes long and allows up to 1024 Page Directory Entries.

Each Page Directory Entry contains the address of the next level of tables, the Page Tables and information about the page table.

Page Directory Entry points to Page Table

PAGE DIRECTORY

Page Directory Entry

Each Page Table is 4K bytes and holds up to 1024 Page Table Entries.

Page Table Entries contain the starting address of the page frame and statistical information about the page

Page tables can be shared between tasks and swapped to disks.

PAGE TABLES

Page Table Entry

The paging mechanism distinguishes between two levels of protection: User which corresponds to level 3 of the segmentation based protection, and supervisor which encompasses all of the other protection levels (0, 1, 2).

Programs executing at Level 0, 1 or 2 bypass the page protection, although segmentation based protection is still enforced by the hardware.

Page Level Protection

The U/S and R/W bits are used to provide User/Supervisor and Read/Write protection

for individual pages or for all pages covered by a Page Table Directory Entry

The U/S and R/W bits in the first level Page Directory Table apply to all pages described

by the page table pointed to by that directory

entry.

Bits used for Protection

The U/S and R/W bits in the second level Page Table Entry apply only to the page described by that entry.

The U/S and R/W bits for a given page are obtained by taking the most restrictive of

the U/S and R/W from the Page Directory Table Entries and the Page Table Entries

Page Level Protection

Performance would degrade substantially if the processor was required to access two levels of tables for every memory

reference. Intel386 DX keeps a cache of the most

recently accessed pages, this cache is called the

Translation Lookaside Buffer (TLB).

Translation Lookaside Buffer

The TLB is a four-way set associative 32-entry page table cache.

It automatically keeps the most commonly used Page Table Entries in the processor.

The 32-entry TLB coupled with a 4K page size, results in coverage of 128K bytes of memory addresses.

Translation Lookaside Buffer

Translation Lookaside Buffer

The paging unit hardware receives a 32-bit linear address from the segmentation unit.

The upper 20 linear address bits are compared with all 32 entries in the TLB to determine if there is a match.

If there is a match (i.e. a TLB hit), then the 32-bit physical address is calculated and will be placed on the address bus.

TLB Hit

Intel386 DX will read the appropriate Page Directory Entry. If P = 1 on the Page Directory Entry indicating that the page table is in memory, then the Intel386 DX will read the appropriate Page Table Entry

TLB Miss

Paging Exceptions